From f69356d7cac5a28a24fc8471c2bc0a1100c5b31a Mon Sep 17 00:00:00 2001 From: Edward Wall Date: Tue, 17 Feb 2026 09:52:54 +0100 Subject: [PATCH] corrects the handling of clearing bits in the simulation --- sim/daq_sim.py | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/sim/daq_sim.py b/sim/daq_sim.py index 9eb1724..d4da2ee 100644 --- a/sim/daq_sim.py +++ b/sim/daq_sim.py @@ -261,10 +261,20 @@ with socket.socket(socket.AF_INET, socket.SOCK_STREAM) as s: elif re.fullmatch(r'CC (\d+)', data): counter = int(re.fullmatch(r'CC (\d+)', data).group(1)) num_bits = daq.total_channels - bits = [(counter >> bit) & 1 for bit in range(num_bits - 1, -1, -1)] + # We add 1, as it also includes the time + bits = [(counter >> bit) & 1 for bit in range(0, num_bits + 1)] for ch, bit in enumerate(bits): - if bit: - daq.clearCount(ch) + if ch < 4: + if bit: + daq.clearCount(ch) + + if ch == 4: + if bit: + daq.clearTime() + + if ch > 4: + if bit: + daq.clearCount(ch - 1) send('') elif re.fullmatch(r'TP (\d+(\.\d+)?)', data):