Upload current state of the test

This commit is contained in:
2025-07-24 14:37:49 +02:00
parent 7f8c2e17b0
commit 035591e03b
10 changed files with 14 additions and 9 deletions

0
.gitignore vendored Normal file → Executable file
View File

View File

@@ -150,8 +150,6 @@ class Motor:
def wait_for_done(self):
while not self.read_field('donemoving'):
if self.has_error():
raise MajorState('Record is in MAJOR state!')
time.sleep(0.1)
def has_error(self):

View File

@@ -1,7 +1,7 @@
pvprefix: DRVTESTS
versions:
turboPmac: "mathis_s"
masterMacs: 1.2
masterMacs: "mathis_s"
controllers:
turboPmac1:
ip: "172.28.101.24"

View File

@@ -30,7 +30,7 @@ pmacAsynIPPortConfigure("$(ASYN_PORT)","$(TURBOPMAC1_IP):$(TURBOPMAC1_PORT)")
turboPmacController("$(NAME)","$(ASYN_PORT)",8,$(TURBOPMAC1_BUSYPOLL),$(TURBOPMAC1_IDLEPOLL),1);
turboPmacAxis("$(NAME)",1);
#turboPmacAxis("$(NAME)",5);
turboPmacAxis("$(NAME)",5);
# Set the number of subsequent timeouts
setMaxSubsequentTimeouts("$(NAME)", 20);

0
tests/sinqMotor/masterMacs/__init__.py Normal file → Executable file
View File

View File

@@ -0,0 +1,11 @@
def stop_reset_enable_move_sequence(motor, target):
motor.write_field('stop', 1)
motor.write_field('reseterrorpv', 1)
motor.write_field('enable', 1)
# MasterMACS motors need to be homed after an error reset
motor.write_field('homeforward', 1)
motor.move_and_wait(target)
assert motor.at_target(target)
assert not motor.has_error()

0
tests/sinqMotor/masterMacs/lin1/__init__.py Normal file → Executable file
View File

0
tests/sinqMotor/masterMacs/lin1/conftest.py Normal file → Executable file
View File

View File

@@ -2,7 +2,7 @@
from tests.move import *
from tests.sinqMotor.limits import *
from tests.sinqMotor.common import *
from tests.sinqMotor.masterMacs.common import *
from tests.sinqMotor.turboPmac.reset import reset

View File

@@ -1,7 +1,3 @@
import time
import pytest
def stop_reset_enable_move_sequence(motor, target):
motor.write_field('stop', 1)