Added macros for 32-bit registers

This commit is contained in:
kpetersn
2018-03-22 14:45:02 -05:00
parent 89cf615600
commit ff2ac7196f
2 changed files with 13 additions and 17 deletions
+7 -10
View File
@@ -329,13 +329,10 @@ ANF2Axis::ANF2Axis(ANF2Controller *pC, const char *ANF2ConfName, int axisNo, epi
// Read data that is likely to be stale
getInfo();
// Send the configuration
//status = pC_->writeReg32(axisNo_, CONFIG_MSW, config, DEFAULT_CONTROLLER_TIMEOUT);
// Send the configuration (array)
// assemble the configuration bits; set the start speed to a non-zero value (100), which is required for the configuration to be accepted
confReg_[0] = config;
confReg_[1] = 0x00000064;
confReg_[CONFIGURATION] = config;
confReg_[BASE_SPEED] = 0x00000064;
// Write all the registers
status = pasynInt32ArraySyncIO->write(pasynUserConfWrite_, confReg_, 5, DEFAULT_CONTROLLER_TIMEOUT);
@@ -447,11 +444,11 @@ void ANF2Axis::reconfig()
status = pasynInt32ArraySyncIO->write(pasynUserConfWrite_, confReg, 5, DEFAULT_CONTROLLER_TIMEOUT);
// Construct the new config
confReg[0] = 0x86000000;
confReg[1] = 0x00000064;
//confReg[2] = 0x0;
//confReg[3] = 0x0;
//confReg[4] = 0x0;
confReg[CONFIGURATION] = 0x86000000;
confReg[BASE_SPEED] = 0x00000064;
//confReg[HOME_TIMEOUT] = 0x0;
//confReg[CONFIG_REG_3] = 0x0;
//confReg[CONFIG_REG_4] = 0x0;
epicsThreadSleep(2.0);
getInfo();
+6 -7
View File
@@ -46,13 +46,12 @@ K. Goetze 2014-03-24
// Not used must equal zero #define RESERVED 8
// Not used must equal zero #define RESERVED 9
/*** Output Configuration Registers ***/
#define CONFIG_MSW 0
#define CONFIG_LSW 1
#define BASE_SPD_MSW 2
#define BASE_SPD_LSW 3
#define HOME_TIMEOUT 4
/*** Output Configuration Registers (32-bit) ***/
#define CONFIGURATION 0
#define BASE_SPEED 1
#define HOME_TIMEOUT 2
#define CONFIG_REG_3 3
#define CONFIG_REG_4 4
// No. of controller-specific parameters
#define NUM_ANF2_PARAMS 2