forked from epics_driver_modules/motorBase
Reformatting; tabs to spaces.
This commit is contained in:
Ron Sluiter
+90
-90
@@ -1,11 +1,11 @@
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/*
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FILENAME... drvOms58.h
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USAGE... OMS driver level "include" information that is specific to OMS
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model VME58.
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FILENAME... drvOms58.h
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USAGE... OMS driver level "include" information that is specific to OMS
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model VME58.
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Version: $Revision$
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Modified By: $Author$
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Last Modified: $Date$
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Version: $Revision$
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Modified By: $Author$
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Last Modified: $Date$
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*/
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/*
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@@ -23,16 +23,16 @@ Last Modified: $Date$
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* and (W-31-109-ENG-38) at Argonne National Laboratory.
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*
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* Initial development by:
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* The Controls and Automation Group (AT-8)
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* Ground Test Accelerator
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* Accelerator Technology Division
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* Los Alamos National Laboratory
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* The Controls and Automation Group (AT-8)
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* Ground Test Accelerator
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* Accelerator Technology Division
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* Los Alamos National Laboratory
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*
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* Co-developed with
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* The Controls and Computing Group
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* Accelerator Systems Division
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* Advanced Photon Source
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* Argonne National Laboratory
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* The Controls and Computing Group
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* Accelerator Systems Division
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* Advanced Photon Source
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* Argonne National Laboratory
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*
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* Modification Log:
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* -----------------
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@@ -40,9 +40,9 @@ Last Modified: $Date$
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* .02 11-14-94 jps copy drvOms.c and modify to point to vme58 driver
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* ...
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* .06 12-07-94 jps first released version w/interrupt supprt
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* .07 12-20-94 jps rearrange the device init routines
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* .07 12-20-94 jps rearrange the device init routines
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* .08 05-03-96 jps convert 32bit card accesses to 16bit - vme58PCB
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* version D does not support 32bit accesses.
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* version D does not support 32bit accesses.
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* .09 05-09-97 jps increase maximum card count to 15
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* .10 08-22-01 rls "int" type specifications for all bit-fields.
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* .11 03-21-05 rls replace VxWorks specific "uint16_t" with "epicsUInt16".
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@@ -63,7 +63,7 @@ Last Modified: $Date$
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#define OMS_NUM_ADDRS 0x4000
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#define OMS_BRD_SIZE 0x1000 /* card address boundary */
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#define BUFFER_SIZE 256
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#define BUFFER_SIZE 256
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/* Board control register structures */
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@@ -91,14 +91,14 @@ typedef union
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epicsUInt8 All;
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struct
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{
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unsigned int intReqEna :1; /* Master interrupt request enable */
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unsigned int ioIntEna :1; /* I/O bits 0 and 1 interrupt enable */
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unsigned int directInEna:1; /* Interrupt request to the VME58 ? */
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unsigned int doneIntEna :1; /* Done detect interrupt enable */
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unsigned int otIntEna :1; /* Overtravel detect interrupt enable */
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unsigned int slipIntEna :1; /* Encoder slip detect interrupt enable */
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unsigned int :1; /* Unused */
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unsigned int update :1; /* Data area update request */
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unsigned int intReqEna :1; /* Master interrupt request enable */
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unsigned int ioIntEna :1; /* I/O bits 0 and 1 interrupt enable */
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unsigned int directInEna:1; /* Interrupt request to the VME58 ? */
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unsigned int doneIntEna :1; /* Done detect interrupt enable */
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unsigned int otIntEna :1; /* Overtravel detect interrupt enable */
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unsigned int slipIntEna :1; /* Encoder slip detect interrupt enable */
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unsigned int :1; /* Unused */
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unsigned int update :1; /* Data area update request */
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} Bits;
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} CNTRL_REG;
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@@ -108,14 +108,14 @@ typedef union
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epicsUInt8 All;
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struct
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{
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unsigned int interrupt :1; /* Interrupt dectect */
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unsigned int directIn :1; /* Direct input interrupt detect */
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unsigned int directOut :1; /* Direct ouput interrupt detect */
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unsigned int done :1; /* Motion done detect */
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unsigned int overtravel :1; /* Overtravel detect */
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unsigned int encoderSlip:1; /* Encoder slip detect */
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unsigned int cardOK :1; /* Powerup initilization complete */
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unsigned int cmndError :1; /* Command error dectect */
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unsigned int interrupt :1; /* Interrupt dectect */
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unsigned int directIn :1; /* Direct input interrupt detect */
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unsigned int directOut :1; /* Direct ouput interrupt detect */
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unsigned int done :1; /* Motion done detect */
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unsigned int overtravel :1; /* Overtravel detect */
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unsigned int encoderSlip:1; /* Encoder slip detect */
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unsigned int cardOK :1; /* Powerup initilization complete */
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unsigned int cmndError :1; /* Command error dectect */
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} Bits;
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} STATUS_REG;
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@@ -125,14 +125,14 @@ typedef union
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epicsUInt8 All;
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struct
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{
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unsigned int io_7 :1; /* Bit 7 */
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unsigned int io_6 :1; /* Bit 6 */
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unsigned int io_5 :1; /* Bit 5 */
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unsigned int io_4 :1; /* Bit 4 */
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unsigned int io_3 :1; /* Bit 3 */
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unsigned int io_2 :1; /* Bit 2 */
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unsigned int io_1 :1; /* Bit 1 */
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unsigned int io_0 :1; /* Bit 0 */
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unsigned int io_7 :1; /* Bit 7 */
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unsigned int io_6 :1; /* Bit 6 */
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unsigned int io_5 :1; /* Bit 5 */
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unsigned int io_4 :1; /* Bit 4 */
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unsigned int io_3 :1; /* Bit 3 */
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unsigned int io_2 :1; /* Bit 2 */
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unsigned int io_1 :1; /* Bit 1 */
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unsigned int io_0 :1; /* Bit 0 */
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} Bits;
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} IO_LOW_REG;
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@@ -142,14 +142,14 @@ typedef union
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epicsUInt8 All;
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struct
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{
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unsigned int slip_s :1; /* status of S axis */
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unsigned int slip_r :1; /* status of R axis */
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unsigned int slip_v :1; /* status of V axis */
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unsigned int slip_u :1; /* status of U axis */
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unsigned int slip_t :1; /* status of T axis */
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unsigned int slip_z :1; /* status of Z axis */
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unsigned int slip_y :1; /* status of Y axis */
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unsigned int slip_x :1; /* status of X axis */
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unsigned int slip_s :1; /* status of S axis */
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unsigned int slip_r :1; /* status of R axis */
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unsigned int slip_v :1; /* status of V axis */
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unsigned int slip_u :1; /* status of U axis */
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unsigned int slip_t :1; /* status of T axis */
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unsigned int slip_z :1; /* status of Z axis */
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unsigned int slip_y :1; /* status of Y axis */
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unsigned int slip_x :1; /* status of X axis */
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} Bits;
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} SLIP_REG;
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@@ -159,14 +159,14 @@ typedef union
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epicsUInt8 All;
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struct
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{
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unsigned int done_s :1; /* status of S axis */
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unsigned int done_r :1; /* status of R axis */
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unsigned int done_v :1; /* status of V axis */
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unsigned int done_u :1; /* status of U axis */
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unsigned int done_t :1; /* status of T axis */
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unsigned int done_z :1; /* status of Z axis */
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unsigned int done_y :1; /* status of Y axis */
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unsigned int done_x :1; /* status of X axis */
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unsigned int done_s :1; /* status of S axis */
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unsigned int done_r :1; /* status of R axis */
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unsigned int done_v :1; /* status of V axis */
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unsigned int done_u :1; /* status of U axis */
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unsigned int done_t :1; /* status of T axis */
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unsigned int done_z :1; /* status of Z axis */
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unsigned int done_y :1; /* status of Y axis */
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unsigned int done_x :1; /* status of X axis */
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} Bits;
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} DONE_REG;
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@@ -176,14 +176,14 @@ typedef union
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epicsUInt8 All;
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struct
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{
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unsigned int :1; /* Unused */
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unsigned int :1; /* Unused */
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unsigned int io_13 :1; /* Bit 13 */
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unsigned int io_12 :1; /* Bit 12 */
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unsigned int io_11 :1; /* Bit 11 */
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unsigned int io_10 :1; /* Bit 10 */
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unsigned int io_9 :1; /* Bit 9 */
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unsigned int io_8 :1; /* Bit 8 */
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unsigned int :1; /* Unused */
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unsigned int :1; /* Unused */
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unsigned int io_13 :1; /* Bit 13 */
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unsigned int io_12 :1; /* Bit 12 */
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unsigned int io_11 :1; /* Bit 11 */
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unsigned int io_10 :1; /* Bit 10 */
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unsigned int io_9 :1; /* Bit 9 */
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unsigned int io_8 :1; /* Bit 8 */
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} Bits;
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} IO_HIGH_REG;
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@@ -194,14 +194,14 @@ typedef union
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epicsUInt8 All;
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struct
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{
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unsigned int limit_s :1; /* status of S axis */
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unsigned int limit_r :1; /* status of R axis */
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unsigned int limit_v :1; /* status of V axis */
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unsigned int limit_u :1; /* status of U axis */
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unsigned int limit_t :1; /* status of T axis */
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unsigned int limit_z :1; /* status of Z axis */
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unsigned int limit_y :1; /* status of Y axis */
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unsigned int limit_x :1; /* status of X axis */
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unsigned int limit_s :1; /* status of S axis */
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unsigned int limit_r :1; /* status of R axis */
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unsigned int limit_v :1; /* status of V axis */
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unsigned int limit_u :1; /* status of U axis */
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unsigned int limit_t :1; /* status of T axis */
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unsigned int limit_z :1; /* status of Z axis */
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unsigned int limit_y :1; /* status of Y axis */
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unsigned int limit_x :1; /* status of X axis */
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} Bits;
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} LIMIT_REG;
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@@ -211,37 +211,37 @@ typedef union
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epicsUInt8 All;
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struct
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{
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unsigned int home_s :1; /* status of S axis */
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unsigned int home_r :1; /* status of R axis */
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unsigned int home_v :1; /* status of V axis */
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unsigned int home_u :1; /* status of U axis */
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unsigned int home_t :1; /* status of T axis */
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unsigned int home_z :1; /* status of Z axis */
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unsigned int home_y :1; /* status of Y axis */
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unsigned int home_x :1; /* status of X axis */
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unsigned int home_s :1; /* status of S axis */
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unsigned int home_r :1; /* status of R axis */
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unsigned int home_v :1; /* status of V axis */
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unsigned int home_u :1; /* status of U axis */
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unsigned int home_t :1; /* status of T axis */
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unsigned int home_z :1; /* status of Z axis */
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unsigned int home_y :1; /* status of Y axis */
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unsigned int home_x :1; /* status of X axis */
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} Bits;
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} HOME_REG;
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typedef struct
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{
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epicsUInt8 unused00;
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epicsUInt8 cntrlReg; /* Control Register - Read/Write */
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epicsUInt8 cntrlReg; /* Control Register - Read/Write */
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epicsUInt8 unused02;
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epicsUInt8 statusReg; /* Status Register - Read */
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epicsUInt8 statusReg; /* Status Register - Read */
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epicsUInt8 unused04;
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epicsUInt8 ioLowReg; /* IO bits 0-7 status register - Read */
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epicsUInt8 ioLowReg; /* IO bits 0-7 status register - Read */
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epicsUInt8 unused06;
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epicsUInt8 slipReg; /* Encoder slip status register - Read */
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epicsUInt8 slipReg; /* Encoder slip status register - Read */
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epicsUInt8 unused08;
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epicsUInt8 doneReg; /* Axis done status register - Read */
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epicsUInt8 doneReg; /* Axis done status register - Read */
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epicsUInt8 unused0A;
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epicsUInt8 ioHighReg; /* IO bits 8-13 status register - Read */
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epicsUInt8 ioHighReg; /* IO bits 8-13 status register - Read */
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epicsUInt8 unused0C;
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epicsUInt8 limitReg; /* Limit switch status register - Read */
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epicsUInt8 limitReg; /* Limit switch status register - Read */
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epicsUInt8 unused0E;
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epicsUInt8 homeReg; /* Home switch status register - Read */
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epicsUInt8 homeReg; /* Home switch status register - Read */
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epicsUInt8 unusedF0;
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epicsUInt8 intVector; /* Interrupt vector */
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epicsUInt8 intVector; /* Interrupt vector */
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} MOTOR_CNTRL_REGS;
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