forked from epics_driver_modules/motorBase
Added OMS MAXv device driver.
This commit is contained in:
Ron Sluiter
@@ -0,0 +1,109 @@
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/*
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FILENAME... devMAXV.cc
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USAGE... Device level support for OMS MAXv model.
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Version: $Revision: 1.1 $
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Modified By: $Author: sluiter $
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Last Modified: $Date: 2004-06-21 21:42:30 $
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*/
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/*
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* Original Author: Ron Sluiter
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* Date: 04/05/04
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* Current Author: Ron Sluiter
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*
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* Experimental Physics and Industrial Control System (EPICS)
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*
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* Copyright 1991, the Regents of the University of California,
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* and the University of Chicago Board of Governors.
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*
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* This software was produced under U.S. Government contracts:
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* (W-7405-ENG-36) at the Los Alamos National Laboratory,
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* and (W-31-109-ENG-38) at Argonne National Laboratory.
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*
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* Initial development by:
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* The Controls and Automation Group (AT-8)
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* Ground Test Accelerator
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* Accelerator Technology Division
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* Los Alamos National Laboratory
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*
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* Co-developed with
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* The Controls and Computing Group
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* Accelerator Systems Division
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* Advanced Photon Source
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* Argonne National Laboratory
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*
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* Modification Log:
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* -----------------
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* .01 04-05-05 rls Copied from devOms58.cc
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*/
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#include "motorRecord.h"
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#include "devOmsCom.h"
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#include "epicsExport.h"
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extern int MAXv_num_cards;
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extern struct driver_table MAXv_access;
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/* ----------------Create the dsets for devMAXv----------------- */
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static long MAXv_init(void *);
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static long MAXv_init_record(void *);
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static long MAXv_start_trans(struct motorRecord *);
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static RTN_STATUS MAXv_end_trans(struct motorRecord *);
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struct motor_dset devMAXv =
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{
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{8, NULL, MAXv_init, MAXv_init_record, NULL},
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motor_update_values,
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MAXv_start_trans,
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oms_build_trans,
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MAXv_end_trans
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};
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epicsExportAddress(dset,devMAXv);
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static struct board_stat **MAXv_cards;
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static const char errmsg[] = {"\n\n!!!ERROR!!! - Oms MAXv driver uninitialized.\n"};
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static long MAXv_init(void *arg)
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{
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int after = (int) arg;
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if (*(MAXv_access.init_indicator) == NO)
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{
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errlogSevPrintf(errlogMinor, "%s", errmsg);
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return(ERROR);
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}
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else
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return(motor_init_com(after, MAXv_num_cards, &MAXv_access, &MAXv_cards));
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}
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static long MAXv_init_record(void *arg)
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{
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struct motorRecord *mr = (struct motorRecord *) arg;
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return(motor_init_record_com(mr, MAXv_num_cards, &MAXv_access, MAXv_cards));
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}
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static long MAXv_start_trans(struct motorRecord *mr)
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{
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struct motor_trans *trans;
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long rtnval;
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rtnval = motor_start_trans_com(mr, MAXv_cards);
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/* Initialize a STOP_AXIS command termination string pointer. */
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trans = (struct motor_trans *) mr->dpvt;
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trans->motor_call.termstring = " ID";
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return(rtnval);
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}
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static RTN_STATUS MAXv_end_trans(struct motorRecord *mr)
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{
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if (*(MAXv_access.init_indicator) == NO)
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{
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errlogSevPrintf(errlogMinor, "%s", errmsg);
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return(ERROR);
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}
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else
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return(motor_end_trans_com(mr, &MAXv_access));
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}
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,182 @@
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/*
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FILENAME... drvMAXv.h
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USAGE... OMS driver level "include" information that is specific to OMS
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model MAXv.
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Version: $Revision: 1.1 $
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Modified By: $Author: sluiter $
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Last Modified: $Date: 2004-06-21 21:42:31 $
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*/
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/*
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* Original Author: Ron Sluiter
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* Date: 04/05/04
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* Current Author: Ron Sluiter
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*
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* Experimental Physics and Industrial Control System (EPICS)
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*
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* Copyright 1991, the Regents of the University of California,
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* and the University of Chicago Board of Governors.
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*
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* This software was produced under U.S. Government contracts:
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* (W-7405-ENG-36) at the Los Alamos National Laboratory,
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* and (W-31-109-ENG-38) at Argonne National Laboratory.
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*
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* Initial development by:
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* The Controls and Automation Group (AT-8)
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* Ground Test Accelerator
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* Accelerator Technology Division
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* Los Alamos National Laboratory
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*
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* Co-developed with
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* The Controls and Computing Group
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* Accelerator Systems Division
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* Advanced Photon Source
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* Argonne National Laboratory
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*
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* Modification Log:
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* -----------------
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* 01 04-05-04 rls Copied for drvOms58.h
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*
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*/
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#ifndef INCdrvMAXvh
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#define INCdrvMAXvh 1
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#include "drvOmsCom.h"
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/*
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* MAXv default profile
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*/
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#define MAXv_NUM_CARDS 15
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#define MAXv_BRD_SIZE 0x1000 /* card address boundary */
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#define BUFFER_SIZE 1024
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/* MAXv DUAL-PORT MEMORY MAP */
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/* Limit Switch Status - Offset = 0x40 */
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typedef union
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{
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epicsUInt32 All;
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struct
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{
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unsigned int s_minus :1;
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unsigned int r_minus :1;
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unsigned int v_minus :1;
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unsigned int u_minus :1;
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unsigned int t_minus :1;
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unsigned int z_minus :1;
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unsigned int y_minus :1;
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unsigned int x_minus :1;
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unsigned int s_plus :1;
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unsigned int r_plus :1;
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unsigned int v_plus :1;
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unsigned int u_plus :1;
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unsigned int t_plus :1;
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unsigned int z_plus :1;
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unsigned int y_plus :1;
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unsigned int x_plus :1;
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} Bits;
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} LIMIT_SWITCH;
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/* Home Switch Status - Offset = 0x44 */
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typedef union
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{
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epicsUInt32 All;
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struct
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{
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unsigned int home_s :1; /* status of S axis */
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unsigned int home_r :1; /* status of R axis */
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unsigned int home_v :1; /* status of V axis */
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unsigned int home_u :1; /* status of U axis */
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unsigned int home_t :1; /* status of T axis */
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unsigned int home_z :1; /* status of Z axis */
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unsigned int home_y :1; /* status of Y axis */
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unsigned int home_x :1; /* status of X axis */
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} Bits;
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} HOME_SWITCH;
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/* Firmware status - Offset = 0x48 */
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typedef union
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{
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epicsUInt32 All;
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struct
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{
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unsigned int na19 :13; /* N/A bits 19-31 */
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unsigned int factoryparm_loaded :1;
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unsigned int altparm_loaded :1;
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unsigned int defaultparm_loaded :1;
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unsigned int altprgm_err :1;
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unsigned int altparm_chksum_err :1;
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unsigned int prgm_err :1;
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unsigned int parm_chksum_err :1;
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unsigned int na10 :2; /* N/A bits 10-11 */
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unsigned int program_error :1;
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unsigned int flash_chksum_err :1;
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unsigned int na3 :5; /* N/A bits 3-7 */
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unsigned int running :1;
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unsigned int initalizing :1;
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unsigned int not_downloaded :1;
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} Bits;
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} FIRMWARE_STATUS;
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/* Status#1 - Offset = 0xFC0 */
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typedef union
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{
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epicsUInt32 All;
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struct
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{
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unsigned int na3 :5; /* N/A bits 3 to 7. */
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unsigned int data_avail :1;
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unsigned int text_response :1;
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unsigned int cmndError :1; /* Command error dectect */
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unsigned int slip :8;
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unsigned int overtravel :8;
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unsigned int done :8;
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} Bits;
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} STATUS1;
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/* OMS VME dual port memory map */
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struct MAXv_motor
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{
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epicsUInt32 cmndPos[8];
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epicsUInt32 encPos[8];
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LIMIT_SWITCH limit_switch;
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HOME_SWITCH home_switch;
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FIRMWARE_STATUS firmware_status;
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epicsUInt32 direct_cmnd_mbox;
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epicsUInt32 position_req_mbox;
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epicsUInt32 coherent_cmndPos[8];
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epicsUInt32 coherent_encPos[8];
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epicsUInt32 msg_semaphore;
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epicsUInt32 queue_flush_mbox;
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epicsUInt32 gpio;
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epicsUInt32 naA0[19]; /* N/A byte offset 0xA0 - 0xEB. */
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epicsUInt32 flash_pgm_ptr;
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epicsUInt32 outPutIndex;
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epicsUInt32 outGetIndex;
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epicsUInt32 inPutIndex;
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epicsUInt32 inGetIndex;
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epicsUInt8 outBuffer[BUFFER_SIZE];
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epicsUInt8 inBuffer[BUFFER_SIZE];
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epicsUInt8 utility[BUFFER_SIZE];
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epicsUInt32 naD00[176]; /* N/A byte offset 0xD00 - 0xFBF. */
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STATUS1 status1_flag;
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epicsUInt32 status1_irq_enable;
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epicsUInt32 status2_flag;
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epicsUInt32 status2_irq_enable;
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epicsUInt32 IACK_vector;
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epicsUInt32 config_switch;
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epicsUInt32 AM_register;
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epicsUInt32 naFDC[7];
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epicsUInt32 FIFO_status_cntrl;
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epicsUInt32 FIFO_date;
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};
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#endif /* INCdrvMAXvh */
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