forked from epics_driver_modules/motorBase
Set svn ignore and eol properties.
This commit is contained in:
@@ -1,23 +1,23 @@
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/* Hy8601Main.cpp */
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/* Author: Marty Kraimer Date: 17MAR2000 */
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#include <stddef.h>
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#include <stdlib.h>
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#include <stddef.h>
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#include <string.h>
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#include <stdio.h>
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#include "epicsExit.h"
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#include "epicsThread.h"
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#include "iocsh.h"
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int main(int argc,char *argv[])
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{
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if(argc>=2) {
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iocsh(argv[1]);
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epicsThreadSleep(.2);
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}
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iocsh(NULL);
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epicsExit(0);
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return(0);
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}
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/* Hy8601Main.cpp */
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/* Author: Marty Kraimer Date: 17MAR2000 */
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#include <stddef.h>
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#include <stdlib.h>
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#include <stddef.h>
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#include <string.h>
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#include <stdio.h>
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#include "epicsExit.h"
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#include "epicsThread.h"
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#include "iocsh.h"
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int main(int argc,char *argv[])
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{
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if(argc>=2) {
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iocsh(argv[1]);
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epicsThreadSleep(.2);
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}
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iocsh(NULL);
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epicsExit(0);
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return(0);
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}
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+1135
-1135
File diff suppressed because it is too large
Load Diff
@@ -1,7 +1,7 @@
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# Database Definition
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registrar(Hy8601AsynRegister)
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driver(drvHy8601Asyn)
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#registrar(xy9660Registrar)
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registrar(Hy8002Registrar)
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# Database Definition
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registrar(Hy8601AsynRegister)
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driver(drvHy8601Asyn)
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#registrar(xy9660Registrar)
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registrar(Hy8002Registrar)
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@@ -1,79 +1,79 @@
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#ifndef DRV_HY8601_H
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#define DRV_HY8601_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DEVICE_NAME "drvHy8601Asyn"
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/* CSR Register bit definitions */
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#define CSR_HOMESTOP 0x8000
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#define CSR_INTEN 0x4000
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#define CSR_DONE 0x2000
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#define CSR_CRASHSTOP 0x1000
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#define CSR_DIRECTION 0x0800
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#define CSR_AUX2 0x0400
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#define CSR_AUX1 0x0200
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#define CSR_ENCODUSE 0x0100
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#define CSR_ENCODDET 0x0080
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#define CSR_JOG 0x0040
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#define CSR_GO 0x0020
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#define CSR_DRVSTAT 0x0010
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#define CSR_HOMELMT 0x0008
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#define CSR_MAXLMT 0x0004
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#define CSR_MINLMT 0x0002
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#define CSR_RESET 0x0001
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/* New Hardware Register Map */
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#define REG_STEPCNTLO 0x00
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#define REG_STEPCNTHI 0x02
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#define REG_CURRPOSLO 0x04
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#define REG_CURRPOSHI 0x06
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#define REG_STARTSTOPSPD 0x08
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#define REG_HIGHSPD 0x0A
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#define REG_RAMPRATE 0x0C
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#define REG_CSR 0x0E
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#define REG_INTMASK 0x10
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#define REG_INTVECTOR 0x12
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#define REG_INTREQUEST 0x14
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#define REG_CURRENTSPD 0x16
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#define REG_SPARE1 0x18
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#define REG_SPARE2 0x1A
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#define REG_SPARE3 0x1C
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#define REG_SPARE4 0x1E
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#define PROM_MODEL 0x8601
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#define PROM_OFFS 0x80
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#define REG_BANK_OFFS 0x00
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#define REG_BANK_SZ 0x20
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#define INT_LMT (CSR_MINLMT | CSR_MAXLMT | CSR_HOMELMT)
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#define INT_SRCS (CSR_RESET | INT_LMT | CSR_DRVSTAT | CSR_DONE)
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/* define a mask to enable all sources of interrupts */
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#define ALL_INTS (INT_SRCS | CSR_INTEN)
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#define DONE_INT (CSR_DONE) /* the only interrupt suggested to use. JC 12-Nov-2009 */
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#define HY8601_NUM_AXES 4
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#define IP_DETECT_STR "VITA4 "
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#define GET_REG(base,reg) (*(volatile epicsUInt16 *)((base)+(reg)))
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#define SET_REG(base,reg,val) do { *(volatile epicsUInt16 *)((base)+(reg)) = (val);} while(0)
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#define CSR_SET(base,bit) do { *(volatile epicsUInt16 *)((base)+REG_CSR) |= (bit);} while(0)
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#define CSR_CLR(base,bit) do { *(volatile epicsUInt16 *)((base)+REG_CSR) &= ~(bit);} while(0)
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int drvHy8601AsynCreate( char *port, int addr, int card, int nAxes );
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int Hy8601Configure(int cardnum,
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int ip_carrier,
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int ipslot,
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int vector,
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int useencoder,
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int limitmode);
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#ifdef __cplusplus
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}
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#endif
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#endif
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#ifndef DRV_HY8601_H
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#define DRV_HY8601_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DEVICE_NAME "drvHy8601Asyn"
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/* CSR Register bit definitions */
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#define CSR_HOMESTOP 0x8000
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#define CSR_INTEN 0x4000
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#define CSR_DONE 0x2000
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#define CSR_CRASHSTOP 0x1000
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#define CSR_DIRECTION 0x0800
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#define CSR_AUX2 0x0400
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#define CSR_AUX1 0x0200
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#define CSR_ENCODUSE 0x0100
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#define CSR_ENCODDET 0x0080
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#define CSR_JOG 0x0040
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#define CSR_GO 0x0020
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#define CSR_DRVSTAT 0x0010
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#define CSR_HOMELMT 0x0008
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#define CSR_MAXLMT 0x0004
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#define CSR_MINLMT 0x0002
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#define CSR_RESET 0x0001
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/* New Hardware Register Map */
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#define REG_STEPCNTLO 0x00
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#define REG_STEPCNTHI 0x02
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#define REG_CURRPOSLO 0x04
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#define REG_CURRPOSHI 0x06
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#define REG_STARTSTOPSPD 0x08
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#define REG_HIGHSPD 0x0A
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#define REG_RAMPRATE 0x0C
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#define REG_CSR 0x0E
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#define REG_INTMASK 0x10
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#define REG_INTVECTOR 0x12
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#define REG_INTREQUEST 0x14
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#define REG_CURRENTSPD 0x16
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#define REG_SPARE1 0x18
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#define REG_SPARE2 0x1A
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#define REG_SPARE3 0x1C
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#define REG_SPARE4 0x1E
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#define PROM_MODEL 0x8601
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#define PROM_OFFS 0x80
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#define REG_BANK_OFFS 0x00
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#define REG_BANK_SZ 0x20
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#define INT_LMT (CSR_MINLMT | CSR_MAXLMT | CSR_HOMELMT)
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#define INT_SRCS (CSR_RESET | INT_LMT | CSR_DRVSTAT | CSR_DONE)
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/* define a mask to enable all sources of interrupts */
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#define ALL_INTS (INT_SRCS | CSR_INTEN)
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#define DONE_INT (CSR_DONE) /* the only interrupt suggested to use. JC 12-Nov-2009 */
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#define HY8601_NUM_AXES 4
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#define IP_DETECT_STR "VITA4 "
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#define GET_REG(base,reg) (*(volatile epicsUInt16 *)((base)+(reg)))
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#define SET_REG(base,reg,val) do { *(volatile epicsUInt16 *)((base)+(reg)) = (val);} while(0)
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#define CSR_SET(base,bit) do { *(volatile epicsUInt16 *)((base)+REG_CSR) |= (bit);} while(0)
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#define CSR_CLR(base,bit) do { *(volatile epicsUInt16 *)((base)+REG_CSR) &= ~(bit);} while(0)
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int drvHy8601AsynCreate( char *port, int addr, int card, int nAxes );
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int Hy8601Configure(int cardnum,
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int ip_carrier,
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int ipslot,
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int vector,
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int useencoder,
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int limitmode);
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#ifdef __cplusplus
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}
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#endif
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#endif
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@@ -1,45 +1,45 @@
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/* This is the EPICS dependent code for the Hytec 8601 Step motor driver.
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* By making this separate file for the EPICS dependent code the driver itself
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* only needs libCom from EPICS for OS-independence (i.e. it is then possible to create
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* module tests without needing to load the entire EPICS libraries!)
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*/
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#include <iocsh.h>
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#include <drvSup.h>
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#include <epicsExport.h>
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#include "drvHy8601Asyn.h"
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/* Code for iocsh registration */
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/* Hy8601Config */
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static const iocshArg Hy8601ConfigArg0 = {"cardnum", iocshArgInt};
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static const iocshArg Hy8601ConfigArg1 = {"carrier", iocshArgInt};
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static const iocshArg Hy8601ConfigArg2 = {"ipslot", iocshArgInt};
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static const iocshArg Hy8601ConfigArg3 = {"vector", iocshArgInt};
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static const iocshArg Hy8601ConfigArg4 = {"useencoder", iocshArgInt};
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static const iocshArg Hy8601ConfigArg5 = {"limitmode", iocshArgInt};
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static const iocshArg * const Hy8601ConfigArgs[] = {&Hy8601ConfigArg0,
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&Hy8601ConfigArg1,
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&Hy8601ConfigArg2,
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&Hy8601ConfigArg3,
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&Hy8601ConfigArg4,
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&Hy8601ConfigArg5};
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static const iocshFuncDef configHy8601 = {"Hy8601AsynConfig", 6, Hy8601ConfigArgs};
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static void configHy8601CallFunc(const iocshArgBuf *args)
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{
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Hy8601Configure(args[0].sval, args[1].ival, args[2].ival, args[3].ival, args[4].ival, args[5].ival);
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}
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static void Hy8601AsynRegister(void)
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{
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iocshRegister(&configHy8601, configHy8601CallFunc);
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}
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epicsExportRegistrar(Hy8601AsynRegister);
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/* This is the EPICS dependent code for the Hytec 8601 Step motor driver.
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* By making this separate file for the EPICS dependent code the driver itself
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* only needs libCom from EPICS for OS-independence (i.e. it is then possible to create
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* module tests without needing to load the entire EPICS libraries!)
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*/
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#include <iocsh.h>
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#include <drvSup.h>
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#include <epicsExport.h>
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#include "drvHy8601Asyn.h"
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/* Code for iocsh registration */
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/* Hy8601Config */
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static const iocshArg Hy8601ConfigArg0 = {"cardnum", iocshArgInt};
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static const iocshArg Hy8601ConfigArg1 = {"carrier", iocshArgInt};
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static const iocshArg Hy8601ConfigArg2 = {"ipslot", iocshArgInt};
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static const iocshArg Hy8601ConfigArg3 = {"vector", iocshArgInt};
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static const iocshArg Hy8601ConfigArg4 = {"useencoder", iocshArgInt};
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static const iocshArg Hy8601ConfigArg5 = {"limitmode", iocshArgInt};
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static const iocshArg * const Hy8601ConfigArgs[] = {&Hy8601ConfigArg0,
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&Hy8601ConfigArg1,
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&Hy8601ConfigArg2,
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&Hy8601ConfigArg3,
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&Hy8601ConfigArg4,
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&Hy8601ConfigArg5};
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static const iocshFuncDef configHy8601 = {"Hy8601AsynConfig", 6, Hy8601ConfigArgs};
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static void configHy8601CallFunc(const iocshArgBuf *args)
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{
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Hy8601Configure(args[0].sval, args[1].ival, args[2].ival, args[3].ival, args[4].ival, args[5].ival);
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}
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static void Hy8601AsynRegister(void)
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{
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iocshRegister(&configHy8601, configHy8601CallFunc);
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}
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epicsExportRegistrar(Hy8601AsynRegister);
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