merged dvx private include file
This commit is contained in:
Jeff Hill
+144
-6
@@ -60,7 +60,7 @@
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* MS 9/20/90 Changed data conversion to offset binary
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* (only test routines affected)
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*
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* JH 7/25/91 added dvx_reset() and dvx_reset() on control X reboot
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* JH 07/25/91 added dvx_reset() and dvx_reset() on control X reboot
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* JH 11/14/91 changed a sysBCLSet to sysIntEnable so ioc_core
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* will load into the nat inst cpu030
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@@ -68,15 +68,21 @@
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* JH 11/14/91 removed sysBCLSet enabling STD non priv and super
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* access since this is already enabled if we are
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* processor 0
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* JH 11/14/91 changed DVX_INTLEV from a mask to a level
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* to support use of sysIntEnable() which
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* is architecture independent
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* BG 4/22/92 added sysBusToLocalAddr() for both short and standard
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* addresses for this module. Moved DVX_ADDR0 to
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* ai_addrs[DVX2502]in module_types.h. Also moved DVX_IVECO
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* to module_types.h.
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* BG 6/23/92 combined dvx_driver.c and drvDvx.c
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* BG 6/26/92 added level to dvx_io_report in drvDvx structure.
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* JH 6/29/92 moved the rest of the dvx io_report here
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* BG 06/26/92 added level to dvx_io_report in drvDvx structure.
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* JH 06/29/92 moved the rest of the dvx io_report here
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* BG 7/2/92 removed the semaphores from dvx_io_report
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* JH 8/5/92 dvx driver init is called from drvDvx now
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* JH 08/03/92 Removed hkv2f dependent base addr
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* JH 08/03/92 moved interrupt vector base to module_types.h
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* JH 08/05/92 dvx driver init is called from drvDvx now
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* JH 08/10/92 merged dvx private include file into this source
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*/
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static char *SccsId = "$Id$\t$Date$";
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@@ -87,8 +93,140 @@ static char *SccsId = "$Id$\t$Date$";
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#include <dbDefs.h>
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#include <drvSup.h>
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#include <module_types.h>
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#include <drvDvx.h>
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/* general constants */
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#define DVX_ID 0xCFF5 /* analogic ID code */
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#define MAX_DVX_CARDS 5 /* max # of 2502 cards per IOC */
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#define MAX_PORTS 3 /* max # of 2601 cards per 2502 */
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#define MAX_CHAN 127 /* max chan when 2601 muxes are used */
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#define DVX_DRATE 0xFFEC /* default scan rate of 184 KHz */
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#define DVX_SRATE 0xF201 /* slow scan used for run away mode */
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#define DVX_RAMSIZE 2048 /* sequence RAM size */
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#define DVX_INTLEV 5 /* interrupt level 5 */
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#define DVX_NBUF 1 /* default # of input buffers */
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/* modes of operation */
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#define INIT_MODE 0 /* initialization mode */
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#define RUN_MODE 1 /* aquisition mode */
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/* self test constants */
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#define TST_RATE 0x3ED /* self test scan rate */
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#define TST_THRESH 0xD00 /* mux card test threshold reg value */
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/* csr command bits */
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#define CSR_RESET 0x01 /* software reset */
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#define CSR_M_START 0x10 /* internal scan start */
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#define CSR_M_ETRIG 0x40 /* external trigger enable */
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#define CSR_M_ESTART 0x20 /* external start enable */
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#define CSR_M_SYSFINH 0x02 /* system fail inhibit */
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#define CSR_M_A24 0x8000 /* enable sequence RAM */
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#define CSR_M_INT 0x80 /* interrupt enable */
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#define CSR_M_MXTST 0x3A /* mux card test bits */
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/* csr status bits */
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#define S_NEPTY 0x02 /* fifo not empty when = 1 */
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/* Sequence Program control codes */
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#define GAIN_CHANNEL 0x80
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#define ADVANCE_TRACK 0x40
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#define ADVANCE_HOLD 0xC0
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#define RESTART 0x00
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/* analogic 2502 memory structure */
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struct dvx_2502
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{
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unsigned short dev_id; /* device id code (CFF5) */
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unsigned short dev_type; /* type code (B100) */
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unsigned short csr; /* control and status register */
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unsigned short seq_offst; /* sequence RAM offset register */
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unsigned short mem_attr; /* memory attribute register */
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unsigned short samp_rate; /* sample rate register */
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unsigned short dma_point; /* DMA pointer register */
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unsigned short dma_data; /* DMA data register */
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unsigned short thresh; /* threshold register */
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unsigned short fifo; /* input fifo */
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unsigned short end_pad[54]; /* pad to 64 byte boundary */
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};
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/* input buffer */
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struct dvx_inbuf
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{
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struct dvx_inbuf *link; /* link to next buffer */
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int wordcnt; /* # of words read to clear fifo */
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short data[512]; /* data buffer */
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};
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/* analogic 2502 control structure */
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struct dvx_rec
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{
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struct dvx_2502 *pdvx2502; /* pointer to device registers */
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short *sr_ptr; /* pointer to sequence RAM */
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struct dvx_inbuf *inbuf; /* pointer to current buffer */
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short unsigned csr_shadow; /* csr shadow register */
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short mode; /* operation mode (init or run) */
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int int_vector; /* interrupt vector */
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int intcnt; /* interrupt count # */
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int cnum; /* card number */
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};
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/* dma chain table size */
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#define DVX_CTBL 34 /* max size of chain table */
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/* am9516 register select constants.
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The DMA control registers are accessed through the dvx2502 registers
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dma_point and dma_data. The constants below are the addresses which must
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be loaded into the pointer register to access the named register through
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the data register. All dual registers are commented as #2. To access channel
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#1, OR the value M_CH1 with the channel #2 address. */
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#define DMA_MMR 0x38 /* master mode register */
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#define DMA_CSR 0x2C /* command/status register #2 */
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#define DMA_CARAH 0x18 /* current address reg A high #2 */
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#define DMA_CARAL 0x08 /* current address reg A low #2 */
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#define DMA_CARBH 0x10 /* current address reg B high #2 */
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#define DMA_CARBL 0x00 /* current address reg B low #2 */
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#define DMA_BARAH 0x1C /* base address reg A high #2 */
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#define DMA_BARAL 0x0C /* base address reg A low #2 */
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#define DMA_BARBH 0x14 /* base address reg B high #2 */
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#define DMA_BARBL 0x04 /* base address reg B low #2 */
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#define DMA_COC 0x30 /* current operation count #2 */
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#define DMA_BOC 0x34 /* base operation count #2 */
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#define DMA_ISR 0x28 /* interrupt save register #2 */
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#define DMA_IVR 0x58 /* interrupt vector register #2 */
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#define DMA_CMRH 0x54 /* channel mode register #2 */
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#define DMA_CMRL 0x50 /* channel mode register #2 */
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#define DMA_CARH 0x24 /* chain address reg high #2 */
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#define DMA_CARL 0x20 /* chain address reg low #2 */
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#define M_CH1 0x2 /* mask for chan 1 reg addresses */
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/* am9516 command constants
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All dual commands are commented as #1. To command channel #2, OR the
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valur M_CH2 with the channel #1 command. */
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#define MMR_ENABLE 0x0D /* chip enable value */
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#define CMR_RESET 0x0 /* reset all channels */
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#define CMR_START 0xA0 /* start channel #1 */
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#define CMR_SSR 0x42 /* set software request #1 */
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#define CMR_CSR 0x40 /* clear software request #1 */
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#define CMR_SHM 0x82 /* set hardware mask #1 */
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#define CMR_CHM 0x80 /* clear hardware mask #1 */
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#define CMR_SC 0x22 /* set CIE/IP #1 */
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#define CMR_CC 0x20 /* clear CIE/IP #1 */
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#define CMR_SFB 0x62 /* set flip bit #1 */
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#define CMR_CFB 0x60 /* clear flip bit #1 */
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#define M_CIE 0x10 /* int enable bit mask (SC/CC cmd) */
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#define M_IP 0x4 /* int pending bit mask (SC/CC cmd) */
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#define M_CH2 0x1 /* mask for channel #2 commands */
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/* am9516 chain reload constants */
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#define R_CAR 0x1 /* chain address */
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#define R_CMR 0x2 /* channel mode */
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#define R_IVR 0x4 /* interrupt vector */
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#define R_PMR 0x8 /* pattern and mask */
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#define R_BOC 0x10 /* base operation count */
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#define R_BAB 0x20 /* base address register B */
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#define R_BAA 0x40 /* base address register A */
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#define R_COC 0x80 /* current operation count */
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#define R_CAB 0x100 /* current address register B */
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#define R_CAA 0x200 /* current address register A */
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/* If any of the following does not exist replace it with #define <> NULL */
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long dvx_io_report();
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@@ -679,7 +817,7 @@ void *lclToA24(void *pLocal)
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void *pA24;
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status = sysLocalToBusAdrs(
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VME_AM_STD_USER_DATA,
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VME_AM_STD_USR_DATA,
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pLocal,
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&pA24);
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if(status<0){
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