diff --git a/src/drv/drvDvx.c b/src/drv/drvDvx.c index 25532fbf8..336c50506 100644 --- a/src/drv/drvDvx.c +++ b/src/drv/drvDvx.c @@ -60,7 +60,7 @@ * MS 9/20/90 Changed data conversion to offset binary * (only test routines affected) * - * JH 7/25/91 added dvx_reset() and dvx_reset() on control X reboot + * JH 07/25/91 added dvx_reset() and dvx_reset() on control X reboot * JH 11/14/91 changed a sysBCLSet to sysIntEnable so ioc_core * will load into the nat inst cpu030 @@ -68,15 +68,21 @@ * JH 11/14/91 removed sysBCLSet enabling STD non priv and super * access since this is already enabled if we are * processor 0 + * JH 11/14/91 changed DVX_INTLEV from a mask to a level + * to support use of sysIntEnable() which + * is architecture independent * BG 4/22/92 added sysBusToLocalAddr() for both short and standard * addresses for this module. Moved DVX_ADDR0 to * ai_addrs[DVX2502]in module_types.h. Also moved DVX_IVECO * to module_types.h. * BG 6/23/92 combined dvx_driver.c and drvDvx.c - * BG 6/26/92 added level to dvx_io_report in drvDvx structure. - * JH 6/29/92 moved the rest of the dvx io_report here + * BG 06/26/92 added level to dvx_io_report in drvDvx structure. + * JH 06/29/92 moved the rest of the dvx io_report here * BG 7/2/92 removed the semaphores from dvx_io_report - * JH 8/5/92 dvx driver init is called from drvDvx now + * JH 08/03/92 Removed hkv2f dependent base addr + * JH 08/03/92 moved interrupt vector base to module_types.h + * JH 08/05/92 dvx driver init is called from drvDvx now + * JH 08/10/92 merged dvx private include file into this source */ static char *SccsId = "$Id$\t$Date$"; @@ -87,8 +93,140 @@ static char *SccsId = "$Id$\t$Date$"; #include #include #include -#include +/* general constants */ +#define DVX_ID 0xCFF5 /* analogic ID code */ +#define MAX_DVX_CARDS 5 /* max # of 2502 cards per IOC */ +#define MAX_PORTS 3 /* max # of 2601 cards per 2502 */ +#define MAX_CHAN 127 /* max chan when 2601 muxes are used */ +#define DVX_DRATE 0xFFEC /* default scan rate of 184 KHz */ +#define DVX_SRATE 0xF201 /* slow scan used for run away mode */ +#define DVX_RAMSIZE 2048 /* sequence RAM size */ +#define DVX_INTLEV 5 /* interrupt level 5 */ +#define DVX_NBUF 1 /* default # of input buffers */ + +/* modes of operation */ +#define INIT_MODE 0 /* initialization mode */ +#define RUN_MODE 1 /* aquisition mode */ + +/* self test constants */ +#define TST_RATE 0x3ED /* self test scan rate */ +#define TST_THRESH 0xD00 /* mux card test threshold reg value */ + +/* csr command bits */ +#define CSR_RESET 0x01 /* software reset */ +#define CSR_M_START 0x10 /* internal scan start */ +#define CSR_M_ETRIG 0x40 /* external trigger enable */ +#define CSR_M_ESTART 0x20 /* external start enable */ +#define CSR_M_SYSFINH 0x02 /* system fail inhibit */ +#define CSR_M_A24 0x8000 /* enable sequence RAM */ +#define CSR_M_INT 0x80 /* interrupt enable */ +#define CSR_M_MXTST 0x3A /* mux card test bits */ + +/* csr status bits */ +#define S_NEPTY 0x02 /* fifo not empty when = 1 */ + +/* Sequence Program control codes */ +#define GAIN_CHANNEL 0x80 +#define ADVANCE_TRACK 0x40 +#define ADVANCE_HOLD 0xC0 +#define RESTART 0x00 + +/* analogic 2502 memory structure */ +struct dvx_2502 + { + unsigned short dev_id; /* device id code (CFF5) */ + unsigned short dev_type; /* type code (B100) */ + unsigned short csr; /* control and status register */ + unsigned short seq_offst; /* sequence RAM offset register */ + unsigned short mem_attr; /* memory attribute register */ + unsigned short samp_rate; /* sample rate register */ + unsigned short dma_point; /* DMA pointer register */ + unsigned short dma_data; /* DMA data register */ + unsigned short thresh; /* threshold register */ + unsigned short fifo; /* input fifo */ + unsigned short end_pad[54]; /* pad to 64 byte boundary */ + }; + +/* input buffer */ +struct dvx_inbuf + { + struct dvx_inbuf *link; /* link to next buffer */ + int wordcnt; /* # of words read to clear fifo */ + short data[512]; /* data buffer */ + }; + +/* analogic 2502 control structure */ +struct dvx_rec + { + struct dvx_2502 *pdvx2502; /* pointer to device registers */ + short *sr_ptr; /* pointer to sequence RAM */ + struct dvx_inbuf *inbuf; /* pointer to current buffer */ + short unsigned csr_shadow; /* csr shadow register */ + short mode; /* operation mode (init or run) */ + int int_vector; /* interrupt vector */ + int intcnt; /* interrupt count # */ + int cnum; /* card number */ + }; + +/* dma chain table size */ +#define DVX_CTBL 34 /* max size of chain table */ + +/* am9516 register select constants. + The DMA control registers are accessed through the dvx2502 registers + dma_point and dma_data. The constants below are the addresses which must + be loaded into the pointer register to access the named register through + the data register. All dual registers are commented as #2. To access channel + #1, OR the value M_CH1 with the channel #2 address. */ +#define DMA_MMR 0x38 /* master mode register */ +#define DMA_CSR 0x2C /* command/status register #2 */ +#define DMA_CARAH 0x18 /* current address reg A high #2 */ +#define DMA_CARAL 0x08 /* current address reg A low #2 */ +#define DMA_CARBH 0x10 /* current address reg B high #2 */ +#define DMA_CARBL 0x00 /* current address reg B low #2 */ +#define DMA_BARAH 0x1C /* base address reg A high #2 */ +#define DMA_BARAL 0x0C /* base address reg A low #2 */ +#define DMA_BARBH 0x14 /* base address reg B high #2 */ +#define DMA_BARBL 0x04 /* base address reg B low #2 */ +#define DMA_COC 0x30 /* current operation count #2 */ +#define DMA_BOC 0x34 /* base operation count #2 */ +#define DMA_ISR 0x28 /* interrupt save register #2 */ +#define DMA_IVR 0x58 /* interrupt vector register #2 */ +#define DMA_CMRH 0x54 /* channel mode register #2 */ +#define DMA_CMRL 0x50 /* channel mode register #2 */ +#define DMA_CARH 0x24 /* chain address reg high #2 */ +#define DMA_CARL 0x20 /* chain address reg low #2 */ +#define M_CH1 0x2 /* mask for chan 1 reg addresses */ + +/* am9516 command constants + All dual commands are commented as #1. To command channel #2, OR the + valur M_CH2 with the channel #1 command. */ +#define MMR_ENABLE 0x0D /* chip enable value */ +#define CMR_RESET 0x0 /* reset all channels */ +#define CMR_START 0xA0 /* start channel #1 */ +#define CMR_SSR 0x42 /* set software request #1 */ +#define CMR_CSR 0x40 /* clear software request #1 */ +#define CMR_SHM 0x82 /* set hardware mask #1 */ +#define CMR_CHM 0x80 /* clear hardware mask #1 */ +#define CMR_SC 0x22 /* set CIE/IP #1 */ +#define CMR_CC 0x20 /* clear CIE/IP #1 */ +#define CMR_SFB 0x62 /* set flip bit #1 */ +#define CMR_CFB 0x60 /* clear flip bit #1 */ +#define M_CIE 0x10 /* int enable bit mask (SC/CC cmd) */ +#define M_IP 0x4 /* int pending bit mask (SC/CC cmd) */ +#define M_CH2 0x1 /* mask for channel #2 commands */ + +/* am9516 chain reload constants */ +#define R_CAR 0x1 /* chain address */ +#define R_CMR 0x2 /* channel mode */ +#define R_IVR 0x4 /* interrupt vector */ +#define R_PMR 0x8 /* pattern and mask */ +#define R_BOC 0x10 /* base operation count */ +#define R_BAB 0x20 /* base address register B */ +#define R_BAA 0x40 /* base address register A */ +#define R_COC 0x80 /* current operation count */ +#define R_CAB 0x100 /* current address register B */ +#define R_CAA 0x200 /* current address register A */ /* If any of the following does not exist replace it with #define <> NULL */ long dvx_io_report(); @@ -679,7 +817,7 @@ void *lclToA24(void *pLocal) void *pA24; status = sysLocalToBusAdrs( - VME_AM_STD_USER_DATA, + VME_AM_STD_USR_DATA, pLocal, &pA24); if(status<0){