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Author SHA1 Message Date
c09f92b043 xilinx: setDAC and setPower returns, setPower cannot set < vmin or 0, setDAC ensures dac value for power regulators cannot be power down value, remove virtual isTransceiverAligned to always return 1 2026-01-13 14:16:14 +01:00
0ba1139741 remove hardcoded MH02 startup
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2026-01-13 11:05:37 +01:00
045d9440de Dev/include file (#1306)
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* create a include command calling the same function as parameters (cmd generation and autocompletion), testing parameters and include

* added include in command line and python and its supposed to do the same as parameters command. both are tested

* added colorama

* moved test_free and test_command python tests to tests/scripts folder from python/tests due to CI issues with dependencies

* generated commands

* formatting

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2026-01-07 10:45:26 +01:00
874ff353e5 virtual servers compile fix for xilinxfmc (#1352)
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2026-01-06 14:38:11 +01:00
Martin Mueller
10879d32da Merge pull request #1351 from slsdetectorgroup/MH02_debug
XCTB updates
2026-01-06 11:42:29 +01:00
66f9664bc4 fprintf should return 2 including terminating character as well. formatting.
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2026-01-06 09:53:55 +01:00
c154164eff refactoring
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2026-01-05 17:51:54 +01:00
d95dff56e4 add back XCTB server binary 2026-01-05 17:03:50 +01:00
32c7afa134 Merge branch 'developer' into MH01_debug 2026-01-05 15:26:15 +01:00
df654ca23d Merge branch 'developer' into MH02_debug 2026-01-05 14:51:37 +01:00
d939dc7e4a update APIXILINXCTB 2026-01-05 14:30:30 +01:00
bcd22af9ba switch XCTB regDefs to cheby output 2026-01-05 13:53:30 +01:00
dece2e16b4 update registerDefs.h
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2026-01-05 09:31:32 +01:00
8063560e3a added FMC control
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2025-11-26 12:16:30 +01:00
178851fcf2 Merge branch 'developer' into MH02_debug
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2025-11-20 14:44:43 +01:00
28 changed files with 1212 additions and 674 deletions

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@@ -149,6 +149,33 @@ class Detector(CppDetectorApi):
value = ut.make_string_path(value)
self.loadParameters(value)
@property
def include(self):
"""Sets detector measurement parameters to those contained in fname.
Set up per measurement.
Note
-----
Equivalent to config, but does not free shared memory. Same as parameters command.
:getter: Not implemented
:setter: loads parameters file
Example
---------
>>> d.include = 'path/to/file.par'
"""
return NotImplementedError("include is set only")
@include.setter
def include(self, value):
if isinstance(value, str):
value = ut.make_string_path(value)
self.loadParameters(value)
@property
def hostname(self):
"""Frees shared memory and sets hostname (or IP address) of all modules concatenated by +

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@@ -41,16 +41,15 @@ def pytest_collection_modifyitems(config, items):
#helper fixture for servers
@pytest.fixture
def servers(request):
""" Fixture to get server and num interaface from test marker. """
try:
return request.param # comes from @pytest.mark.parametrize(..., indirect=True)
except AttributeError:
# fallback default if the test did not parametrize
return [['eiger', 1], ['jungfrau', 1], ['jungfrau', 2], ['mythen3',1], ['gotthard2',1], ['ctb',1], ['moench',1], ['moench',2],['xilinx_ctb',1]]
return request.param
return ['eiger', 'jungfrau', 'mythen3', 'gotthard2', 'ctb', 'moench', 'xilinx_ctb']
return request.param
@pytest.fixture()
def test_with_specific_simulator(servers):
@pytest.fixture
def test_with_simulators(servers):
""" Fixture to automatically setup virtual detector servers for testing. """
LOG_PREFIX_FNAME = '/tmp/slsDetectorPackage_virtual_PythonAPI_test'
@@ -59,50 +58,23 @@ def test_with_specific_simulator(servers):
with open(MAIN_LOG_FNAME, 'w') as fp:
try:
nmods = 2
server, ninterface = servers
msg = f'Starting Python API Tests for {server}'
for server in servers:
for ninterfaces in range(1,2):
if ninterfaces == 2 and server != 'jungfrau' and server != 'moench':
continue
msg = f'Starting Python API Tests for {server}'
if server == 'jungfrau' or server == 'moench':
msg += f' with {ninterface} interfaces'
if server == 'jungfrau' or server == 'moench':
msg += f' with {ninterfaces} interfaces'
Log(LogLevel.INFOBLUE, msg, fp)
cleanup(fp)
startDetectorVirtualServer(server, nmods, fp)
startReceiver(nmods, fp)
d = loadConfig(name=server, log_file_fp=fp, num_mods=nmods, num_frames=1, num_interfaces=ninterface)
loadBasicSettings(name=server, d=d, fp=fp)
yield # run test
cleanup(fp) # teardown
except Exception as e:
with open(MAIN_LOG_FNAME, 'a') as fp_error:
traceback.print_exc(file=fp_error)
Log(LogLevel.ERROR, f'Tests Failed.', fp)
cleanup(fp)
@pytest.fixture(scope="module", params=[['eiger', 1], ['jungfrau', 1], ['jungfrau', 2], ['mythen3',1], ['gotthard2',1], ['ctb',1], ['moench',1], ['moench',2],['xilinx_ctb',1]])
def test_with_simulators(request):
""" Fixture to automatically setup virtual detector servers for testing. """
LOG_PREFIX_FNAME = '/tmp/slsDetectorPackage_virtual_PythonAPI_test'
MAIN_LOG_FNAME = LOG_PREFIX_FNAME + '_log.txt'
server, ninterfaces = request.param
with open(MAIN_LOG_FNAME, 'w') as fp:
try:
nmods = 2
msg = f'Starting Python API Tests for {server}'
if server == 'jungfrau' or server == 'moench':
msg += f' with {ninterfaces} interfaces'
Log(LogLevel.INFOBLUE, msg, fp)
cleanup(fp)
startDetectorVirtualServer(server, nmods, fp)
startReceiver(nmods, fp)
d = loadConfig(name=server, log_file_fp=fp, num_mods=nmods, num_frames=1, num_interfaces=ninterfaces)
loadBasicSettings(name=server, d=d, fp=fp)
yield # run test
Log(LogLevel.INFOBLUE, msg, fp)
cleanup(fp)
startDetectorVirtualServer(server, nmods, fp)
startReceiver(nmods, fp)
d = loadConfig(name=server, log_file_fp=fp, num_mods=nmods, num_frames=1, num_interfaces=ninterfaces)
loadBasicSettings(name=server, d=d, fp=fp)
yield # run test
cleanup(fp) # teardown
except Exception as e:
with open(MAIN_LOG_FNAME, 'a') as fp_error:

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@@ -5,67 +5,44 @@ from conftest import test_with_simulators
from slsdet import Detector
from slsdet._slsdet import slsDetectorDefs
detectorType = slsDetectorDefs.detectorType
@pytest.mark.withdetectorsimulators
def test_rx_ROI(test_with_simulators):
""" Test rx_ROI property of Detector class. """
@pytest.mark.parametrize("servers", [["moench"]], indirect=True)
def test_rx_ROI_moench(test_with_simulators, servers):
""" Test setting and getting rx_ROI property of Detector class for moench. """
d = Detector()
if d.type == detectorType.CHIPTESTBOARD or d.type == detectorType.XILINX_CHIPTESTBOARD:
pytest.skip("Skipping ROI test for ctb/xilinx_ctb detector types.")
d.rx_roi = (0, 10, 10, 20)
roi = d.rx_roi
assert roi == [(0, 10, 10, 20)]
if(d.type == detectorType.MYTHEN3 or d.type == detectorType.GOTTHARD2):
d.rx_roi = (0, 10)
roi = d.rx_roi
assert roi == [(0, 10, -1, -1)]
d.rx_roi = [5,15,15,25]
#d.rx_roi = [[5,15, 0, 1]] # not allowed for mythen3
assert d.rx_roi == [(5,15,15,25)]
d.rx_roi = [0,10, -1, -1]
d.rx_roi = [[0,10,0,20], [5,20,410,420]]
assert d.rx_roi == [(0,10,-1,-1)]
d.rx_clearroi()
else:
roi = d.rx_roi
assert roi == [(0,10,0,20), (5,20,410,420)]
d.rx_roi = (0, 10, 10, 20)
roi = d.rx_roi
assert roi == [(0, 10, 10, 20)]
d.rx_roi = [5,15,15,25]
assert d.rx_roi == [(5,15,15,25)]
if d.type != detectorType.JUNGFRAU and d.numinterfaces != 2:
d.rx_roi = [[0,10,0,20], [5,20,410,420]]
roi = d.rx_roi
assert roi == [(0,10,0,20), (5,20,410,420)] #in same file for jungfrau
d.rx_clearroi()
roi = d.rx_roi
assert roi == [(-1,-1,-1,-1)]
d.rx_clearroi()
roi = d.rx_roi
assert roi == [(-1,-1,-1,-1)]
@pytest.mark.withdetectorsimulators
@pytest.mark.parametrize("servers", [["moench", 1]], indirect=True)
def test_type(test_with_specific_simulator):
@pytest.mark.parametrize("servers", [["mythen3"]], indirect=True)
def test_rx_ROI_mythen(test_with_simulators, servers):
""" Test setting and getting rx_ROI property of Detector class for mythen. """
d = Detector()
assert d.type == detectorType.MOENCH
d.rx_roi = (0, 10)
roi = d.rx_roi
assert roi == [(0, 10, -1, -1)]
#d.rx_roi = [[5,15, 0, 1]] # not allowed for mythen3
@pytest.mark.withdetectorsimulators
@pytest.mark.parametrize("servers", [["moench", 1], ["jungfrau", 1]], indirect=True)
def test_numinterfaces(test_with_specific_simulator):
d.rx_roi = [0,10, -1, -1]
d = Detector()
assert d.numinterfaces == 1
assert d.rx_roi == [(0,10,-1,-1)]

View File

@@ -0,0 +1,5 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
int XILINX_FMC_enable_all(char *error_message, int message_size);
int XILINX_FMC_disable_all(char *error_message, int message_size);

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@@ -373,6 +373,8 @@ int getOnChipDAC(enum ONCHIP_DACINDEX ind, int chipIndex);
void setDAC(enum DACINDEX ind, int val, int mV, int counterEnableCheck);
void setGeneralDAC(enum DACINDEX ind, int val, int mV);
void setVthDac(int index, int enable);
#elif defined(XILINX_CHIPTESTBOARDD)
int setDAC(enum DACINDEX ind, int val, int mV);
#else
void setDAC(enum DACINDEX ind, int val, int mV);
#endif
@@ -401,7 +403,7 @@ void powerOff();
int getBitOffsetFromDACIndex(enum DACINDEX ind);
int isPowerValid(enum DACINDEX ind, int val);
int getPower();
void setPower(enum DACINDEX ind, int val);
int setPower(enum DACINDEX ind, int val);
#endif
#if defined(MYTHEN3D) || defined(GOTTHARD2D) || defined(XILINX_CHIPTESTBOARDD)

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@@ -0,0 +1,83 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#include "XILINX_FMC.h"
#include "arm64.h"
#include "clogger.h"
#include <math.h>
#include <stdbool.h>
#include <unistd.h>
// clang-format off
#define FMC_BASE_PATH "/root/fmc/"
#define FMC_VADJ_EN "FMC_VADJ_EN"
#define FMCP_VADJ_EN "FMCP_VADJ_EN"
#define FMCP_3V3_EN "FMCP_3V3_EN"
#define FMC_3V3_EN "FMC_3V3_EN"
#define FMC_12V_EN "FMC_12V_EN"
#define FMCP_12V_EN "FMCP_12V_EN"
static const char *fmc_files[] = {
FMC_VADJ_EN,
FMCP_VADJ_EN,
FMCP_3V3_EN,
FMC_3V3_EN,
FMC_12V_EN,
FMCP_12V_EN
};
#define FMC_NUM_FILES (sizeof(fmc_files) / sizeof(fmc_files[0]))
// clang-format on
int XILINX_FMC_enable_all(char *error_message, int message_size) {
LOG(logINFOBLUE, ("enable FMC power\n"));
#ifdef VIRTUAL
return 0;
#endif
char full_path[64];
for (size_t i = 0; i < FMC_NUM_FILES; ++i) {
const char *file = fmc_files[i];
snprintf(full_path, sizeof(full_path), "%s%s", FMC_BASE_PATH, file);
FILE *fp = fopen(full_path, "w");
if (fp == NULL) {
snprintf(error_message, message_size,
"XILINX_FMC: Couuld not enable.\n");
LOG(logERROR, (error_message));
return 1;
}
if (fprintf(fp, "1\n") != 2) {
snprintf(error_message, message_size,
"XILINX_FMC: Could not write enable.\n");
LOG(logERROR, (error_message));
return 1;
}
fclose(fp);
}
return 0;
}
int XILINX_FMC_disable_all(char *error_message, int message_size) {
LOG(logINFOBLUE, ("disable FMC power\n"));
#ifdef VIRTUAL
return 0;
#endif
char full_path[64];
for (size_t i = 0; i < FMC_NUM_FILES; ++i) {
const char *file = fmc_files[i];
snprintf(full_path, sizeof(full_path), "%s%s", FMC_BASE_PATH, file);
FILE *fp = fopen(full_path, "w");
if (fp == NULL) {
snprintf(error_message, message_size,
"XILINX_FMC: Could not disable\n");
LOG(logERROR, (error_message));
return 1;
}
if (fprintf(fp, "0\n") != 2) {
snprintf(error_message, message_size,
"XILINX_FMC: Could not write disable.\n");
LOG(logERROR, (error_message));
return 1;
}
fclose(fp);
}
return 0;
}

View File

@@ -1302,7 +1302,17 @@ int validateAndSetDac(enum dacIndex ind, int val, int mV) {
}
else {
#ifdef XILINX_CHIPTESTBOARDD
ret = setPower(serverDacIndex, val);
if (ret == FAIL) {
sprintf(mess,
"Setting power regulator %d to value %d failed.\n",
serverDacIndex, val);
LOG(logERROR, (mess));
}
#else
setPower(serverDacIndex, val);
#endif
}
}
if (ret == OK) {
@@ -1393,6 +1403,15 @@ int validateAndSetDac(enum dacIndex ind, int val, int mV) {
#ifdef MYTHEN3D
// ignore counter enable to force vth dac values
setDAC(serverDacIndex, val, mV, 0);
#elif defined(XILINX_CHIPTESTBOARDD)
{
ret = setDAC(serverDacIndex, val, mV);
if (ret == FAIL) {
sprintf(mess, "Setting dac %d to value %d failed.\n",
serverDacIndex, val);
LOG(logERROR, (mess));
}
}
#else
setDAC(serverDacIndex, val, mV);
#endif

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@@ -7,6 +7,7 @@ add_executable(xilinx_ctbDetectorServer_virtual
../slsDetectorServer/src/communication_funcs.c
../slsDetectorServer/src/arm64.c
../slsDetectorServer/src/XILINX_PLL.c
../slsDetectorServer/src/XILINX_FMC.c
../slsDetectorServer/src/common.c
../slsDetectorServer/src/sharedMemory.c
../slsDetectorServer/src/loadPattern.c

View File

@@ -23,7 +23,7 @@ DESTDIR ?= bin
INSTMODE = 0777
SRCS = slsDetectorFunctionList.c
SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)arm64.c $(main_src)XILINX_PLL.c $(main_src)common.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c $(main_src)programViaArm.c $(main_src)LTC2620_Driver.c
SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)arm64.c $(main_src)XILINX_PLL.c $(main_src)XILINX_FMC.c $(main_src)common.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c $(main_src)programViaArm.c $(main_src)LTC2620_Driver.c
OBJS = $(SRCS:.c=.o)

File diff suppressed because it is too large Load Diff

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@@ -1,24 +1 @@
# Prepare MH02 configuration
reg 0xC00C 0x00040041
reg 0xC010 0x01200004
# configure Matterhorn SPI
setbit 0xC014 0
# wait till config is done
pollbit 0xC014 3 0
# reset transceiver
reg 0xC120 0x0
reg 0xC120 0x1
reg 0xC120 0x0
# set MSB LSB inversions and polarity for transceiver
reg 0xC120 0x1e0
# Enable MH02 PLL clock
pattern enable_clock_pattern.pyat
# start the flow
setbit 0xB030 0
clearbit 0xB030 0
sleep 1
# nothing

View File

@@ -1,39 +1,2 @@
# turn off clock
clearbit 0xB018 15
setbit 0xB010 15
sleep 1
# reset Matterhorn periphery
setbit 0xC014 1
sleep 1
# turn on clock
clearbit 0xB010 15
sleep 1
# reset rx transceiver datapath
setbit 0xC120 4
sleep 1
# reset 8b10b counters
setbit 0xC120 9
setbit 0xC120 10
setbit 0xC120 11
setbit 0xC120 12
sleep 1
clearbit 0xC120 9
clearbit 0xC120 10
# reset buffer fifos
reg 0x9024 0xFFFFFFFF
reg 0x9028 0xFFFFFFFF
reg 0x902C 0xFFFFFFFF
reg 0x9024 0x0
reg 0x9028 0x0
reg 0x902C 0x0
setbit 0xA000 18
# load default pattern
pattern readout_pattern.pyat
# nothing

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@@ -9,8 +9,8 @@
#include "sls/versionAPI.h"
#include "LTC2620_Driver.h"
#include "XILINX_FMC.h"
#include "XILINX_PLL.h"
#include "loadPattern.h"
#ifdef VIRTUAL
#include "communication_funcs_UDP.h"
@@ -257,17 +257,17 @@ int testFixedFPGAPattern() {
LOG(logINFO, ("Testing FPGA Fixed Pattern:\n"));
#ifndef VIRTUAL
uint32_t val = bus_r(FIXEDPATTERNREG);
if (val == FIXEDPATTERNVAL) {
if (val == FIXEDPATTERNREG_PRESET) {
LOG(logINFO, ("\tFixed pattern: successful match (0x%08x)\n", val));
} else {
LOG(logERROR,
("Fixed pattern does not match! Read 0x%08x, expected 0x%08x\n",
val, FIXEDPATTERNVAL));
val, FIXEDPATTERNREG_PRESET));
return FAIL;
}
#endif
LOG(logINFO,
("\tSuccessfully read FPGA Fixed Pattern (0x%x)\n", FIXEDPATTERNVAL));
LOG(logINFO, ("\tSuccessfully read FPGA Fixed Pattern (0x%x)\n",
FIXEDPATTERNREG_PRESET));
return OK;
}
@@ -405,10 +405,21 @@ void setupDetector() {
LTC2620_D_SetDefines(DAC_MIN_MV, DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC,
NPWR, DAC_POWERDOWN_DRIVER_FILE_NAME);
// power LTC2620 before talking to it:
initError = XILINX_FMC_enable_all(initErrorMessage, MAX_STR_LENGTH);
if (initError == FAIL) {
return;
}
LOG(logINFOBLUE, ("Powering down all dacs\n"));
for (int idac = 0; idac < NDAC; ++idac) {
for (int idac = 0; idac < NDAC_ONLY; ++idac) {
setDAC(idac, LTC2620_D_GetPowerDownValue(), 0);
}
LOG(logINFOBLUE, ("Defaulting all power regulators to 0 mV.\n"));
for (int idac = NDAC_ONLY; idac < NDAC; ++idac) {
setDAC(idac, 0, 0);
}
resetFlow();
cleanFifos();
@@ -502,9 +513,6 @@ void setTransceiverAlignment(int align) {
#endif
int isTransceiverAligned() {
#ifdef VIRTUAL
return 1;
#endif
int times = 0;
int retval = bus_r(TRANSCEIVERSTATUS2) & RXLOCKED_MSK;
while (retval) {
@@ -579,9 +587,10 @@ int powerChip(int on, char *mess) {
} else {
LOG(logINFOBLUE, ("Powering chip: off\n"));
bus_w(addr, bus_r(addr) & ~mask);
chipConfigured = 0;
if (FAIL == XILINX_FMC_disable_all(mess, MAX_STR_LENGTH)) {
return FAIL;
}
#ifdef VIRTUAL
setTransceiverAlignment(0);
#endif
@@ -1143,19 +1152,42 @@ int64_t getMeasurementTime() {
/* parameters - dac, adc, hv */
void setDAC(enum DACINDEX ind, int val, int mV) {
int setDAC(enum DACINDEX ind, int val, int mV) {
// Cannot use power down value for power regulators
if (val == LTC2620_D_GetPowerDownValue()) {
switch (ind) {
case D_PWR_D:
case D_PWR_EMPTY:
case D_PWR_IO:
case D_PWR_A:
case D_PWR_B:
case D_PWR_C:
LOG(logERROR, ("Cannot power down Power regulators.\n"));
return FAIL;
default:
break;
}
}
char dacName[MAX_STR_LENGTH] = {0};
memset(dacName, 0, MAX_STR_LENGTH);
sprintf(dacName, "dac%d", (int)ind);
if (val < 0 && val != LTC2620_D_GetPowerDownValue())
return;
if (val < 0 && val != LTC2620_D_GetPowerDownValue()) {
LOG(logERROR,
("Invalid value %d for dac[%d - %s]\n", val, (int)ind, dacName));
return FAIL;
}
LOG(logDEBUG1, ("Setting dac[%d - %s]: %d %s \n", (int)ind, dacName, val,
(mV ? "mV" : "dac units")));
int dacval = val;
if (LTC2620_D_SetDACValue((int)ind, val, mV, dacName, &dacval) == OK)
dacValues[ind] = dacval;
if (LTC2620_D_SetDACValue((int)ind, val, mV, dacName, &dacval) == FAIL)
return FAIL;
dacValues[ind] = dacval;
return OK;
}
int getDAC(enum DACINDEX ind, int mV) {
@@ -1235,8 +1267,7 @@ int isPowerValid(enum DACINDEX ind, int val) {
}
// not power_rgltr_max because it is allowed only upto vchip max - 200
if (val != 0 && (val != LTC2620_D_GetPowerDownValue()) &&
(val < min || val > POWER_RGLTR_MAX)) {
if (val != 0 && (val < min || val > POWER_RGLTR_MAX)) {
LOG(logERROR,
("Invalid value of %d mV for Power V%s. Is not between %d and "
"%d mV\n",
@@ -1287,44 +1318,36 @@ int getPower(enum DACINDEX ind) {
return retval;
}
void setPower(enum DACINDEX ind, int val) {
int setPower(enum DACINDEX ind, int val) {
// validate index and get bit offset in ctrl register
int bitOffset = getBitOffsetFromDACIndex(ind);
if (bitOffset == -1) {
return;
return FAIL;
}
uint32_t addr = CTRL_REG;
uint32_t mask = (1 << bitOffset);
if (val == -1)
return;
char *powerNames[] = {PWR_NAMES};
int pwrIndex = (int)(ind - D_PWR_D);
LOG(logINFO, ("Setting Power V%s to %d mV\n", powerNames[pwrIndex], val));
// validate value (already checked at tcp (funcs.c))
if (!isPowerValid(ind, val)) {
LOG(logERROR, ("Invalid power value for V%s: %d mV\n",
powerNames[pwrIndex], val));
return;
return FAIL;
}
// Switch off power enable
LOG(logDEBUG1, ("Switching off power enable\n"));
LOG(logDEBUG1, ("\tSwitching off power enable\n"));
bus_w(addr, bus_r(addr) & ~(mask));
// power down dac
LOG(logINFO, ("\tPowering down V%d\n", powerNames[pwrIndex]));
setDAC(ind, LTC2620_D_GetPowerDownValue(), 0);
//(power off is anyway done with power enable)
if (val == 0)
val = LTC2620_D_GetPowerDownValue();
// convert voltage to dac (power off is anyway done with power enable)
if (val != LTC2620_D_GetPowerDownValue()) {
// power down dac (Cannot use power down value for power regulators)
if (setDAC(ind, 0, 0) == FAIL) {
return FAIL;
}
// convert voltage to dac
if (val != 0) {
int dacval = -1;
if (ConvertToDifferentRange(
POWER_RGLTR_MIN, POWER_RGLTR_MAX, LTC2620_D_GetMaxInput(),
@@ -1334,20 +1357,23 @@ void setPower(enum DACINDEX ind, int val) {
"mV. Is not between "
"%d and %d mV\n",
powerNames[pwrIndex], val, POWER_RGLTR_MIN, POWER_RGLTR_MAX));
return;
return FAIL;
}
// set and power on/ update dac
LOG(logINFO, ("Setting Power V%s: %d mV (%d dac)\n",
LOG(logINFO, ("\tSetting DAC V%s: %d mV (%d dac)\n",
powerNames[pwrIndex], val, dacval));
setDAC(ind, dacval, 0);
// if valid, enable power
if (dacval >= 0) {
LOG(logDEBUG1, ("Switching on power enable\n"));
bus_w(addr, bus_r(addr) | mask);
if (setDAC(ind, dacval, 0) == FAIL) {
LOG(logERROR,
("Could not set dac for Power V%s\n", powerNames[pwrIndex]));
return FAIL;
}
LOG(logDEBUG1, ("\tSwitching on power enable for Power V%s\n",
powerNames[pwrIndex]));
bus_w(addr, bus_r(addr) | mask);
}
return OK;
}
int getADC(enum ADCINDEX ind, int *value) {

View File

@@ -80,7 +80,7 @@ _sd() {
local IS_PATH=0
local SLS_COMMANDS=" acquire activate adcclk adcenable adcenable10g adcindex adcinvert adclist adcname adcphase adcpipeline adcreg adcvpp apulse asamples autocompdisable badchannels blockingtrigger burstmode burstperiod bursts burstsl bustest cdsgain chipversion clearbit clearbusy clientversion clkdiv clkfreq clkphase collectionmode column compdisabletime confadc config configtransceiver counters currentsource dac dacindex daclist dacname dacvalues datastream dbitclk dbitphase dbitpipeline defaultdac defaultpattern define_bit define_reg definelist_bit definelist_reg delay delayl detectorserverversion detsize diodelay dpulse dr drlist dsamples execcommand exptime exptime1 exptime2 exptime3 extrastoragecells extsampling extsamplingsrc extsig fformat filtercells filterresistor findex firmwaretest firmwareversion fliprows flowcontrol10g fmaster fname foverwrite fpath framecounter frames framesl frametime free fwrite gaincaps gainmode gappixels gatedelay gatedelay1 gatedelay2 gatedelay3 gates getbit hardwareversion highvoltage hostname im_a im_b im_c im_d im_io imagetest initialchecks inj_ch interpolation interruptsubframe kernelversion lastclient led lock master maxadcphaseshift maxclkphaseshift maxdbitphaseshift measuredperiod measuredsubperiod moduleid nextframenumber nmod numinterfaces overflow packageversion parallel parameters partialreset patfname patioctrl patlimits patloop patloop0 patloop1 patloop2 patmask patnloop patnloop0 patnloop1 patnloop2 patsetbit pattern patternstart patwait patwait0 patwait1 patwait2 patwaittime patwaittime0 patwaittime1 patwaittime2 patword pedestalmode period periodl polarity port powerchip powerindex powerlist powername powervalues programfpga pulse pulsechip pulsenmove pumpprobe quad ratecorr readnrows readout readoutspeed readoutspeedlist rebootcontroller reg resetdacs resetfpga romode row runclk runtime rx_arping rx_clearroi rx_dbitlist rx_dbitoffset rx_dbitreorder rx_discardpolicy rx_fifodepth rx_frameindex rx_framescaught rx_framesperfile rx_hostname rx_jsonaddheader rx_jsonpara rx_lastclient rx_lock rx_missingpackets rx_padding rx_printconfig rx_realudpsocksize rx_roi rx_silent rx_start rx_status rx_stop rx_tcpport rx_threads rx_udpsocksize rx_version rx_zmqfreq rx_zmqhwm rx_zmqip rx_zmqport rx_zmqstartfnum rx_zmqstream samples savepattern scan scanerrmsg selinterface serialnumber setbit settings settingslist settingspath signalindex signallist signalname sleep slowadc slowadcindex slowadclist slowadcname slowadcvalues start status stop stopport storagecell_delay storagecell_start subdeadtime subexptime sync syncclk temp_10ge temp_adc temp_control temp_dcdc temp_event temp_fpga temp_fpgaext temp_fpgafl temp_fpgafr temp_slowadc temp_sodl temp_sodr temp_threshold templist tempvalues tengiga threshold thresholdnotb timing timing_info_decoder timinglist timingsource top transceiverenable trigger triggers triggersl trimbits trimen trimval tsamples txdelay txdelay_frame txdelay_left txdelay_right type udp_cleardst udp_dstip udp_dstip2 udp_dstlist udp_dstmac udp_dstmac2 udp_dstport udp_dstport2 udp_firstdst udp_numdst udp_reconfigure udp_srcip udp_srcip2 udp_srcmac udp_srcmac2 udp_validate update updatedetectorserver updatekernel updatemode user v_a v_b v_c v_chip v_d v_io v_limit vchip_comp_adc vchip_comp_fe vchip_cs vchip_opa_1st vchip_opa_fd vchip_ref_comp_fe versions veto vetoalg vetofile vetophoton vetoref vetostream virtual vm_a vm_b vm_c vm_d vm_io zmqhwm zmqip zmqport "
local SLS_COMMANDS=" acquire activate adcclk adcenable adcenable10g adcindex adcinvert adclist adcname adcphase adcpipeline adcreg adcvpp apulse asamples autocompdisable badchannels blockingtrigger burstmode burstperiod bursts burstsl bustest cdsgain chipversion clearbit clearbusy clientversion clkdiv clkfreq clkphase collectionmode column compdisabletime confadc config configtransceiver counters currentsource dac dacindex daclist dacname dacvalues datastream dbitclk dbitphase dbitpipeline defaultdac defaultpattern define_bit define_reg definelist_bit definelist_reg delay delayl detectorserverversion detsize diodelay dpulse dr drlist dsamples execcommand exptime exptime1 exptime2 exptime3 extrastoragecells extsampling extsamplingsrc extsig fformat filtercells filterresistor findex firmwaretest firmwareversion fliprows flowcontrol10g fmaster fname foverwrite fpath framecounter frames framesl frametime free fwrite gaincaps gainmode gappixels gatedelay gatedelay1 gatedelay2 gatedelay3 gates getbit hardwareversion highvoltage hostname im_a im_b im_c im_d im_io imagetest include initialchecks inj_ch interpolation interruptsubframe kernelversion lastclient led lock master maxadcphaseshift maxclkphaseshift maxdbitphaseshift measuredperiod measuredsubperiod moduleid nextframenumber nmod numinterfaces overflow packageversion parallel parameters partialreset patfname patioctrl patlimits patloop patloop0 patloop1 patloop2 patmask patnloop patnloop0 patnloop1 patnloop2 patsetbit pattern patternstart patwait patwait0 patwait1 patwait2 patwaittime patwaittime0 patwaittime1 patwaittime2 patword pedestalmode period periodl polarity port powerchip powerindex powerlist powername powervalues programfpga pulse pulsechip pulsenmove pumpprobe quad ratecorr readnrows readout readoutspeed readoutspeedlist rebootcontroller reg resetdacs resetfpga romode row runclk runtime rx_arping rx_clearroi rx_dbitlist rx_dbitoffset rx_dbitreorder rx_discardpolicy rx_fifodepth rx_frameindex rx_framescaught rx_framesperfile rx_hostname rx_jsonaddheader rx_jsonpara rx_lastclient rx_lock rx_missingpackets rx_padding rx_printconfig rx_realudpsocksize rx_roi rx_silent rx_start rx_status rx_stop rx_tcpport rx_threads rx_udpsocksize rx_version rx_zmqfreq rx_zmqhwm rx_zmqip rx_zmqport rx_zmqstartfnum rx_zmqstream samples savepattern scan scanerrmsg selinterface serialnumber setbit settings settingslist settingspath signalindex signallist signalname sleep slowadc slowadcindex slowadclist slowadcname slowadcvalues start status stop stopport storagecell_delay storagecell_start subdeadtime subexptime sync syncclk temp_10ge temp_adc temp_control temp_dcdc temp_event temp_fpga temp_fpgaext temp_fpgafl temp_fpgafr temp_slowadc temp_sodl temp_sodr temp_threshold templist tempvalues tengiga threshold thresholdnotb timing timing_info_decoder timinglist timingsource top transceiverenable trigger triggers triggersl trimbits trimen trimval tsamples txdelay txdelay_frame txdelay_left txdelay_right type udp_cleardst udp_dstip udp_dstip2 udp_dstlist udp_dstmac udp_dstmac2 udp_dstport udp_dstport2 udp_firstdst udp_numdst udp_reconfigure udp_srcip udp_srcip2 udp_srcmac udp_srcmac2 udp_validate update updatedetectorserver updatekernel updatemode user v_a v_b v_c v_chip v_d v_io v_limit vchip_comp_adc vchip_comp_fe vchip_cs vchip_opa_1st vchip_opa_fd vchip_ref_comp_fe versions veto vetoalg vetofile vetophoton vetoref vetostream virtual vm_a vm_b vm_c vm_d vm_io zmqhwm zmqip zmqport "
__acquire() {
FCN_RETURN=""
return 0
@@ -1262,6 +1262,21 @@ fi
fi
return 0
}
__include() {
FCN_RETURN=""
if [[ ${IS_GET} -eq 1 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN="0 1"
fi
fi
if [[ ${IS_GET} -eq 0 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN=""
IS_PATH=1
fi
fi
return 0
}
__initialchecks() {
FCN_RETURN=""
if [[ ${IS_GET} -eq 0 ]]; then

View File

@@ -4,7 +4,7 @@
_sd() {
local SLS_COMMANDS=" acquire activate adcclk adcenable adcenable10g adcindex adcinvert adclist adcname adcphase adcpipeline adcreg adcvpp apulse asamples autocompdisable badchannels blockingtrigger burstmode burstperiod bursts burstsl bustest cdsgain chipversion clearbit clearbusy clientversion clkdiv clkfreq clkphase collectionmode column compdisabletime confadc config configtransceiver counters currentsource dac dacindex daclist dacname dacvalues datastream dbitclk dbitphase dbitpipeline defaultdac defaultpattern define_bit define_reg definelist_bit definelist_reg delay delayl detectorserverversion detsize diodelay dpulse dr drlist dsamples execcommand exptime exptime1 exptime2 exptime3 extrastoragecells extsampling extsamplingsrc extsig fformat filtercells filterresistor findex firmwaretest firmwareversion fliprows flowcontrol10g fmaster fname foverwrite fpath framecounter frames framesl frametime free fwrite gaincaps gainmode gappixels gatedelay gatedelay1 gatedelay2 gatedelay3 gates getbit hardwareversion highvoltage hostname im_a im_b im_c im_d im_io imagetest initialchecks inj_ch interpolation interruptsubframe kernelversion lastclient led lock master maxadcphaseshift maxclkphaseshift maxdbitphaseshift measuredperiod measuredsubperiod moduleid nextframenumber nmod numinterfaces overflow packageversion parallel parameters partialreset patfname patioctrl patlimits patloop patloop0 patloop1 patloop2 patmask patnloop patnloop0 patnloop1 patnloop2 patsetbit pattern patternstart patwait patwait0 patwait1 patwait2 patwaittime patwaittime0 patwaittime1 patwaittime2 patword pedestalmode period periodl polarity port powerchip powerindex powerlist powername powervalues programfpga pulse pulsechip pulsenmove pumpprobe quad ratecorr readnrows readout readoutspeed readoutspeedlist rebootcontroller reg resetdacs resetfpga romode row runclk runtime rx_arping rx_clearroi rx_dbitlist rx_dbitoffset rx_dbitreorder rx_discardpolicy rx_fifodepth rx_frameindex rx_framescaught rx_framesperfile rx_hostname rx_jsonaddheader rx_jsonpara rx_lastclient rx_lock rx_missingpackets rx_padding rx_printconfig rx_realudpsocksize rx_roi rx_silent rx_start rx_status rx_stop rx_tcpport rx_threads rx_udpsocksize rx_version rx_zmqfreq rx_zmqhwm rx_zmqip rx_zmqport rx_zmqstartfnum rx_zmqstream samples savepattern scan scanerrmsg selinterface serialnumber setbit settings settingslist settingspath signalindex signallist signalname sleep slowadc slowadcindex slowadclist slowadcname slowadcvalues start status stop stopport storagecell_delay storagecell_start subdeadtime subexptime sync syncclk temp_10ge temp_adc temp_control temp_dcdc temp_event temp_fpga temp_fpgaext temp_fpgafl temp_fpgafr temp_slowadc temp_sodl temp_sodr temp_threshold templist tempvalues tengiga threshold thresholdnotb timing timing_info_decoder timinglist timingsource top transceiverenable trigger triggers triggersl trimbits trimen trimval tsamples txdelay txdelay_frame txdelay_left txdelay_right type udp_cleardst udp_dstip udp_dstip2 udp_dstlist udp_dstmac udp_dstmac2 udp_dstport udp_dstport2 udp_firstdst udp_numdst udp_reconfigure udp_srcip udp_srcip2 udp_srcmac udp_srcmac2 udp_validate update updatedetectorserver updatekernel updatemode user v_a v_b v_c v_chip v_d v_io v_limit vchip_comp_adc vchip_comp_fe vchip_cs vchip_opa_1st vchip_opa_fd vchip_ref_comp_fe versions veto vetoalg vetofile vetophoton vetoref vetostream virtual vm_a vm_b vm_c vm_d vm_io zmqhwm zmqip zmqport "
local SLS_COMMANDS=" acquire activate adcclk adcenable adcenable10g adcindex adcinvert adclist adcname adcphase adcpipeline adcreg adcvpp apulse asamples autocompdisable badchannels blockingtrigger burstmode burstperiod bursts burstsl bustest cdsgain chipversion clearbit clearbusy clientversion clkdiv clkfreq clkphase collectionmode column compdisabletime confadc config configtransceiver counters currentsource dac dacindex daclist dacname dacvalues datastream dbitclk dbitphase dbitpipeline defaultdac defaultpattern define_bit define_reg definelist_bit definelist_reg delay delayl detectorserverversion detsize diodelay dpulse dr drlist dsamples execcommand exptime exptime1 exptime2 exptime3 extrastoragecells extsampling extsamplingsrc extsig fformat filtercells filterresistor findex firmwaretest firmwareversion fliprows flowcontrol10g fmaster fname foverwrite fpath framecounter frames framesl frametime free fwrite gaincaps gainmode gappixels gatedelay gatedelay1 gatedelay2 gatedelay3 gates getbit hardwareversion highvoltage hostname im_a im_b im_c im_d im_io imagetest include initialchecks inj_ch interpolation interruptsubframe kernelversion lastclient led lock master maxadcphaseshift maxclkphaseshift maxdbitphaseshift measuredperiod measuredsubperiod moduleid nextframenumber nmod numinterfaces overflow packageversion parallel parameters partialreset patfname patioctrl patlimits patloop patloop0 patloop1 patloop2 patmask patnloop patnloop0 patnloop1 patnloop2 patsetbit pattern patternstart patwait patwait0 patwait1 patwait2 patwaittime patwaittime0 patwaittime1 patwaittime2 patword pedestalmode period periodl polarity port powerchip powerindex powerlist powername powervalues programfpga pulse pulsechip pulsenmove pumpprobe quad ratecorr readnrows readout readoutspeed readoutspeedlist rebootcontroller reg resetdacs resetfpga romode row runclk runtime rx_arping rx_clearroi rx_dbitlist rx_dbitoffset rx_dbitreorder rx_discardpolicy rx_fifodepth rx_frameindex rx_framescaught rx_framesperfile rx_hostname rx_jsonaddheader rx_jsonpara rx_lastclient rx_lock rx_missingpackets rx_padding rx_printconfig rx_realudpsocksize rx_roi rx_silent rx_start rx_status rx_stop rx_tcpport rx_threads rx_udpsocksize rx_version rx_zmqfreq rx_zmqhwm rx_zmqip rx_zmqport rx_zmqstartfnum rx_zmqstream samples savepattern scan scanerrmsg selinterface serialnumber setbit settings settingslist settingspath signalindex signallist signalname sleep slowadc slowadcindex slowadclist slowadcname slowadcvalues start status stop stopport storagecell_delay storagecell_start subdeadtime subexptime sync syncclk temp_10ge temp_adc temp_control temp_dcdc temp_event temp_fpga temp_fpgaext temp_fpgafl temp_fpgafr temp_slowadc temp_sodl temp_sodr temp_threshold templist tempvalues tengiga threshold thresholdnotb timing timing_info_decoder timinglist timingsource top transceiverenable trigger triggers triggersl trimbits trimen trimval tsamples txdelay txdelay_frame txdelay_left txdelay_right type udp_cleardst udp_dstip udp_dstip2 udp_dstlist udp_dstmac udp_dstmac2 udp_dstport udp_dstport2 udp_firstdst udp_numdst udp_reconfigure udp_srcip udp_srcip2 udp_srcmac udp_srcmac2 udp_validate update updatedetectorserver updatekernel updatemode user v_a v_b v_c v_chip v_d v_io v_limit vchip_comp_adc vchip_comp_fe vchip_cs vchip_opa_1st vchip_opa_fd vchip_ref_comp_fe versions veto vetoalg vetofile vetophoton vetoref vetostream virtual vm_a vm_b vm_c vm_d vm_io zmqhwm zmqip zmqport "
__acquire() {
FCN_RETURN=""
return 0
@@ -1186,6 +1186,21 @@ fi
fi
return 0
}
__include() {
FCN_RETURN=""
if [[ ${IS_GET} -eq 1 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN="0 1"
fi
fi
if [[ ${IS_GET} -eq 0 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN=""
IS_PATH=1
fi
fi
return 0
}
__initialchecks() {
FCN_RETURN=""
if [[ ${IS_GET} -eq 0 ]]; then

View File

@@ -1846,6 +1846,13 @@ parameters:
PUT:
function: loadParameters
include:
inherit_actions: EXECUTE_SET_COMMAND_NOID_1ARG
help: "\n\tSets detector measurement parameters to those contained in fname. Set up per measurement. Same as parameters command."
actions:
PUT:
function: loadParameters
savepattern:
inherit_actions: EXECUTE_SET_COMMAND_NOID_1ARG
help: "\n\t[Ctb][Mythen3][Xilinx Ctb] Saves pattern to file (ascii). \n\t[Ctb] Also executes pattern."

View File

@@ -5092,6 +5092,32 @@ imagetest:
\ pixel intensity incremented by 1. If 1, all pixels almost saturated."
infer_action: true
template: true
include:
actions:
PUT:
args:
- arg_types:
- special::path
argc: 1
cast_input:
- false
check_det_id: true
convert_det_id: true
function: loadParameters
input:
- args[0]
input_types:
- std::string
output:
- args.front()
require_det_id: false
store_result_in_t: false
command_name: include
function_alias: include
help: "\n\tSets detector measurement parameters to those contained in fname. Set\
\ up per measurement. Same as parameters command."
infer_action: true
template: true
initialchecks:
actions:
GET:

View File

@@ -6227,6 +6227,48 @@ std::string Caller::imagetest(int action) {
return os.str();
}
std::string Caller::include(int action) {
std::ostringstream os;
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N(
Sets detector measurement parameters to those contained in fname. Set up per measurement. Same as parameters command. )V0G0N"
<< std::endl;
return os.str();
}
// check if action and arguments are valid
if (action == slsDetectorDefs::PUT_ACTION) {
if (1 && args.size() != 1) {
throw RuntimeError("Wrong number of arguments for action PUT");
}
if (args.size() == 1) {
}
}
else {
throw RuntimeError(
"INTERNAL ERROR: Invalid action: supported actions are ['PUT']");
}
// generate code for each action
if (action == slsDetectorDefs::PUT_ACTION) {
if (args.size() == 1) {
if (det_id != -1) {
throw RuntimeError("Cannot execute include at module level");
}
det->loadParameters(args[0]);
os << args.front() << '\n';
}
}
return os.str();
}
std::string Caller::initialchecks(int action) {
std::ostringstream os;

View File

@@ -165,6 +165,7 @@ class Caller {
std::string im_d(int action);
std::string im_io(int action);
std::string imagetest(int action);
std::string include(int action);
std::string initialchecks(int action);
std::string inj_ch(int action);
std::string interpolation(int action);
@@ -531,6 +532,7 @@ class Caller {
{"im_d", &Caller::im_d},
{"im_io", &Caller::im_io},
{"imagetest", &Caller::imagetest},
{"include", &Caller::include},
{"initialchecks", &Caller::initialchecks},
{"inj_ch", &Caller::inj_ch},
{"interpolation", &Caller::interpolation},

View File

@@ -1686,6 +1686,18 @@ int InferAction::imagetest() {
}
}
int InferAction::include() {
if (args.size() == 1) {
return slsDetectorDefs::PUT_ACTION;
}
else {
throw RuntimeError("Could not infer action: Wrong number of arguments");
}
}
int InferAction::initialchecks() {
if (args.size() == 0) {

View File

@@ -120,6 +120,7 @@ class InferAction {
int im_d();
int im_io();
int imagetest();
int include();
int initialchecks();
int inj_ch();
int interpolation();
@@ -456,6 +457,7 @@ class InferAction {
{"im_d", &InferAction::im_d},
{"im_io", &InferAction::im_io},
{"imagetest", &InferAction::imagetest},
{"include", &InferAction::include},
{"initialchecks", &InferAction::initialchecks},
{"inj_ch", &InferAction::inj_ch},
{"interpolation", &InferAction::interpolation},

View File

@@ -46,32 +46,46 @@ TEST_CASE("config", "[.cmdcall]") {
// free: not testing
TEST_CASE("parameters", "[.cmdcall]") {
void test_include_file(const std::string &cmd) {
Detector det;
Caller caller(&det);
// put only
REQUIRE_THROWS(caller.call("parameters", {}, -1, GET));
/*
auto prev_val = det.getNumberOfFrames().tsquash("Number of frames has to
be same to test");
{
system("echo 'frames 2' > /tmp/tempsetup.det ");
std::ostringstream oss;
caller.call("parameters", {"/tmp/tempsetup.det"}, -1, PUT, oss);
REQUIRE(oss.str() == "parameters /tmp/tempsetup.det\n");
REQUIRE(det.getNumberOfFrames().tsquash("failed") == 2);
}
{
system("echo '0:frames 1' > /tmp/tempsetup.det ");
std::ostringstream oss;
caller.call("parameters", {"/tmp/tempsetup.det"}, -1, PUT, oss);
REQUIRE(oss.str() == "parameters /tmp/tempsetup.det\n");
REQUIRE(det.getNumberOfFrames({0}).tsquash("failed") == 1);
}
det.setNumberOfFrames(prev_val);
*/
REQUIRE_THROWS(caller.call(cmd, {}, -1, GET));
auto prev_frames = det.getNumberOfFrames().tsquash(
"Number of frames has to be same to test");
auto prev_fwrite =
det.getFileWrite().tsquash("File write enable has to be same to test");
{
system("echo -e 'frames 2\nfwrite 1' > /tmp/tempsetup.det ");
std::ostringstream oss;
caller.call(cmd, {"/tmp/tempsetup.det"}, -1, PUT, oss);
REQUIRE(oss.str() == cmd + " /tmp/tempsetup.det\n");
REQUIRE(det.getNumberOfFrames().tsquash(
"frames inconsistent and failed") == 2);
REQUIRE(det.getFileWrite().tsquash("fwrite inconsistent and failed") ==
1);
}
{
system("echo -e 'frames 3\nfwrite 0' > /tmp/tempsetup.det ");
std::ostringstream oss;
caller.call(cmd, {"/tmp/tempsetup.det"}, -1, PUT, oss);
REQUIRE(oss.str() == cmd + " /tmp/tempsetup.det\n");
REQUIRE(det.getNumberOfFrames().tsquash(
"frames inconsistent and failed") == 3);
REQUIRE(det.getFileWrite().tsquash("fwrite inconsistent and failed") ==
0);
}
det.setNumberOfFrames(prev_frames);
det.setFileWrite(prev_fwrite);
}
TEST_CASE("parameters", "[.cmdcall]") { test_include_file("parameters"); }
TEST_CASE("include", "[.cmdcall]") { test_include_file("include"); }
TEST_CASE("hostname", "[.cmdcall]") {
Detector det;
Caller caller(&det);

View File

@@ -804,7 +804,7 @@ typedef struct {
}
sls_detector_module &operator=(const sls_detector_module &other) {
if(this == &other)
if (this == &other)
return *this;
delete[] dacs;
delete[] chanregs;

View File

@@ -7,6 +7,6 @@
#define APIGOTTHARD2 "0.0.0 0x250909"
#define APIMOENCH "0.0.0 0x250909"
#define APIEIGER "0.0.0 0x250909"
#define APIXILINXCTB "0.0.0 0x251015"
#define APIXILINXCTB "0.0.0 0x260113"
#define APIJUNGFRAU "0.0.0 0x250909"
#define APIMYTHEN3 "0.0.0 0x250922"

View File

@@ -62,3 +62,5 @@ configure_file(scripts/test_frame_synchronizer.py ${CMAKE_BINARY_DIR}/bin/test_f
configure_file(scripts/utils_for_test.py ${CMAKE_BINARY_DIR}/bin/utils_for_test.py COPYONLY)
configure_file(scripts/test_roi.py ${CMAKE_BINARY_DIR}/bin/test_roi.py COPYONLY)
configure_file(scripts/test_free.py ${CMAKE_BINARY_DIR}/bin/test_free.py COPYONLY)
configure_file(scripts/test_commands.py ${CMAKE_BINARY_DIR}/bin/test_commands.py COPYONLY)

View File

@@ -0,0 +1,100 @@
# SPDX-License-Identifier: LGPL-3.0-or-other
# Copyright (C) 2021 Contributors to the SLS Detector Package
'''
This file is used to start up simulators and test for freeing shm and accessing it from python.
Run this using: pytest -s test_free.py
'''
from time import time
import pytest, sys, time
from slsdet import Detector, Ctb, freeSharedMemory
from slsdet.defines import DEFAULT_TCP_RX_PORTNO
from utils_for_test import (
Log,
LogLevel,
cleanup,
startDetectorVirtualServer,
startProcessInBackground,
loadConfig,
loadBasicSettings
)
def startReceiver(num_mods, fp):
if num_mods == 1:
cmd = ['slsReceiver']
else:
cmd = ['slsMultiReceiver', str(DEFAULT_TCP_RX_PORTNO), str(num_mods)]
# in 10.0.0
#cmd = ['slsMultiReceiver', '-p', str(DEFAULT_TCP_RX_PORTNO), '-n', str(num_mods)]
startProcessInBackground(cmd, fp)
time.sleep(1)
'''
scope = module =>Once per test file/module
to share expensive setup like startDetectorVirtualServer
'''
@pytest.fixture(scope="module")
def det_config():
return {
"name": "ctb",
"num_mods": 1
}
# autouse is false to pass explictly
@pytest.fixture(scope="module", autouse=False)
def setup_simulator(det_config):
"""Fixture to start the detector server once and clean up at the end."""
fp = sys.stdout
cleanup(fp)
# server
startDetectorVirtualServer(det_config["name"], det_config["num_mods"], fp)
# receiver
startReceiver(det_config["num_mods"], fp)
# config and basic settings
d = loadConfig(name=det_config["name"], rx_hostname="localhost", settingsdir="", fp=fp, num_mods=det_config["num_mods"])
loadBasicSettings(name=det_config["name"], d=d, fp=fp)
yield d # tests run here
cleanup(fp)
def test_parameters_file(setup_simulator):
d = setup_simulator
Log(LogLevel.INFOBLUE, f'\nRunning test_parameters_file')
assert isinstance(d, Detector)
with open("/tmp/params.det", "w") as f:
f.write("frames 2\n")
f.write("fwrite 1\n")
# this should not throw
d.parameters = "/tmp/params.det"
assert d.frames == 2
assert d.fwrite == 1
Log(LogLevel.INFOGREEN, f"✅ Test passed. Command: parameters")
def test_include_file(setup_simulator):
d = setup_simulator
Log(LogLevel.INFOBLUE, f'\test_include_file test_parameters_file')
assert isinstance(d, Detector)
with open("/tmp/params.det", "w") as f:
f.write("frames 3\n")
f.write("fwrite 0\n")
# this should not throw
d.include = "/tmp/params.det"
assert d.frames == 3
assert d.fwrite == 0
Log(LogLevel.INFOGREEN, f"✅ Test passed. Command: include")

View File

@@ -217,7 +217,7 @@ def loadConfig(name, rx_hostname = 'localhost', settingsdir = None, log_file_fp
d.numinterfaces = num_interfaces
d.udp_dstport = DEFAULT_UDP_DST_PORTNO
if name == 'eiger' or num_interfaces > 1:
if name == 'eiger' or name == 'jungfrau' or name == 'moench':
d.udp_dstport2 = DEFAULT_UDP_DST_PORTNO + 1
d.rx_hostname = rx_hostname
@@ -227,7 +227,7 @@ def loadConfig(name, rx_hostname = 'localhost', settingsdir = None, log_file_fp
if name != "eiger":
d.udp_srcip = 'auto'
if num_interfaces > 1:
if name == "jungfrau" or name == "moench":
d.udp_dstip2 = 'auto'
if name == "jungfrau" or name == "moench" or name == "xilinx_ctb":