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Author SHA1 Message Date
228d7a5720 removed tests for eiger
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2025-11-19 17:19:51 +01:00
465a9d9ebc rx_roi also accepts sequence of 2 ints 2025-11-19 16:01:17 +01:00
706fc919c7 another bug for xilinx in test script 2025-11-19 12:21:18 +01:00
c8d82909fc Code Review 2025-11-19 11:58:46 +01:00
2eca0cf117 fixed virtual detector test scripts 2025-11-19 11:08:15 +01:00
a0bd26fa7c resolved merge conflict
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2025-11-18 12:06:23 +01:00
e4f47cedf7 Merge pull request #1333 from slsdetectorgroup/1001/fix_format
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changed format to clang-format 17
2025-11-18 12:02:47 +01:00
e92fafbb4b formatted with clang format 12 2025-11-18 12:02:13 +01:00
4730236170 changed format to clang-format 17 2025-11-18 11:31:17 +01:00
85edf98133 disable user id and port test
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2025-11-17 11:00:37 +01:00
ea07eb36d0 added colorama in github workflows
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2025-11-17 09:37:58 +01:00
7d1809642e updated release 2025-11-14 14:58:39 +01:00
c5357a4d73 wrapped virtual detector setup in a test fixture 2025-11-14 14:51:09 +01:00
e6c6b8f4c5 release notes is a markdown file 2025-11-14 12:31:42 +01:00
6474029c42 added tests 2025-11-14 12:29:42 +01:00
f2ee88ba68 clear_rx_roi accessible from python API 2025-11-14 11:15:20 +01:00
f1736b5e7f API also allows single sequence for single ROI 2025-11-14 11:12:34 +01:00
e471b81b84 added typecaster for slsdefs::ROI and added setter and getter for ROI 2025-11-14 10:20:56 +01:00
54e4c46f02 10.0.0.rc (#1260)
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* alignedData now uses std::align_alloc

* imagedata is now allocated on the heap

* m3 server fix for trimbits and badchannels that are shifted by 1

* formatting

* binary in

* added check for proper memory allocation

* commenting out the example in receiver data call back changing size as it affects users using debugging mode to print out headers

* fixed warnings

* commenting out the example in receiver data call back changing size as it affects users using debugging mode to print out headers

* got rid of cast to uint64

* got rid of Reorder function

* added sanity check to only enable for chipttestboard and xilinx

* removed Gotthard stuff

* update the comment about how to modify data on a data call back from the receiver

* autogenerated commands and make format

* changed font size in GUI

* clang-format with clang-format version 17

* updated update_image_size in xilinx

* version number automated for python build

* mistakenly set version back to 0.0.0

* updated github workflow scripts to support automatic version numbering with environment variable

* managed to load VERSION file in yaml file - simplifies things

* saving changes in git workflow failed

* got typo in github workflow

* updatet regex pattern to support postfix

* normalized version to PEP 440 specification in update_version.py

* bug did not support version 0.0.0

* upgrading to c++17 from c++11 and patch command has to be found before applying patch on libzmq (#1195)

* Dev/allow localhost for virtual tests (#1190)

* remove the check for localhost being used in rx_hostname for python test for simulators, run rx_arping test only if hostname is not 'localhost'

* fix tests for fpath: cannot set back to empty anymore (empty is default)

* default rx_hostname arg = localhost, and default settings path =../../settingsdir

* changed virtual tests script for better printout on exceptions

* fix for catching generaltests exceptions and exiting instead of continuing

* fix minor

* fixed shared memeory tests to include current env and fixed prints for errors

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>

* added regex pattern matching to version in toml file

* Dev/gitea docker (#1194)

* gitea workflows for RH8 and RH9
* using our docker images

* version now supports . before postfix

* rough draft of test acquire of all detectors for frames caught and file size. ctb not included yet

* moved dbitoffset, dbitreorder and dbitlist to GeneralData

* added error message on receiver side, throw error

* removed log as error already printed

* added tests to check file size and frames caught with an acquire (virtual) for every detector

* minor printout removed

* typo fixed

* removed minor printout

* incorrect counter mask tested

* fix 10g adc enable mask, switched with 1g

* fixed hardcoded values of nchip nchan etc from detPArameters

* fixed ctb tests, need to fix in develoepr (if digital modfe not enabled, should not take into accoutn dbitlist or dbitoffset or dbitreorder

* only reorder bits if some sort of digital readout mode enabled

* trying to fix acquire for xilinx

* fix for xilinx ctb virtual

* alloweing all tests

* typo

* fix for slsreceiver killed but complaining for virtual tests with script

* fixed bug found by @AliceMazzoleni99 that for ctb server is still shown in pgrep -f if xilinx server running, so now the pid is killed and looking for any DetectorServer_virtual instead. also reset color coding after Log

* check if process running for kill -9 slsReceiver fail

* removed -9 to kill with cleanup

* frame synchonrizer fixes: typo of iterator for loop and zmg_msg_t list cleaned up before sending multi part zmq; test written for the frame synchronizer, test_simulator.py rewritten for more robustness and refactoring commonality between both scripts

* better error messageS

* minor

* typo

* moving the erasure of the fnum to after sending the zmg packets and also deleteing all old frames when end of acquisition

* fix bug in blackfin read access to firmware registers

* updates api version based on version file & converted shell script files to python

* updated all makefiles

* refactoring code and compiling binary

* formatting

* rewrote end() for StaticVector

* rearranged receiver topics, differentiated btween receiver variants and added info about slsFrameSynchronizer

* typo

* minor aesthetics

* minor

* added extra fs link and fixed execute_program warning

* and now with link

* updating pmods

* adresses review comments

* dummy commit for versionAPI

* formatted and updated versionAPI.h

* added expat to host section

* updated documentation for pip installation as well

* Dev/add numpy  (#1227)

* added numpy dependency
* added build specifications for python version and platform

* updates files/variants for pmods for 9.2.0 (#1233)

* tests for bool in ToString/StringTo (#1230)

- Added tests for ToString/StringTo<bool>
- Added overload for ToString of bool (previously went through int)

* added docs for SLSDETNAME (#1228)

* added docs for SLSDETNAME

* clarification on hostname

* added examples on module index

* fixes

* fixed typo

* Dev/update test framesynchronizer (#1221)

* raise an exception if the pull socket python script had errors at startup (for eg if pyzmq was not installed)

* minor changes that got lost in the merge of automate_version_part 2 PR

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>

* added workflow for python wheels

* wip

* formatting

* wip

* wip to parse vector of rois at command line

* wip

* first level test

* can get individual rois, but not connected to command yet

* rois shoudl work. left to implement tests for individual rois, create multiple datasets (1 for each roi) in the virutal data file. currently virutal dataset with roi is not implemented and a warning is given instead. wonder why since the inviduviaual roi files are clipped

* all tests pased

* minor

* fixed rx_roi for multi modules jungfrau , tests for eiger, multi modules jungfrau in x and 2 interfaces

* works for eiger as well

* switched to vector instead of std::array<ROI, 2>>, which prints extra [-1, -1] when theres only 1 udp interface

* wip

* fix for empty roi vectors (which shouldnt be) as you cant know if its all or not in roi

* wip: to map roi to virutal

* fix for eiger, added python test for testig roi in different module and detector type configurations

* wip, fails with master and virtual

* works for complete roi

* wip, works for a single roi

* works for all rois

* wip to fix tests

* 1d fixes

* rois test work on 1d as well

* check master file creation as well in rx_roi tests

* get rx_roi from metadata from rxr, cant reconstruct. fixed clear roi should give 1 roi min

* gui shows roi now

* format

* updated python bindings

* updated master file versions

* cmd generation and formatting

* minor fixes in command line and help

* minor

* doesnt happen anymore

* comment

* minor

* redundant getRxROI in Detector class for multi level and module level

* refactor cmd parsing (detid can be parsed directly)

* refactor cmd line

* refactor command line parsing of roi

* modified comments about ctb and xilinx not using roi

* refactoring

* refactorign

* refactoring wip

* wip refactoring

* formattin

* to avoid confusion, moved default initialized, single sized declared vector of roi to be created at setDetectorType

* pybind only 1 function for getRxROI

* command line help

* specified number of receiver error message

* minor comment

* refactored to take out repetitive code, need to adjust for slsMulti and slsFrameSync

* wip

* works, need to add tests

* made Commadnlineoptions into a class

* wip test

* fixed tests

* cleaning up properly , semaphore leaks, child process/thread throwing handled

* getuid issue on github workflow

* constexpr and checking if options object type is same

* unnecessary capture

* remove testing code, minor

* fixed help, -t for multi should not be supported as it never had it

* Formatting

* hdf5 definitions in test when not compiled with hdf5

* typo

* moved optstring and long options to the constructor

* raising a SIGINT when the child thread has an exception so that the parent thread can exit all the threads and clean up gracefully

* minor test typo

* check status of child exiting and use that to send sigint to all the child processes from the parent

* fixed validation in network_utils, added a tests to throw for port 65535 in test mode (option on for sls_use_tests), multi:parent process checks child process exit status to send sigint to others

* moving set signal handler to network utils

* readoutspeed in rx master file and  other master file inconsistencies (#1245)

readout speed added to json and h5 master files.
Also fixed master file inconsistencies

Sserver binaries
- update server binaries because readoutspeed needs to be sent to receiver with rx_hostname command

API
- added const to Detector class set/getburstmode

Python
- updated python bindings (burstmode const and roi arguments)

Cmd generation
- added pragma once in Caller.in.h as Caller is included in test files

m3: num channels due to #counters < 3
* workaround for m3 for messed up num channels (client always assumes all counters enabled and adds them to num channels), fix for hdf5

g2: exptime master file inconsistency
- exptime didnt match because of round of when setting burst mode (sets to a different clk divider)
- so updating actual time for all timers (exptime, period, subexptime etc, )  in Module class, get timer values from detector when setting it and then send to receiver to write in master file

ctb image size incorrect:
-  write actual size into master file and not the reserved size (digital reduces depending on dbit list and dbit offset)
- added a calculate ctb image size free function in generalData.h that is used there as well as for the tests.


master file inconsistencies
- refactored master attributes writing using templates
-    names changed to keep it consistent between json and hdf5 master file (Version, Pixels, Exposure Times, GateDelays, Acquisition Period, etc.)
-  datatypes changed to keep it simple where possible: imageSize, dynamicRange, tengiga, quad, readnrows, analog, analogsamples, digital, digitalsamples, dbitreorder, dbitoffset, transceivermask, transeiver, transceiversamples, countermask, gates =>int
- replacing "toString" with arrays, objects etc for eg for scan, rois, etc.
- json header always written (empty dataset or empty brackets)
- hdf5 needs const char* so have to convert strings to it, but taking care that strings exist prior to push_back
- master attributes (redundant string literals->error prone

tests for master file
- suppressed deprecated functions in rapidjson warnings just for the tests
- added slsREceiverSoftware/src to allow access to receiver_defs.h to test binary/hdf5 version
- refactored acquire tests by moving all the acquire tests from individual detector type files to a single one=test-Caller-acquire.cpp
- set some default settings (loadBasicSettings) for a basic acquire at load config part for the test_simulator python scripts. so minimum number of settings for detector to be set for any acquire tests.
- added tests to test master files for json and hdf5= test-Caller-master-attributes.cpp
- added option to add '-m' markers for tests using test_simulator python script

* doc: added inst on how to set persistentn NIC changes after reboot for each ethernet interface such as rx 4096, rx-usecs, adaptive-rx and gro etc.

* added permanent ethtool settings also for fedora or modern rhel

* troubleshooting doc: permanent changes for 10g pc tuning (#1247)

* doc: added inst on how to set persistentn NIC changes after reboot for each ethernet interface such as rx 4096, rx-usecs, adaptive-rx and gro etc.

* added permanent ethtool settings also for fedora or modern rhel

* ifcfg scripts still work on rhel8, just not preferred

* added dataformat for jungfrau

* eiger basic mod

* eiger doc done

* added moench

* done

* free shm exposed in python as free function and detector function

* minimum change

* added quad and updated about 1gbe/10gbe

* more info

* remove arguments info

* replacing commands with links

* minor

* detail explanation of eiger

* fixed imagesize ctb issue (out values not transferred, setting any dbit values was not recalculatign image size in generaldata)

* fixed ctb dbit clock changing period in tests as it was setting run clock instead

* python accessing freed shared memory object (#1253)

* added a 'isValid' member in shared memory (also updated shm version) with default true, any access to shared memory() checks also for validity. any free will set this to false and then unmap shm. Any access to shm will then check validity in python.

* fixed tests for shm

* added tests in python as well

---------

Co-authored-by: Alice <alice.mazzoleni@psi.ch>

* updated error message

* made markers argument in ParseArguments a boolean instead of an int

* removed relative path compared to where executable run in test script for settingsdir

* fix roi test

* updating versions (#1258)

* updating package version, client version, server versions. Renaming server versions, using hardlinks in serverBin. Removing ctb servers in serverBin. (#1259)

* fixed no interpolation mode for moench (#1262)

Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>

* fixed multi receiver and frames sync help throw of bad variant access (#1265)

* 1000/doc c standard (#1267)

* updated c++11 to c++17

* more about c++11 and updating readme

* updated documentation for receiver arguments and also making receiver constructor explicit

* minor fix for rxr err message

* fixed doc about gcc version

* 1000/release notes (#1269)

* updated firmware and server version in release notes

* release notes wip

* updated notes(prs done)

* updated release notes. wip

* Release notes

* minor

* minor fix

* 1000/doc architecture commands (#1271)

* sw architecture and setup commands

* 1000/shm free obsolete (#1273)

* freeing obsolete shm withoua a 'isValid' should access raw pointers. Need to move this all into the shm class

* fixed obsolete shm free issue

* minor

* ensuring the test works platform independent for size of int

* removed verify, update, fixed getUser to be a free function, generated commands, python bindings yet to do

* python bindings

* fixed tests

* minor

* minor

* format

* userdetails refinedg

* fixed caller test

* updated client api version (#1277)

* one doesnt need to open shared memory to call removesharedmemory, and calling hasMemoryvalid without opening will cause segfault (not used now, but could in the future)

* fix test on shm

* minor

* added image source files from draw.io to create the images (#1280)

* 1000/fix_actual_tests (#1282)

- fix acquire fail in tests (adcreg test)
- roi tests fail after overlapping invalid test and acquire after
- print udp dest mac in server properly
- fixed udp dst list get (server was not sending entry proper size to match proper struct size in client)
- updated server binaries and updated hard links in serverBin
- added documentation regarding gui:  zmqport and zmqip in terms of gui, rx_zmqstream
- removed print - probably ended there for debuggung

---------

Co-authored-by: Alice <alice.mazzoleni@psi.ch>

* 1000/fix_m3_tests (#1286)

* testing clkdiv one must ensure the exptime delay etc all are reset to the exact values for tests

* change dac max values for vth values for m3 in client side (set module

* 1000/doc_cmake (#1289)

* more detail documentation in installation

* more detail documentation in installation

* added links to api examples

* reverted back that vthreshold dacs in m3 have min and max as 200 and 2400 (#1294)

* update release notes and date (#1298)

---------

Co-authored-by: Mazzoleni Alice Francesca <mazzol_a@pc17378.psi.ch>
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
Co-authored-by: AliceMazzoleni99 <alice.mazzoleni@psi.ch>
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: froejdh_e <erik.frojdh@psi.ch>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
2025-09-10 11:13:36 +02:00
c10bc5e530 9.2.0.rc (#1232)
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* Python module is now built using scikit-build-core: Dev/scikitbuild #1164
* slsdet is available on PyPI from this release onwards
* Fixed broken import in typecaster.h #1181
* Dev/automate version number #1193
* Dev/automate version part2 #1209
* 9111: added expat to host section to fix conda #1216
* fix for gotthard.py to import slsdet properly
* added slsFramesynchronizer to conda copy_lib.sh
* version of release
* update version of client
* removed cmake <=3.28 that was added in 9.1.11 (main_library in meta.yaml in conda-recipes)
* added slsFrameSynchronizer binary to conda
* added numpy dependency to toml
* added documentation for pip in installation

Detailed Commits:
* skeleton pyproject.toml
* moved compiled extension into slsdet
* WIP
* WI{
* separated the recipes
* restored comments, cleanup
* cleaned meta yaml
* added back some python versions
* conda build of main library
* fixed typo
* removed conda build pin
* added zlib
* added workflow for python lib
* patching libzmq and cleaned up cmake
* removed compiler version
* switched patch tool
* reverted to scikit-build in pyproject.toml
* added sls_detector bin
* added sync, renamed action
* update cmake<=3.28 in conda build requirements
* Fixed broken import in typecaster.h (#1181)
- Fixed the broken import _slsdet --> slsdet._slsdet caused by a previous upgrade
- added tests that exercises the conversion from python to C++ and from C++ to python
- Python unit tests now run in CI (!)
* removed 3.28 restriction on cmake in meta.yaml
* from #1216 to 9.1.1.rc that got lost in merge from develoepr, added expat to host section to fix conda build
* back with the cmake restriction
* fixing gotthard1 import
* version number automated for python build
* mistakenly set version back to 0.0.0
* updated github workflow scripts to support automatic version numbering with environment variable
* managed to load VERSION file in yaml file - simplifies things
* saving changes in git workflow failed
* got typo in github workflow
* updatet regex pattern to support postfix
* normalized version to PEP 440 specification in update_version.py
* bug did not support version 0.0.0
* added regex pattern matching to version in toml file
* version now supports . before postfix
* updates api version based on version file & converted shell script files to python
* updated all makefiles
* adresses review comments
* updated release version and the api lib version
* raise an exception if the pull socket python script had errors at startup (for eg if pyzmq was not installed)
* cmake<=3.28 not required anymore
* updated documentation for pip installation as well
* 920/add numpy  (#1226)
* added numpy dependency
* aded build specifications for python version and platform
* release notes
---------
Co-authored-by: froejdh_e <erik.frojdh@psi.ch>
Co-authored-by: Fröjd Lars Erik <froejdh_e@pcmoench03.psi.ch>
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
Co-authored-by: mazzol_a <mazzol_a@pc17378.psi.ch>
Co-authored-by: AliceMazzoleni99 <alice.mazzoleni@psi.ch>
2025-06-02 13:45:06 +02:00
0d1642c56e 9.1.1: Merge pull request #1217 from slsdetectorgroup/9.1.1.rc
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2025-05-22 11:33:01 +02:00
9bb25445f5 formatting 2025-05-22 10:54:02 +02:00
376514606f updated relase notes 2025-05-22 10:51:57 +02:00
8707196f58 Merge pull request #1216 from slsdetectorgroup/911/fix-conda
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added expat to host section to fix conda build
2025-05-22 10:06:41 +02:00
froejdh_e
9f9b1d496c added expat to host section 2025-05-22 09:51:01 +02:00
b2dd964907 Merge pull request #1212 from slsdetectorgroup/911/doc_frame_sync
911/documentation for slsFrameSynchronizer
2025-05-22 08:43:11 +02:00
348d820265 minor 2025-05-21 17:27:31 +02:00
d414c7459b minor aesthetics 2025-05-21 17:05:38 +02:00
8eb2134d9f Merge pull request #1213 from slsdetectorgroup/fix/StaticVector
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911: rewrote end() for StaticVector
2025-05-21 16:34:07 +02:00
b8b067d74b typo 2025-05-21 15:46:49 +02:00
froejdh_e
3619a032ac rewrote end() for StaticVector 2025-05-21 15:46:04 +02:00
2ee7e36fb3 rearranged receiver topics, differentiated btween receiver variants and added info about slsFrameSynchronizer 2025-05-21 14:45:01 +02:00
d739453f2b added support to release notes
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2025-05-14 09:10:15 +02:00
3bfa3bfba3 update receiver version
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2025-05-13 23:30:35 +02:00
894c227723 update release notes and package version 2025-05-13 23:26:04 +02:00
f3e5804d02 Merge pull request #1205 from slsdetectorgroup/911/fix_frame_sync
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911/fix frame sync
2025-05-12 01:01:16 +02:00
2c4cd80748 moving the erasure of the fnum to after sending the zmg packets and also deleteing all old frames when end of acquisition
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2025-05-07 16:44:03 +02:00
674865120b typo 2025-05-07 16:03:43 +02:00
c0ae090be0 better error messageS 2025-05-07 16:02:37 +02:00
a85ad6cd84 minor 2025-05-07 16:01:31 +02:00
5f6dea2d6d fix for gotthard to work 2025-05-07 14:06:30 +02:00
f5bf509525 typo 2025-05-07 13:58:21 +02:00
03eded30f9 refactored test_simulator and test_frame_synchronizer tests 2025-05-07 13:57:12 +02:00
684f511bf8 copy in make
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2025-05-06 17:38:07 +02:00
2c93d40e81 moved log out to utils 2025-05-06 17:37:40 +02:00
9889a31f81 works for all detectors
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2025-05-05 17:22:47 +02:00
b00a37bc16 minor 2025-05-05 14:05:08 +02:00
15030ab732 minor 2025-05-05 14:04:06 +02:00
0ecc6030c6 fixed fram sync issue. mainly due to zmq msg being cleaned up before sending it 2025-05-05 14:03:00 +02:00
6c604e2340 small fixes, but bug introduced here '40895b0148'
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2025-05-03 00:11:55 +02:00
0f4d10912b test frame synchonizer now runs for all modules (only jungfrua enableD) with num modules and num frames as arguments (also servers) and checks the output log of pull socket to ensure there are expected number of headers, moduels and series end htypes 2025-05-02 22:48:48 +02:00
af386a736e first draft of frame synchonizer test. also updated tests updated test_simiulator.py 2025-05-02 16:19:34 +02:00
a43f2c946f Merge pull request #1184 from slsdetectorgroup/911/fix_m3_trimbits_badchannels
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911: m3: fix trimbits and badchannels
2025-04-11 10:41:11 +02:00
8d21fd364b Merge pull request #1188 from slsdetectorgroup/911/slsmultireceiver_verbose_size
911: multi receiver: verbose option
2025-04-11 10:37:34 +02:00
9aceb07d80 update the comment about how to modify data on a data call back from the receiver 2025-04-11 10:30:28 +02:00
7b3accf372 commenting out the example in receiver data call back changing size as it affects users using debugging mode to print out headers 2025-04-10 13:11:16 +02:00
cfde194834 fixed versioning in server from preivous commit 2025-04-09 18:38:06 +02:00
8ac9cd6b15 updated release notes and serverbin 2025-04-09 18:16:47 +02:00
3e38de5092 m3 binary in 2025-04-09 18:13:54 +02:00
70e7879dd9 m3 server fix for trimbits and badchannels that are shifted by 1 2025-04-09 17:52:23 +02:00
37b2efb1ed Merge pull request #1178 from slsdetectorgroup/main_910/conda_build_fix
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fixed conda build
2025-03-28 14:39:43 +01:00
7ac18fbad9 update cmake<=3.28 in conda build requirements 2025-03-28 14:21:56 +01:00
6839315a7c release date 2025-03-28 11:38:50 +01:00
527915a2ca fixed conda build 2025-03-28 11:37:11 +01:00
64aad1e196 Merge pull request #1143 from slsdetectorgroup/9.1.0.rc
Some checks failed
CMake / Configure and build using cmake (push) Failing after 10s
9.1.0
2025-03-26 08:38:23 +01:00
d3f847100e updated date on release notes
Some checks failed
CMake / Configure and build using cmake (push) Failing after 11s
2025-03-25 17:08:40 +01:00
e1224936ca udpate api versioning 2025-03-25 17:02:53 +01:00
f29ef9e345 Merge pull request #1165 from slsdetectorgroup/910/multirxr_proper_cleanup_on_ctrlc
910: multirxr dirty destruct leaving arping thread hanging + versioning (multi and framesync)
2025-03-25 16:54:19 +01:00
00e3b196f6 added release notes 2025-03-20 13:40:37 +01:00
0109973e68 missed to commit 2025-03-20 13:38:17 +01:00
ad995b381a multireceiverapp: changed from pointer to destruct properly (or could have used reset() before exit but kept this for consistency with slsReceiver and slsFrameSynchronizer, added --version/ -v for slsMultiReciever and slsFramesynchronizer (in 10, could be done properly, got rid of unnecessary break after an exit in multireceiverapp, removed outdated f: command line option in slsReceiver used previously for config files, updated version print out to print binary in slsReceiver version command 2025-03-20 13:33:04 +01:00
53b84b17a6 Merge pull request #1162 from slsdetectorgroup/910/fix_tests_real_g2
Some checks failed
CMake / Configure and build using cmake (push) Failing after 10s
910: fixed tests for real gotthard2. change in reg address to test
2025-03-19 17:16:19 +01:00
16d404c21b fixed tests for real gotthard2. change in reg address to test 2025-03-19 17:11:05 +01:00
34ce96ffa0 Merge pull request #1157 from slsdetectorgroup/910/jf_timing_decoder_only_hw2.0
Some checks failed
CMake / Configure and build using cmake (push) Failing after 12s
jf: get timing info decoder only for hw 2.0
2025-03-18 12:31:45 +01:00
d5fa26ef9a even get is not supported for timing info decoder for jungfrau hw v1.0. only hw v2.0 is uspported 2025-03-18 12:29:25 +01:00
77f20b4e97 updated jungfrau binary 2025-03-18 11:04:55 +01:00
a295208c12 Merge pull request #1125 from slsdetectorgroup/910/release_notes
release notes
2025-03-12 09:29:48 +01:00
Erik Fröjdh
36a6087e1d Update RELEASE.txt
Updated frame sync notes
2025-03-12 08:10:49 +01:00
fb406a7c6c experimental tag on frame syncrhonizer release notes 2025-03-11 15:41:21 +01:00
6e4380db43 updated 910 lib versioning dates 2025-03-11 15:25:40 +01:00
903652bb72 added back the binaries that were missing 2025-03-11 11:04:43 +01:00
1609706093 minor changes in topic 2025-03-11 10:43:39 +01:00
14d2d171bb Merged main to 9.1.0.rc, keeping 9.1.0.rc changes 2025-03-11 10:34:17 +01:00
dd8452b365 jf firmware dates updated in release notes 2025-03-11 09:40:12 +01:00
15a9fb86da Merge pull request #1140 from slsdetectorgroup/910/jf_firmware_dates
910/jf firmware dates
2025-03-11 09:36:02 +01:00
222d2b3fad updated jf binary for fwv 1.6 and 2.6 2025-03-11 09:31:05 +01:00
a57531312f jungfrau firmware dates for fw v 1.6 and fw2.6 2025-03-11 09:29:01 +01:00
85a03a1d72 removed CMakeFiles folder. mistakenly added to repo (#1136) 2025-03-10 14:26:22 +01:00
fc197ed002 changed line 66 in docs/conf.py.in to app.add_css_file(filename) (#1130)
Co-authored-by: AliceMazzoleni99 <l_mazzol_a@pc17378.psi.ch>
2025-03-06 14:41:46 +01:00
a5d242876b m3:default period set to 0, updated serverBin folder as well (#1126) 2025-03-04 16:06:46 +01:00
76ce5de89e added release notes for m3 default period 2025-03-04 15:43:45 +01:00
dbb0dbcbcd release notes 2025-03-04 15:28:09 +01:00
87d40d418e reverted servers of eiger, gotthard, gotthard2, moench and mythen3 as nothing has really changed there other than formatting 2025-03-03 15:30:35 +01:00
c82712b587 prior release notes 2025-03-03 11:40:29 +01:00
9dd1509714 formatting 2025-03-03 11:02:38 +01:00
c8290598db 910: multi ids ignored silently in config file (#1114)
* warn that the multi id is ignored in config file? or throw?

* throw and not just warn with printouts as that could be silent as well

* throw for any multi id command in the file.
2025-02-27 10:41:31 +01:00
ff6a2655a2 when creating the python bindings for Detector class, it should ignore the assignment operators (#1106) 2025-02-26 12:20:35 +01:00
7b2e6ae4ab 910: udpated help on multi module and multi command help (#1116)
* udpated help on multi module and multi command help

* fixed issues with empty lines and other syntax with docuemntation

* fixed some warningsin documentation

* some changes to documentation about command line usage

* minor
2025-02-26 11:13:59 +01:00
706f3a103c jf: removed check to allow chipv1.0 also to set comp disable time (#1117) 2025-02-24 09:38:57 +01:00
5de98b3db0 file from Anna: could be reduce print out in zmq processing when using energy threshold (#1112) 2025-02-21 12:49:18 +01:00
7494e41862 910/frame synchronizer (#1086)
* wip: draft of frame synchronizer, semaphores not done yet

* signal handler not affecting semaphore inside lambda function

* finally works with sem

* install targets cmake error fix

* reducing the number of data call backs. incoming from developer

* WIP: of synchronisation (#969)

* WIP of synchronisation

* working so far if everything goes right

* added all information into json headers

* valid json

* allow frame synchronizer to have access to static libzmq when compiling on conda (libzeromq-devel not installed by default

* upto date with multirecieverapp for invalid arguments and help

* formatting

* remove warnings

* changes to print

* removed prints

* no need for print frames to be called

* minor

* commnet

* adding json header in start callback, imagesize in data callback and formatted

* fixed sanitizer issues. 1 left for ctrl+C
- zmq_msg_t should be deleted, not freed. Same with the char arrays and semaphores.

* fixed sanitizer issues and made it more readable

* moving clearing old frames to new startacq just in case it has to process soem frames before the callback

* created a callback mutex to register the callbacks when using threads for different Receiver objects instead of child processes, remove the clean up of the frames (deleting from a signal is thread unsafe) from the siginterrupt handler, reading or  setting terminate should also be inside the mutex, pass receiver object index so that only the first one   cleans up the shared structure

---------

Co-authored-by: Felix Engelmann <felix-github@nlogn.org>
2025-02-18 11:19:00 +01:00
7607fdc9a7 910 jf : bunch id decoder and auto comp disable (#1096)
* jf wip: bunch id decoder only in pcb v2.0 check and comments

* auto comp disable the same way for both chip versions. compdisabletime also available for 1.1 now

* formatting

* fixed tests

* updated jf binary
2025-02-18 11:16:11 +01:00
1bfffb842d added documentation of order in hostname command in quick start guide, udp header format for row and column values and in command line hostname (#1098) 2025-02-18 11:12:20 +01:00
7c48ae9a49 dont usleep if no transmission delay (#1100) 2025-02-18 11:10:26 +01:00
bf82aeee8d 910/restream stop delay (#1093)
* wait a bit for post processor to process the dummy

* refactoring

* minor
2025-02-11 11:02:32 +01:00
84e83bf551 restream stop if stop called, temp solution (#1092)
* restream stop if stop called, temp solution until new command for it

* chekckrestream is ambiguous when only checking receiver

* moved restreaming in background to receiver stop instead of detector stop (was in stop before due to gui stop button access), increase to 2s time to restream in client acquire

* minor

* moved stop to module class

* fix from before
2025-02-11 09:17:25 +01:00
60ce31bb17 removed .str().c_str() (#1089) 2025-02-11 09:15:18 +01:00
2947b65e02 versioning and formatting 2025-02-04 14:25:21 +01:00
1b41e39ad1 updated client versioning (#1061) 2024-11-26 15:14:03 +01:00
64fea22c2b back to getting version for conda from tag (#1059) 2024-11-26 14:35:46 +01:00
9beaed7813 release notes 2024-11-26 11:16:33 +01:00
0aeb7e4417 9.0.0.rc (#1058)
* dev: update 2d gain plot color map (if no x and ymin/max changes or window resizing): setFixedWidth was updating for window resize, updated virtual servers for g2 and jungfrau to keep changing gain and data for every frame. the data value (#819)

* Dev/jf/fix pedestal (#821)

* jf pedestal fix: touch enable bit last

* dev: jf sync: stopping master gives idle (#824)

* jf sync mode master could return idle when stopped and so not all modules return the same value and must check for 'stopped or idle', Also must throw if any of the module gives an error

* added contains_only to sls::Result (#827)

* added variadic template for checking if a result contains only specified values

* fix for gcc4.8

* renamed to Result::contains_only

* updated condition in Detector.cpp

* stop on only the positions

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>

* dev jf: change status reg bits  (#829)

* jf: rewrite of status reg bits, waiting state includes both wati for trigger and start frame, blocking trigger only waits if its not in waiting for trigger and run busy enabled, error state connected in firmware

* dev jf: reconfigure chip when touching electron collection mode bit (#831)

* jf: if bit 14 in reg 0x5d (electron mode collection bit) is changed, configure chip if v1.1 and powered on. so touch writeregister (setbit/clearbit also calls write register in the end). replace when electroncollectionmode command introduced

* eiger required fw version to 32: fix for blocking trigger in quad (#834)

* fix warning for prev_val (variable size array) in tests (#838)

* Dev: : gui acq finished callback for different status (#850)

* fix acquisition finished status to have different status for different modules, but does not have to be error. for eg. jf sync fw (2.4.1 gives idle for master and stopped for slaves when stopping acquiistion)

* handling inconsistent fnums to be -1 in gui, so when one sets 0 (change of value) will also give an exception (#854)

* Dev: fix py virtual test  (#846)

* draft to fix virtual test when it fails

* catching errors in tests and removing sigchild ignore so servers (process in background) executing commands will not fail (pclose no child processes, if sigchld is ignored) fixed

* uncommented python loading config

* somehow killal slsReciever in second detector test fails even though no receiver running

* fixing script for virtual simlator test:fixed issue with check if process running, fixed moench tests

* formatting

* tests for jf (#835)

* execute command inside server fixed (from fix simulator tests and exec command PR) (#857)

* dev: fix server logic in checking detector idle  (#861)

* fix buggy logic in checking detector idle and an argument check

* Dev: trigger signal issues handled at acquire (#864)

* if blocking and handling sync, only master gets blocking acq, slaves get non blocking as they are first and so dont get status or error caught when slaves dont get trigger (due to not connected etc) and acq returns with slaves still in waiting status. so check status of all in blocking acq

* for all dets with sync, ensure atleast one master when starting acq

* docs updated about sync

* minor fix for test_simulator

* updating docs

* fixed doc

* added python 3.12 to the conda build variants

* documentation and examples

* formatting

* forward declare zmq_msg_t and moved include (#869)

* forward declare zmq_msg_t and moved include

* removed zmq from pkg list

* removed zmq as dependency for slsdet (#870)

* dev: moench: min exptime (#865)

* moench: remove min clock cycles for setting exptime (had been ported from jf)

* commands code generation (#871)

* commands code generation  (#803)

* commands code generation for only frames command

* fix cmake file and add Caller files

* working exptime, fully extended commands file and its variants

* start adding template commands

* add INT_CMD_VEC_ID template

* add list command, generate multiple bins, format code

* reach 208 commands using the cpp macros

* add tests for command parser

* start adding tests for commands parser

* fix typo to use commands.yaml

* add more tests for command_parser

* add all template functions (up to 218 commands)

* finish template functions and add more CmdProxy.cpp functions (250+)

* 257 commands

* 300 commands the rest are very special commands

* add special commands without generation

* separate special functions from generated c++ file

* implementing one command for put and get (buggy)

* add infer action in a separate file

* generate header for special commands from yaml

* allow only 0 or 1 for bool inputs

* group all commands in gen_commands.py

* add help to gen_commands.py

* add autocomplete bash script

* autocompletion: add support for module levels and help

* remove debugging line

* add autocompletion, help to commands, change int [0,1] to bool

* copy tests for Caller.cpp. Tests pass

* update with the new developer branch changes

* fix errors after merging (there is problems with tests)

* fixed port/stopport in yaml (intput typo), added '_caller' to the test dac and test on chip dac command in global test for cmdcaller

* undo previous test simulator debug change

* add documentation for the generated code

* reducing the comment to be replaced in length so formatting does not split into 2 lines

* removed formatting specific style of C++11 in gen_commands.py to keep with the top level clang format of the project
* regeneratign code for commands

* automation generated

* Redirect deprecated commands (#872)

* working implementation, need to fix dac

* fixed deprecation redirect for dac command

* Detector specific autocomplete (#873)

* working implementation, need to fix dac

* fixed deprecation redirect for dac command

* detector specific completion for dac

* added autocomplete using detector specific

* fixed error when autocompleting partial words

* Generate commands/fix commands (#875)

* fix vm_a, im_a etc have deg Celsius suffix, also help missing or changed in some places

* dac: require det id for all, arg0 to be printed at output, help for onchip dac and dac, onchipdac: spacing

* getscan detid and blocking trigger help

* udp_Dstlist det_id fixed, but rx_id invalid

* cmdApp in line with cmdLineApp (missing version, receiver_id, not creating det object in help action

* added set_command to differentiate between check_det_id and require_det_id (mixed up), args: -1 needs to check for at least one argument

* reordering

* reordering and checked till integer_command_hex

* fixed a lot more commands

* fix caller tests for eiger

* changes to tests after Bechir left

* changing .cmd to .cmdcall for the caller commands

* fixed tests for caller, still warning for setexptime about cast input

* autocomplete ran

* add moench test

* regenerating autocomplete and commands

* fixing other things from merge conflicts (renaming slsDetectorDefs to defs in commands.yaml)

* formatting

* added code injection to help (#876)

* updated 3 commands to have get output that can be put into put (#877)

* updated some commands to have get output that can be put into put

* fix tests for clkdiv

* adding help to free (#878)

* removing old commands and renaming them, (also making it work for parameters command as it was still calling cmdproxy) (#879)

* More helpful error messages for unsupported actions (#880)

* removing old commands and renaming them, (also making it work for parameters command as it was still calling cmdproxy)

* Added specific help for unsupported actions

* fixed a vetofile get special exception message. more specific warning for special exception message instead of no function warning

* added condition checking true in exceptions for special message

---------
Co-authored-by: Bechir Brahem <bachbrahem@gmail.com>
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>

* Generate commands/fix det command rename (#881)

* made a link to bash autocompletion script in main folder, and replaced all references to 'det' command with 'sls_detector'

* Generate commands/fix detp detg command rename (#882)

* replacing detp with sls_Detector_put and detg with sls_detector_get

* sls_detector_not implemented, but extended message to ask user to use sls_detector_get or sls_detector_put

* autocompletion also for sls_detector or det

* Xilinx ctb (#884)

* updated registers, arm64

* compiler set to aarch64 for xilinx server

* updated RegisterDefs.h

* merge into generate branch and resolving conflicts and adding the xilinx changes to callerspecial and commands.yaml

* compiles and can print firmware version (using a different csp0 address)

* fixing other servers (gotthard, jungfrau, moench, mythen3) that it returns in case of mapping failure, xilinxctb: added that it checks type, prints proper fw version, checks kernel date, added armprocessor define to use in common places, added specifiers to supress overflow and truncation warnings

* added detector ip and mac adddress to the printout

* fixed tests and recompiled servers

* Xilinx client tests (#887)

* implemented testbus, testfpga, set/get #frames, triggers, allowed that and for connection to client, also allowed, getnumchannels, configuremac, getrunstatus, setdetectorposition with dummy values

* allowing tests for xilinx

* binaries in

* Dev/xilinx defaults and pattern (#888)

* implemented testbus, testfpga, set/get #frames, triggers, allowed that and for connection to client, also allowed, getnumchannels, configuremac, getrunstatus, setdetectorposition with dummy values

* connected kernelversion, hardwareversion, versions, framesl, triggersl, dr, timingmode, pattern (except patioctrl) thats there for altera ctb

* replaced set/get64Bit to set/getU64bit in all loadpattern.c for (ctb and m3 also)

* minor

* updated commands generation

* formatting

* moench default speed set to after init readout configuration (half speed) (#886)

* Fixed path when building as submodule

* Moench v8 (#892)

* new rct structure for moench03

* new moench data structure for offline processing

* meonch raw data and zmq process files updated to 7.0.3 version

* implemented config file for Zmq file

* raw data and zmq work with config file, but only with one file/interface

* zmq config change

* added config examples for zmq and rawdata

* pmod for 7.0.3 and 8.0.0 from previous releases

* updated pmod 8.0.1 for rh7 and rh8

* m3 fix to get kernel version properly on nios without an incorrect error msg (#898)

* moench: changed max shifts of adc clk from 240 to 200 (#900)

* Protect from getenv("HOME") returning nullptr  (#907) (#908)

* Protect from getenv("HOME") returning nullptr (e.g., in case running in systemd)

* Write proper warning in Module.cpp

Co-authored-by: Filip Leonarski <filip.leonarski@psi.ch>

* Dev/xilinx acq (#901)

* period and exptime(patternwaittime level 0)

* added new regsieterdefs and updated api version and fixedpattern reg

* autogenerate commands

* formatting

* minor

* wip resetflow, readout mode, transceiver mask, transceiver enable

* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw

* programming fpga and device tree done

* most configuration done, need to connect configuretransceiver to client

* stuck at resetting transciever timed out

* minor

* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber

* configuretransceiver from client, added help in client

* make formatt and command generation

* tests for xilinx ctb works

* command generation

* dacs added and tested, power not done

* power added

* added temp_fpga

* binaries in

* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed

* start works

* virtual server sends

* receiver works

* tests

* python function and enum generation, commands generatorn and autocomplete, formatting, tests

* tests fail at start(transceiver not aligned)

* tests passed

* all binaries compiled

* eiger binary in

* added --nomodule cehck for xilinx

* updated binaries

* formatting

* moench server: changed default values of adcphase for full speed from 300 to 150 and dac vipre_cds from 800 to 1280 (#922)

* client bug fix: m3 multi module bad channel file throws bad allocation when modules skipped, needed to add vectors in 2d vector of bad channel list (#920)

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>

* developer: blocking acquire stop with slave temporarily in waiting (#926)

* client: stopping a blocking acquire of multi modules checks status to catch slaves that might still be in waiting. Problem is (gotthard2 25um at least) slave is in waiting only temporarily before going go idle/stopped. So a 50ms sleep is necessary ot not throw an unnecessary error

* client: when stopping blocking acquire, wait up to 1s in 50ms increments for slave to stop waiting temporarily

* fix to rapidjson for build with gcc 14 (#929)

* Dev: m3 clkdiv0 20 (#924)

* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)

* g2: startup clk div back to 10 as in firmware but setting in software startup to 20

* m3: minor print error if clk divider > max

* G2: reconfigure chip (#927)

* changed common.c readADCFromFile to make it more general and move temperature calculation for Eiger out of this function and inside whereever it is called.
* g2 and m2: gethighvoltage was just a variable set in server, it is now moved to a get inside DAC5671 implementation (but not reading a measured value, instead what is set from a file), high voltage variable used inside DAC5671 for virtual servers
* g2: switching off hv (ifrom non zero to zero value) will wait for 10s; powering on chip reconfigures chip; powering off chip unconfigures chip; powering off chip also includes check if hv = 0, if not throw exception; chip configuration checked before acquring; at start up: hv switched off and chip powered on, so does not wait 10s to switch off hv;
* included test to check powering off chip when hv is on should throw an exception
* g2:  check if chip configured before acquiring

* nios: read hv value set from file and virtual still goes into DAC5671 for conversions to and fro dac to V, change common readadc to readparameter to generalize, make sethighvoltage into a get and set to catch errors in get as well, g2: if not at startup, remmeber hv value before setting it and after check if value was being switched off (from a non zero value) and wait 10s if it was (10s wait only for switching off from non zero and not at startup)

* developer: moench empty data callback  (#936)

* moench (feature to wait for post processing to be done in new sls_detector_acquire_zmq executable)

READOUT_ACTION_ZMQ added to action enums
sls_detector_acquire_zmq added to executables
empty data call back so that client listens to last dummy zmq packet from moench post processor
processor: remove NEWZMQ ifdefs and remove connect for zmq publisher socket

* fix to compile

* cmds generated and parsed

* dev: client: status for blocking acquire stop with slave temporarily in waiting (#944)

* acq finish call back gets status squashed with default error but before that need to wait for gotthard slaves to catch up from waiting to stopped

* bug fixes related to file saving (#931) (#946)

* fix the file path resetting issue of GUI in the case where different modules have different fpath setting.

* fix stack-buffer-overflow issue when using HDF5 HDF5DataFile::parameterDataTypes have 64bit type (i.e. STD_U64LE), the size of fill_value should be at least 8 bytes.

* change the type of fill_value to uint64_t

Co-authored-by: Z.H. Li <zhenghenge@gmail.com>

* updated documentation from martin (#948)

* Dev/xilinx ctb test (#942)

* voltage regulators only looks at dac and not at ctrl_reg

* xilinx: change dac max to 2048, setting dac ist not inverse conversion from dac to voltage anymore, but setting power is inverse, also there is max and min to power, a different min for vio and this is checked at funcs interface, not printign or converting to mv in dac for power regulators (as its conversion max and min are different)

* Use links for dacs/adc and adapt power rglt thresholds

* Remove wait for transceiver reset

* adc and dac device not used anymore and hence removed

* udp restucturing: arm has to be multiple of 16 and no byteswap in udp_gen, option to compile locally in arm architecture, memsize of the second udp memory has to be limited

---------

Co-authored-by: Martin Brückner <martin.brueckner@psi.ch>

* formatting

* dev: jungfrau HW 1.0: adc output clock phase to 120 (#952)

* jungfrau: change adc output clock phase from 180 to 120 for v1.0 boards for reliable readout of adc #2

* versioning

* formatting

* rx: moved creating fpath (if it doesnt exist) from setting file path to at the start of acquisition when creating file. This is done here so that it does not fail if fwrite is disabled anyway. Also fixed it in documentation. Changed in documentation that the default for fwrite is disabled (#957)

* added keepalive zmq socket option (after 60s of idle time, 10 probes every sec. Mainly because an issue at Max IV (#956)

* Moench mess from developer (#953)

* new moench data structure for offline processing

* Dev/zmq stream all ipv6 adn remove rx_zmqip (#958)

* enable ipv6 in zmq socket

* removed rx_zmqip API and field in gui, changed client updaterxrzip to updateclientzmqip to have the rx_hostname ip if 0. 

* updated command line for rx_zmqip to give a warning. 

* Replaced 'depreciated' to 'deprecated' everywhere

* switching from * to 0.0.0.0 works for rebinding zmq sockets

* fixed help in command line for rx_zmqip * to 0.0.0.0 and removed cmd in python

* remove publisher zmq socket ip also for moench post processing

* fixed tests

* publisher zmq ip macros to be reused

* fixed a warning about narrowing conversion from size_t to int (#963)

* fixed stop server not starting up with setup variables (#949)

* m3: fixed stop server not starting up with setup variables

* all servers except eiger fixed for virtual stop server to start up with setupDetector function called

* virtual tests work

* eiger: versions print neednt be in stop server

* jungfrau: stop server (not virtual) also needs to read config file

* ensuring master is setup for virtual and real servers

* Dev/pyctbgui merge (#960)

* added empty c extension

* added rotation to the decoding

* added color map, options and findex

* minor

* move checks to before acquisition

* added pixel map based decoder

* cleanup

* no thread creation for single thread processing

* added rotation and test to compare

* allow high and low water mark for zmq (also buffer size) for fast readouts

* removed roatation during decoding

* added Transpose to image and invert Y False to invert it

* retains the zoomed state after the first image of gui, catch and display exception if no detector connected

* moved start frame to dockable widget, removed extra frame number label, moved current measurement also to dockable widget, hide frame plot entirely when showing patternviewer

* first image dependin on which plot

* remember settings of main window size and position, dockewidget if docked, its size and posisiotn as well, then update it next time the gui is opened

* change in comment

* using c decoder for moench 04 and matterhorn

* catch exception from invalid image from decoder

* clean up

* update row and col when choosing image type, neeeded to show values

* fix for previous PR

* disable resetting colormap values
keep the range selected for every new acquisition

* fix typos + tested on virtual matterhorn

* minor print

* refactored Slow ADCs Tab

* refactored DAC tab

* refactored power supplies

* refactored signals tab

* refactored transceiver tab

* fix typo

* fix typo2

* remove commented code

* delete commented code

* delete commented code

* delete commented signals code

* remove commented code for transceiver tab

* refactor adc tab

* refactor Pattern Tab

* Refactor transceivers tab (PR#5) (#118)

* refactored transceiver tab

* remove commented code for transceiver tab

---------

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>

* refactor adc tab (PR#6) (#119)


* refactor adc tab

* refactored Plot and Acquisition Tabs

* fix the regression issue

* restructure project files

* applying singleton and renaming tabs to services

* working install using pip

* applies singleton to tab classes and remove CI erros

* added pyzmq and pillow

* remove the singleton implementation and keep changes

* fix merge errors in mainWindow

* moved misplaced init file

* rename service to tab

* reorganize imports

* iterate over tabs

* reorder tabs

* add slowadc to the list

* saving changes (buggy)
power supply ui not showing in the gui

* split power supply tab

* fixed tests

* add hardcoded values to defines file

* fix error

* separate power supply

* fix errors for powerSuppliesTab

* split dacs

* split slow adcs

* split signals tab

* added tests for bit_utils

* add slowAdc class to defines

* split transceiver ui file

* split adc.ui

* split pattern ui file

* split plot and acquisition ui file

* added basic test for parsing bit names

* removed redundant code in read_alias_file

* fix dacs ui position

* testing for correct exception

* cmd and args at split

* group radio buttons

* fix comments from PR#1

* show legend

* added python version and dev requirements to setup.py

* fix dac issue

* moved _decoder into pkg

* added inplace build

* removed clear

* fixed dependencies

* make tests run without slsdet

* updated name of action

* define colcount

* fixed loading of alias file

* add yapf and ruff

* apply formatting

* fix E and F rules

* add more ruff rules

* change variable name

* squashing gh debugging commits and add pre-commit

* update label values to mv units

* add hook for yapf

* reconfigure yapf precommit hook

* add format and check_format to makefile

* change gh actions

* update readme

* added check_format

* WIP

* added linting in github action

* updated readme]

* add more control for color choice

* remove useless file

* fix un-updated line after refactoring Defines
BIT0_31_MASK is not found in Defines.signals

* visually improve the interface

* fix last commit

* add only selected plots for legend

* add hide legend button

* change hide legend to show legend
checkbox show legend is checked by default

* add support for saving in numpy

* solve conversations

* fix acq index offset

* fix browse button in pattern error

* fix other browse button errors

* finish tests and add usage.md

* remove buffer

* add file,numpy-like interface and tests

* remove useless .npy files

* subscriptible npz files

* remove useless files

* remove repetetive tests

* save changes

* add mode r+, add with support,remove logging

* remove offset of acqIndex between raw and numpy saving

* fix only saving last frame

* save signals of multiple devices

* add comments and move condition for clearer code

* fix bug when vieweing pattern file

* iterate over enabled and plotted plots

* add padestal substraction to transceiver and analog data

* init pedestal frames to detector.frames

* restore old exception

* add pedestal substraction for digital signals

* remove frames spinbox from plotTab

* remove comments and use str instead of Path

* avoid saving all frames

* correct exception and log error's trace

* add gui tests

* add waveform test

* add pedestal test

* refactor by using fixtures

* add tests for moench analog and pattern

* add pytest-qt to dependencies

* add save and load gui parameters

* remove nohup file

* fix old bug IndexError

* save plot type

* a

* handle canceling load, loading matterhorn pedestal for moench

* remove comparing .png files for pattern test

* save plot type

* red error on status bar when shape mismatch for loaded pedestal

* fix makefile and docstrings

* fix PRs conversation

* move code into different function

* fix wrong function names for power supply

* removed old ctbgui

* removed unnecessary files

---------

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
Co-authored-by: Braham Bechir <braham_b@pc11979.psi.ch>
Co-authored-by: Bechir <bechir.braham@psi.ch>
Co-authored-by: Bechir <bechir.brahem420@gmail.com>

* Dev/xilinx mat update (#959)

* put back code to obtain adc and dac device indexafter loading device tree and then create folder iio_device_links and create symbolic links there according to device indices found. ln -sf operation not permitted, so folder has to be deleted and created everytime. Also refactored definitions to have all the xilinx name or detector specific stuff out of programbyArm.c

* uncommented waittransceiverreset at startup (should work now) and return of powering off chip at startup (error for transceiver alignment reset)

* updated registerdefs from firmware

* minor prints and updating names from registerdefs

* waittransceiverreset has been fixed in firmware and removing warnign for that, transceiver alignment check for powering off chip is not done in fw (giving a warning and returning ok for now)

* fixing ipchecksum (not done), removed startperiphery, allowing readout command to be allowed for xilinx when acquiring

* dont build doc for Tobi Schluter from libzmq, which uses iso-8859-1 and the umlaut cause compilation to fail on some machines (#973)

* 8.0.2 psi modules

* missed the rx_zmqip implementations in detector.h and python bindings (#975)

* rx_zmqip has been removed. Remove it also for pyctbgui (#979)

* format

* Dev/rx callbacks (#966)

* changed rxr callback signatures to all include structs
* removed datamodify call back as size can be changed in the original data call back now
* bringing some parameters (set functions) to dataProcessor class for its callback (namely udpport, quad, fliprows, totalframes, jsonheader), resulting in also removing totalframes from 2 other function signatures

* updated MultiReceiverApp to reflect the new callback signatures

* Dev/reg bit change no validate (#970)

- do not validate write reg, setbit and clearbit by default anymore
- --validate will force validation on the bitmask or entire reg
- remove return value for write reg (across server to client, but thankfully not in the Detector class)
- extend validation into writereg, setbit and clearbit for Eiger (always special)
-  need to check python (TODO)
- missed the rx_zmqip implementations in detector.h and python bindings

* sleep implemented for command line, mainly for config files for firmware developers (#982)

* change gain mode help from dynamicgain to dynamic (#988)

* fixing python version. allowing versions to execute even if no detector connected or in shared memory (#990)

* Jf: Electron collection mode (#983)

* electron collection mode for jungfrau. also removing the config chip when using register command
* collectionMode: HOLE/ELECTRON (enum)

* Dev/m3 readout speed (#985)

* added readoutspeed command to m3 (fullspeed - 10, half speed - 20, quarter speed - 40), removed reaodut pll, moved up system pll clock indices, leaving pll index in common altera code, default speed is half speed, allow only system_c0 to be set, the others can be obtained, same for clkphase, maxclkphaseshift, clkfreq. added to readoutspeedlist commands, updated help and updated tests

* updated readoutspeedlist command

* jf: timing info decoder (#987)

* timing_info_decoder command with options swissfel (default) and shine. added to python, command line generation, autocomplete, tostring, tests.

* updated jungfrau timing info decoder mask (#991)

* minor. removed warning print at startup for empty eth udp to listen to (#992)

* removed 'Caller/CALLER' from test names as there is only one command line now (#993)

* formatting

* Dev/g2 stop frame number (#980)

* get/set next frame number in G2 (firmware only has set, no get)
* firmware has issues: each stop keeps 2 frame header in fifo and the resetting frame number happens after that
* removed the option to set burstmode to burst external or continuwous internal
* needs to be revisited before 9.0.0

* formatting

* fix the command help in the command help generator for Gotthard2 about nextframenumber (#994)

* first draft at fixing nextframenumber properly with firmware (#995)

* fixing nextframenumber properly with firmware

* updated firmware to have getnextframenumber and fixed setnextframenumber to reset also the header fifo when stopping

* fix tests for gotthard2

* Dev/g2 fix next frame number (#996)

* binaries in

* formatting

* release notes

* release notes

* updating firmware dates

* release notes

* package release version and renaming server names

* updated client versioning

* updated moench fw release version

* 900/proper free (#1002)

* first draft of fixing the free function available within the class

* removed class member function freeSharedmemory for both Detector and Module; made the free function freeSharedmemory accessible to python interface; setHostname if there is already a module in shm will recreate the Detector object while freeing shm completely and keeping detsize and intitialchecks (previous commit), sethostname called from DetectorClass in virtual command to have one point of entry (previous commit), testing Module class frees shared memory using free function

* Detector class: added copy and move constructor and assignmentoperators due to explicit destructor (DetectorImpl fwd declared), DetectorImpl class: included ZmqSocket to remove destructor (should not be virtual in any case), Module class: removed explciit destructor to allow compiler generated constructor and operators

* formatting

* updated client version date

* minor fix for readme autocomplete

* setting detsize after hostname should throw also for single module for consistency (#999)

* 900/autocomplete documentation (#1003)

* fixed the gendoc to reflect the new parser, updated documentation to include info about autocomplete in the command line part, error in createing docs

* fixed list deprecated, fixed command help (to show properly on a html, fixed other help warnings

* minor indents

* 900/g2 chip configure at startup (#1008)

* g2: chip reconfigure variable not set when powering on at startup because readconfig is the one configuring the chip the first time to default chip settings

* cleaning up code

* 900/rm volatile (#1006)

* Removing volatile and replacing with atomic to ensure atomicity

* compiling header include issue

* 900/jf firmware rollback (#1010)

* jf: rolling back firmware required to v1.5 and 2.5, updated release notes, fixed a bug when updating server (when server name same as link name:throws with no message, pedestal mode check changed for the time being for loops to be 0xFF size

* compensating for jf fw bug for pedestalmode where loops should be 16 bit, but is 8 bit in fw. to be fixed in next version

* formatting

* fixed python test simulator to kill previous servers

* gui: hide 'complete image' and just show 'missing packets' when there are missing packets in that image form the receiver (#1013)

* release notes update (#1015)

* 900/detach pthreads not joining (#1017)

* detach the pthreads that are not joining else memory leak

* release notes

* removed the clean up comment, also refactored the pthread join/detach for ctb 1g

* 900/server malloc check (#1020)

* usleep in communication to actually relay the err message of memory allocation to the client (weird but test for now), function in server to handle memory allcoation issues (updates mess, ret and sendsit to the client and returns prior from function implementatin, setting fnum in client for the speicific functions that send to detector each argument separtely, they need to remember the fnum else they throw with the incorrect fnum

* server: every malloc must check if it succeeded, rearranging so that the free is clear as well (only in funcs so far)

* formatting

* fixed malloc checks in other places other than funcs.c

* bug fix return from previous commit

* pointer bug from previous commit

* formatting

* binaries in

* 900/document json ctb file format (#1027)

* docs receiver formats rewrite

* added documentation for all the receiver files, updated release notes, udpated help in commands help for timing, fixed by throwing exception for aa dividy by 0 error caused by not freeing memory (detsize) when switching between 1d and 2d detectors, removed unnecessary 'recevier up' printout, fixed dbit list 64 bit mask error in master json file (was not 64 bit before), fixed bug in reading gotthard1 data (needs to be tested)

* generating commands help and formatting, also fix help for trimen command line

* added ctb frame format documentation, added some links to some commands, added documentation about adding expat-devel in installation for rhel8 gui, fixed some indentation issues that screwed up command line help documentation

* added ctb frame format documentation

* updated documentation about zeromq-devel for <8.0.0 versions

* fixed typo in python for vb_pixbuf Jungfrau dac (#1030)

* fixed cli documentation (#1037)

* 900: legal gain values in jungfrau simulator (#1043)

* legal gain values in jungfrau simulator

* typo

* release notes

* 900/jungfrau temp control default enable (#1041)

* jungfrau: enabling temp control by default at server startup

* 900: fixed invalid arguments to slsmultireceiver (#1039)

* wasnt showing error message for invalid arguments to slsmultireceiver
* allow 0 arguments to act like an slsReceiver with start tcp port 1954 and just 1 receiver

* 9.0.0: version from file to cmake and python (#1024)

- renamed conda-recipe folder
- added a check to see if build and install folder exists in build.sh (conda recipe)
- created VERSION file that has '0.0.0'for developer but can be updated using update_version.py that takes in a version. The script checks for semantic versioning and updates VERSION file
- VERSION file also copied along with py files to slsdet in python cmakelist and build_pylib.sh (for conda), also copied in root folder for installations (for no coding purpose)
- init.py and setup.py reads this file to get the version (a bit differently to find the VERSION file)
- VERSION file read into cmake to get the version and also added to compile definition. So RELEASE removed from versionAPI.h (using SLS_DET_VERSION compile definiton instead) and also removed updateRelease script.
- conda getting project version from environment variable SLS_DET_VERSION that is set in build_pylib.sh prior.
- added 3.13 python to conda build
- anything related to ctb removed from release notes as users will always use developer
- sets 9.0.0 to VERSION file  by running update_version.py without an argument

* formatting

* finalized binaries

* updated m3 fw version (#1046)

* release notes

* fix cmake (cannot find VERSION file) when using package as subfolder as cmake_source_dir is not same anymore, add troubleshooting doc for m3 regarding loose control board for waiting status in auto timing mode, fix m3 tests to test register write (previously was read only) (#1047)

* 900: bumped pybind11 version and added setuptools on host (#1050)

* bumped pybind11 version and added setuptools on host

* updated pybind11 tarball to 2.13 and in cmakefile to get 2.13 frpm github, also updated documentation about pybind 2.13

* update release notes, doc

* updating readme

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>

* 900 cmake_source_dir (#1053)

* when package used as subdirectory (cmake-subfolder-example) it fails when python is used because the cmake_source_dir is now the one above package.

* changed cmake_current_list_dir to cmake_current_source_dir

* removing the unnecessary VERSION file installed in the root directory (from PR #1020)

* 900: pybind 2.13.6 and python 3.8 (#1054)

* changed pybind 2.13.0 to 2.13.6, kept conda at min 2.13.0

* changed min python version from 3.6 to 3.8

* 900/docs (#1056)

* minimum python is 3.8, so >=

* removed ctb frame documentation. should be in internal wiki

* updated release notes

* updated releate date

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
Co-authored-by: froejdh_e <erik.frojdh@psi.ch>
Co-authored-by: anberga <34126852+anberga@users.noreply.github.com>
Co-authored-by: Filip Leonarski <filip.leonarski@psi.ch>
Co-authored-by: Z.H. Li <zhenghenge@gmail.com>
Co-authored-by: Martin Brückner <martin.brueckner@psi.ch>
Co-authored-by: Braham Bechir <braham_b@pc11979.psi.ch>
Co-authored-by: Bechir <bechir.braham@psi.ch>
Co-authored-by: Bechir <bechir.brahem420@gmail.com>
2024-11-26 11:13:45 +01:00
4880f87791 8.0.2.rc (#974)
* moench: changed max shifts of adc clk from 240 to 200 (#909)

* moench server name and version renaming

* 802/moench default speed (#910)

* moench:change default speed to half speed

* Protect from getenv("HOME") returning nullptr  (#907)

* Protect from getenv("HOME") returning nullptr (e.g., in case running in systemd)

* Write proper warning in Module.cpp

* moench: min exptime and also a firmware update required (#911)

* moench server: changed default values of adcphase for full speed from 300 to 150 and dac vipre_cds from 800 to 1280 (#921)

* client bug fix: m3 multi module bad channel file throws bad allocation when modules skipped, needed to add vectors in 2d vector of bad channel list (#919)

* 8.0.2.rc: client: blocking acquire stop with slave temporarily in waiting (#925)

* client: stopping a blocking acquire of multi modules checks status to catch slaves that might still be in waiting. Problem is (gotthard2 25um at least) slave is in waiting only temporarily before going go idle/stopped. So a 50ms sleep is necessary ot not throw an unnecessary error

* client: when stopping blocking acquire, wait up to 1s in 50ms increments for slave to stop waiting temporarily

* fix to rapidjson for build with gcc 14 (#928)

* 8.0.2.rc: m3 clkdiv0 20 (#923)

* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)

* g2: startup clk div back to 10 as in firmware but setting in software startup to 20

* 8.0.2.rc: moench empty data callback (#935)

* moench: empty data call back so that zmq sockets are still made and listened to in acquire that it waits for the dummy packet to be done

* moench zmq postprocessor: remove NEWZMQ ifdefs and remove connect for publisher socket

* changed enum from READOUT_ACTION_ZMQ to READOUT_ZMQ_ACTION for consistency

* 8.0.2.rc: client: status for blocking acquire stop with slave temporarily in waiting (#943)

* acq finish call back gets status squashed with default error but before that need to wait for gotthard slaves to catch up from waiting to stopped

* bug fixes related to file saving (#931)

* fix the file path resetting issue of GUI in the case where different modules have different fpath setting.

* fix stack-buffer-overflow issue when using HDF5 HDF5DataFile::parameterDataTypes have 64bit type (i.e. STD_U64LE), the size of fill_value should be at least 8 bytes.

* change the type of fill_value to uint64_t

* updated documentation from martin (#947)

* 802: jungfrau HW 1.0: adc output clock phase to 120  (#951)

* jungfrau: change adc output clock phase from 180 to 120 for v1.0 boards for reliable readout of adc #2

* formatting

* 802/release notes (#954)

* updated release notes

* versioning

* fixed a warning about narrowing conversion from size_t to int (#962)

* updating client versioning

* dont build doc for Tobi Schluter from libzmq, which uses iso-8859-1 and the umlaut cause compilation to fail on some machines (#972)

* updated release notes

---------

Co-authored-by: Filip Leonarski <filip.leonarski@psi.ch>
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
Co-authored-by: Z.H. Li <zhenghenge@gmail.com>
2024-09-17 09:44:14 +02:00
97f0c1fe46 8.0.1.rc (#891)
* forward declare zmq_msg_t and moved include

* removed zmq as dependency for slsdet (#870)

* Fixed path when building as submodule

* new moench data structure for offline processing

* meonch raw data and zmq process files updated to 7.0.3 version

* implemented config file for Zmq file

* raw data and zmq work with config file, but only with one file/interface

* zmq config change

* added config examples for zmq and rawdata

* update release notes, release versions

---------

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
Co-authored-by: froejdh_e <erik.frojdh@psi.ch>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
Co-authored-by: anberga <34126852+anberga@users.noreply.github.com>
2024-01-16 15:31:25 +01:00
a86fd00e59 Merge branch 'main' into 8.0.0.rc 2023-11-13 16:38:25 +01:00
24894667b7 release fw for ctb 2023-11-13 16:03:52 +01:00
4b414bfddb release notes 2023-11-12 15:39:58 +01:00
15d357d9ab release notes 2023-11-12 15:32:28 +01:00
f95de054f9 formatting 2023-11-12 15:29:34 +01:00
0aef8113dd documentation and examples 2023-11-12 15:11:36 +01:00
9785a41048 Merge branch '8.0.0.rc' of github.com:slsdetectorgroup/slsDetectorPackage into 8.0.0.rc 2023-11-10 17:29:47 +01:00
417e1a88a5 fixed doc 2023-11-10 17:29:35 +01:00
9c0dd0385d updating docs 2023-11-10 16:02:21 +01:00
Erik Frojdh
5ab64efe3e added python 3.12 to the conda build variants 2023-11-10 14:18:38 +01:00
Erik Frojdh
8f77e4d4fe added python 3.12 to the conda build variants 2023-11-10 14:17:40 +01:00
41c5b75b10 trigger signal issues handled at acquire (#862)
* if blocking and handling sync, only master gets blocking acq, slaves get non blocking as they are first and so dont get status or error caught when slaves dont get trigger (due to not connected etc) and acq returns with slaves still in waiting status. so check status of all in blocking acq

* for all dets with sync, ensure atleast one master when starting acq

* docs updated about sync
2023-11-10 11:24:18 +01:00
bfe53c6693 udpated release notes 2023-11-09 15:10:17 +01:00
f7997dd09a 8.0.0.rc: fix server logic in checking detector idle (#860)
* fix buggy logic in checking detector idle and an argument check
2023-11-09 15:07:03 +01:00
c64e87a2b6 7.0.3.rc: fix server logic in checking detector idle (#859)
* fix buggy logic in checking detector idle and an argument check
2023-11-09 14:21:11 +01:00
5eeb8e29c1 project version change 2023-11-08 17:31:29 +01:00
09697fa325 updated release notes 2023-11-08 17:30:07 +01:00
90b4daef39 updated release notes 2023-11-08 17:28:48 +01:00
2082f1eee7 updated release notes 2023-11-08 17:28:17 +01:00
d3a636b563 updated release notes 2023-11-08 17:24:56 +01:00
50b9b6ca39 update release notes 2023-11-08 14:14:04 +01:00
e86b57cdfc versioning, format, release notes, update test simulator (no need for psutil) 2023-11-08 12:12:17 +01:00
14e11e8b5b formatting and versioning 2023-11-08 11:43:09 +01:00
beafe86554 execute command inside server fixed (from fix simulator tests and exec command PR) (#856) 2023-11-08 09:26:00 +01:00
af3dc1e7f4 7.0.3.rc: execute command inside server fixed (from fix simulator tests and exec command PR) (#855)
* execute command inside server fixed (from fix simulator tests and exec command PR)
2023-11-08 09:25:52 +01:00
573177203b formatting 2023-11-07 14:51:15 +01:00
a3ca9ebce5 updating release notes 2023-11-07 14:35:42 +01:00
8174fc9691 Update RELEASE.txt 2023-11-07 12:34:10 +01:00
d6eac6da71 updated release notes 2023-11-07 11:22:09 +01:00
56c7ae4852 8.0.0.rc: fix py virtual test (#841)
* fix virtual test when it fails

* catching errors in tests and removing sigchild ignore so servers (process in background) executing commands will not fail (pclose no child processes, if sigchld is ignored) fixed

* uncommented python loading config

* somehow killal slsReciever in second detector test fails even though no receiver running

* fixing script for virtual simlator test:fixed issue with check if process running, fixed moench tests
2023-11-07 09:30:24 +01:00
9b9b09ceaf 703rc/tests/fix execute command (#842)
* fix execute command
* fix for tests for ctb
2023-11-07 09:29:48 +01:00
cfebaee2a5 handling inconsistent fnums to be -1 in gui, so when one sets 0 (change of value) will also give an exception (#853) 2023-11-06 16:11:40 +01:00
4613c54f57 handling inconsistent fnums to be -1 in gui, so when one sets 0 (change of value) will also give an exception (#852) 2023-11-06 16:11:25 +01:00
51f9d6f011 8.0.0rc: : gui acq finished callback for different status (#851)
* fix acquisition finished status to have different status for different modules, but does not have to be error. for eg. jf sync fw (2.4.1 gives idle for master and stopped for slaves when stopping acquiistion)
2023-11-06 16:08:23 +01:00
58ac7ac280 7.0.3.rc: gui acq finished callback for different status (#847)
* fix acquisition finished status to have different status for different modules, but does not have to be error. for eg. jf sync fw (2.4.1 gives idle for master and stopped for slaves when stopping acquiistion)
2023-11-06 16:07:38 +01:00
anberga
82edfa75d3 7.0.3.rc: process the raw data files as a list (#848)
* Added file list option for moenchRawDataProcess
2023-11-03 12:10:20 +01:00
35ed926047 formatting 2023-10-25 09:36:51 +02:00
4023ed0775 updated versioning 2023-10-25 09:36:04 +02:00
b6ef3bc39e updated release notest 2023-10-25 09:15:10 +02:00
2035666792 versioning and binaries updated 2023-10-25 08:43:23 +02:00
1ff4d806e7 minor 2023-10-25 08:25:02 +02:00
3861379653 updated release notes 2023-10-24 17:39:47 +02:00
91140bbb71 formatting 2023-10-24 11:17:18 +02:00
a5632fcbea fix warning for prev_val (variable size array) in tests (#837) 2023-10-23 15:55:13 +02:00
d44329117d fix warning for prev_val (variable size array) in tests (#836) 2023-10-23 15:52:59 +02:00
4a454aa698 tests for jf (#835) 2023-10-19 16:55:29 +02:00
0e43072db8 eiger required fw version to 32: fix for blocking trigger in quad (#833) 2023-10-18 17:04:26 +02:00
6c67025ea8 7.0.3.rc eiger: fw version to 32 (quad blocking trigger) (#832)
* eiger required fw version to 32: fix for blocking trigger in quad
2023-10-18 16:51:17 +02:00
e5ee27dbfa 8.0.0.rc jf: reconfigure chip when touching electron collection mode bit (#830)
* jf: if bit 14 in reg 0x5d (electron mode collection bit) is changed, configure chip if v1.1 and powered on. so touch writeregister (setbit/clearbit also calls write register in the end). replace when electroncollectionmode command introduced
2023-10-18 10:49:44 +02:00
601249cc71 8.0.0.rc jf: change status reg bits (#828)
* rewrite of status reg bits, waiting state includes both wati for trigger and start frame, blocking trigger only waits if its not in waiting for trigger and run busy enabled, error state connected in firmware
2023-10-18 10:36:56 +02:00
ff60b8c379 8.0.0.rc: jf sync: stopping master gives idle (#823)
* jf sync mode master could return idle when stopped and so not all modules return the same value and must check for 'stopped or idle', Also must throw if any of the module gives an error

* added contains_only to sls::Result (#827)

* added variadic template for checking if a result contains only specified values

* fix for gcc4.8

* renamed to Result::contains_only

* stop on only the positions

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2023-10-13 15:25:19 +02:00
37ce3d6f59 7.0.3.rc: jf sync: stopping master gives idle (#822)
* jf sync mode master could return idle when stopped and so not all modules return the same value and must check for 'stopped or idle', Also must throw if any of the module gives an error ( not jungfrau, but eiger could)

* added contains_only to sls::Result (#827)

* added variadic template for checking if a result contains only specified values

* fix for gcc4.8

* renamed to Result::contains_only

* stop on only the positions

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2023-10-13 12:27:43 +02:00
bf26533fd8 8.0.0.rc: jf fix pedestal (#820)
* jf pedestal fix: touch enable bit last
2023-10-05 10:28:51 +02:00
7106273521 update 2d gain plot (if no x and ymin/max changes or window resizing): setFixedWidth was updating for window resize, updated virtual servers for g2 and jungfrau to keep changing gain and data for every frame (#817) 2023-10-03 17:22:14 +02:00
1484d038de 7.03.rc: update 2d gain plot color map (if no x and ymin/max changes or window resizing): setFixedWidth was updating for window resize, updated virtual servers for g2 and jungfrau to keep changing gain and data for every frame. the data value (#818) 2023-10-03 17:22:03 +02:00
fb0090c79e removing the misleading word 'Simulating' when programmig fpga (#814) 2023-09-28 16:20:59 +02:00
adc68cd519 formatting 2023-09-28 15:51:40 +02:00
1566eef247 703rc/fix numeric limits (#812)
* fixed compilation for fedora for numeric_limits

* formatting
2023-09-28 10:49:02 +02:00
anberga
e7cd90db78 fixed crashing of moench03RawDataProcess when nframes>0 (#810) 2023-09-27 09:22:40 +02:00
45414149fe binaries in for the previous PR 2023-09-22 15:59:35 +02:00
48759f440e 703rc/fix port size (#802)
* validate port numbers in client

* validate port numbers created at virtual servers and receiver process as tcp ports
2023-09-18 08:59:53 +02:00
anberga
b367b7e431 fixed some interpolation issues (#796) 2023-08-28 13:38:19 +02:00
f0b2a6f6f9 update release notes 2023-08-25 14:02:50 +02:00
f761046bfc updated docs and versions 2023-07-12 16:50:13 +02:00
1a859b83db formatting 2023-07-12 16:06:31 +02:00
70bfc875a6 updating release notes 2023-07-11 17:02:27 +02:00
c0755308a4 updating release notes 2023-07-11 17:01:14 +02:00
ab5509e10c updating release notes 2023-07-11 17:00:42 +02:00
004cb26646 updated firmware versions for 7.0.2 2023-07-10 12:21:19 +02:00
a4f47a5945 synced master status running when setting to slave (#747)
* jf: unsync before setting master/slave and then sync (if it was set) to overcome master going into running state when making it a slave and synced

* add tests for this condition

* updated release notes, updated min fw version requirement for v1.0 boards
2023-05-25 11:04:05 +02:00
312f3f473d fix that only master starts second and not all (for start acq), typo with pos and masters list (#743) 2023-05-11 10:20:17 +02:00
5871086cd6 formatting 2023-05-08 17:04:04 +02:00
6a0fe823b3 enable fix g0 when in expert mode (when gain mode enabled and not just visible) (#736) 2023-05-08 14:20:21 +02:00
5912aae53e Rx roi zmq (#726)
adding rx_roi also in the zmq header for external guis to put the "yellow box".. sending full roi instead of -1, and sending for each zmq port. "(multiple yellow boxes)".
2023-05-08 12:23:05 +02:00
8833ccf5cc 7.0.2.rc (#721)
* row and column for jungfrau mixed up

* multi module jungfrau sync must do slaves first then master for start acquisition and send software trigger, and master first and then slaves for stopacquisition

* non blocking to slaves first and only then blocking/nonblocking to the master for sending software trigger(jungfrau multi mod sync)

* fixed get/set timing jungfrau when sync enabled, getsync during blocking acquire (for trigger or stop) will get stuck as it should ask the stop server

* switching between 1 and 2 interfaces did not set gui/client zmq port properly. Resulted in dummy streaming forever. fixed

* formatting, refactoring: const & for positions, multi mod M3 stop first master first

* adding missing cstdint for gcc 13

* Refactoring handle sync out, handling synchronization also for softwaretrigger for m3, for start/sync/stop for g2/g1

---------

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
2023-05-08 12:11:19 +02:00
77c558a7be formatting 2023-03-24 12:54:55 +01:00
378fc301b8 updating client version, release version and project_version in CMakeLists.txt 2023-03-23 15:43:17 +01:00
Dhanya Thattil
87d6e16090 7.0.1 fix det server version (#702)
* check server version before initial checks, catch old server version exception, get old server version as 64 bit and print it along with exception
2023-03-23 15:37:01 +01:00
Dhanya Thattil
2ef021041c rx_arping sigchld (#701)
* rx_arping pclose gave -1 due to sigchld being ignored, fixed with sig handler doing a wait
2023-03-23 13:58:40 +01:00
Dhanya Thattil
574127b5ac fix hdf5 compilation using det spec fields in header (#700)
* fix hdf5 compilation using det spec fields in header
2023-03-23 12:30:38 +01:00
122 changed files with 2065 additions and 4810 deletions

View File

@@ -1,33 +0,0 @@
name: Build on local RHEL8
on:
push:
branches:
- developer
workflow_dispatch:
permissions:
contents: read
jobs:
build:
runs-on: "detectors-software-RH8"
steps:
- uses: actions/checkout@v4
- name: Build library
run: |
source /home/gitea_runner/.bashrc
conda activate det
mkdir build && cd build
conda activate det
cmake .. -DSLS_USE_PYTHON=ON
make -j 2
cd ../pyctbgui
make
- name: Deploy to NFS update server
if: gitea.ref == 'refs/heads/developer'
run: |
sftp -r gitea_runner@mpc2935:/slsDetectorSoftware/RH8 <<< $'put build/bin'
sftp -r gitea_runner@mpc2935:/slsDetectorSoftware/RH8 <<< $'put pyctbgui'

View File

@@ -21,9 +21,9 @@ jobs:
- name: Build library
run: |
mkdir build && cd build
cmake .. -DSLS_USE_PYTHON=ON -DSLS_USE_TESTS=ON -DSLS_USE_SIMULATOR=ON
cmake .. -DSLS_USE_PYTHON=ON -DSLS_USE_TESTS=ON
make -j 2
- name: C++ unit tests
working-directory: ${{gitea.workspace}}/build
run: ctest -j1 --rerun-failed --output-on-failure
run: ctest

View File

@@ -1,30 +0,0 @@
name: Build on local RHEL9
on:
push:
branches:
- developer
workflow_dispatch:
permissions:
contents: read
jobs:
build:
runs-on: "detectors-software-RH9"
steps:
- uses: actions/checkout@v4
- name: Build library
run: |
mkdir build && cd build
cmake -DSLS_USE_PYTHON=ON -DPython_EXECUTABLE=/usr/bin/python3.13 -DPython_INCLUDE_DIR=/usr/include/python3.13 -DPython_LIBRARY=/usr/lib64/libpython3.13.so ..
make -j 2
cd ../pyctbgui
make
- name: Deploy to NFS update server
if: gitea.ref == 'refs/heads/developer'
run: |
sftp -r gitea_runner@mpc2935:/slsDetectorSoftware/RH9 <<< $'put build/bin'
sftp -r gitea_runner@mpc2935:/slsDetectorSoftware/RH9 <<< $'put pyctbgui'

View File

@@ -19,9 +19,9 @@ jobs:
- name: Build library
run: |
mkdir build && cd build
cmake .. -DSLS_USE_PYTHON=ON -DSLS_USE_TESTS=ON -DSLS_USE_SIMULATOR=ON
cmake .. -DSLS_USE_PYTHON=ON -DSLS_USE_TESTS=ON
make -j 2
- name: C++ unit tests
working-directory: ${{gitea.workspace}}/build
run: ctest -j1 --rerun-failed --output-on-failure
run: ctest

View File

@@ -23,7 +23,7 @@ jobs:
- uses: actions/checkout@v4
- name: Build wheels
run: pipx run cibuildwheel==3.2.1
run: pipx run cibuildwheel==2.23.0
- uses: actions/upload-artifact@v4
with:

View File

@@ -37,7 +37,7 @@ jobs:
- name: C++ unit tests
working-directory: ${{github.workspace}}/build
run: ctest -C ${{env.BUILD_TYPE}} -j1 --rerun-failed --output-on-failure
run: ctest -C ${{env.BUILD_TYPE}} -j1
- name: Python unit tests
working-directory: ${{github.workspace}}/build/bin

View File

@@ -1,47 +0,0 @@
name: Build and deploy slsdetlib
on:
release:
types:
- published
jobs:
build:
strategy:
fail-fast: false
matrix:
platform: [ubuntu-latest, ] # macos-12, windows-2019]
python-version: ["3.12",]
runs-on: ${{ matrix.platform }}
# The setup-miniconda action needs this to activate miniconda
defaults:
run:
shell: "bash -l {0}"
steps:
- uses: actions/checkout@v4
- name: Get conda
uses: conda-incubator/setup-miniconda@v3.0.4
with:
python-version: ${{ matrix.python-version }}
channels: conda-forge
- name: Prepare
run: conda install conda-build conda-verify pytest anaconda-client
- name: Enable upload
run: conda config --set anaconda_upload yes
- name: Build
env:
CONDA_TOKEN: ${{ secrets.CONDA_TOKEN }}
run: conda build conda-recipes/main-library --user slsdetectorgroup --token ${CONDA_TOKEN} --output-folder build_output
- name: Upload all Conda to github as artifacts
uses: actions/upload-artifact@v4
with:
name: conda-packages
path: build_output/** # Uploads all packages

View File

@@ -1,47 +0,0 @@
name: deploy slsdet
on:
release:
types:
- published
jobs:
build:
strategy:
fail-fast: false
matrix:
platform: [ubuntu-latest, ] # macos-12, windows-2019]
python-version: ["3.12",]
runs-on: ${{ matrix.platform }}
# The setup-miniconda action needs this to activate miniconda
defaults:
run:
shell: "bash -l {0}"
steps:
- uses: actions/checkout@v4
- name: Get conda
uses: conda-incubator/setup-miniconda@v3.0.4
with:
python-version: ${{ matrix.python-version }}
channels: conda-forge
- name: Prepare
run: conda install conda-build conda-verify pytest anaconda-client
- name: Enable upload
run: conda config --set anaconda_upload yes
- name: Build
env:
CONDA_TOKEN: ${{ secrets.CONDA_TOKEN }}
run: conda build conda-recipes/python-client --user slsdetectorgroup --token ${CONDA_TOKEN} --output-folder build_output
- name: Upload all Conda packages
uses: actions/upload-artifact@v4
with:
name: conda-packages
path: build_output/** # Uploads all packages

View File

@@ -24,16 +24,6 @@ include(cmake/SlsAddFlag.cmake)
include(cmake/helpers.cmake)
find_package(Threads REQUIRED)
# POSIX threads are required for the moment but we use CMake to find them
# Once migrated to std::thread this can be removed
if(NOT CMAKE_USE_PTHREADS_INIT)
message(FATAL_ERROR "A POSIX threads (pthread) implementation is required, but was not found.")
endif()
option(SLS_USE_SYSTEM_ZMQ "Use system installed libzmq" OFF)
# Using FetchContent to get libzmq
include(FetchContent)
@@ -60,111 +50,51 @@ if(NOT PATCH_EXECUTABLE)
message(FATAL_ERROR "The 'patch' tool is required for patching lib zeromq. Please install it.")
endif()
if(SLS_USE_SYSTEM_ZMQ)
# find_package(ZeroMQ REQUIRED)
# 1) Try a CMake package config if available (vcpkg, Homebrew, source builds)
# Many installs export either ZeroMQ::libzmq or libzmq.
find_package(ZeroMQ QUIET CONFIG)
set(ZEROMQ_TARGET "")
if (TARGET ZeroMQ::libzmq)
set(ZEROMQ_TARGET ZeroMQ::libzmq)
message(STATUS "Found target: ${ZEROMQ_TARGET} version: ${ZeroMQ_VERSION}")
elseif (TARGET libzmq)
set(ZEROMQ_TARGET libzmq)
message(STATUS "Found target: ${ZEROMQ_TARGET} version: ${ZeroMQ_VERSION}")
elseif (TARGET ZeroMQ::ZeroMQ) # rare older naming
set(ZEROMQ_TARGET ZeroMQ::ZeroMQ)
message(STATUS "Found target: ${ZEROMQ_TARGET} version: ${ZeroMQ_VERSION}")
endif()
# 2) Fallback: use pkg-config hints + manual find_* to create an imported target
if (NOT ZEROMQ_TARGET)
find_package(PkgConfig QUIET)
if (PkgConfig_FOUND)
pkg_check_modules(PC_ZeroMQ QUIET libzmq)
endif()
find_path(ZEROMQ_INCLUDE_DIR
NAMES zmq.h
HINTS ${PC_ZeroMQ_INCLUDE_DIRS}
)
find_library(ZEROMQ_LIBRARY
NAMES zmq libzmq
HINTS ${PC_ZeroMQ_LIBRARY_DIRS}
)
if (ZEROMQ_INCLUDE_DIR AND ZEROMQ_LIBRARY)
add_library(libzmq UNKNOWN IMPORTED)
set_target_properties(libzmq PROPERTIES
IMPORTED_LOCATION "${ZEROMQ_LIBRARY}"
INTERFACE_INCLUDE_DIRECTORIES "${ZEROMQ_INCLUDE_DIR}"
)
set(ZEROMQ_TARGET libzmq)
endif()
message(STATUS "ZeroMQ version (pkg-config): ${PC_ZeroMQ_VERSION}")
endif()
# 3) Error out if still not found, with a helpful message
if (NOT ZEROMQ_TARGET)
message(FATAL_ERROR "ZeroMQ (libzmq) not found. Please install ZeroMQ development files.")
endif()
# Use it
# target_link_libraries(your_target PRIVATE ${ZEROMQ_TARGET})
message(STATUS "Using system installed libzmq: ${ZeroMQ_LIBRARIES}")
message(STATUS "ZeroMQ target: ${ZEROMQ_TARGET}")
message(STATUS "ZeroMQ include dirs: ${ZeroMQ_INCLUDE_DIRS}")
if(SLS_FETCH_ZMQ_FROM_GITHUB)
# Opt in to pull down a zmq version from github instead of
# using the bundled version
FetchContent_Declare(
libzmq
GIT_REPOSITORY https://github.com/zeromq/libzmq.git
GIT_TAG v${SLS_LIBZMQ_VERSION}
PATCH_COMMAND ${CMAKE_COMMAND} -E chdir <SOURCE_DIR> patch -p1 < ${CMAKE_CURRENT_SOURCE_DIR}/libs/libzmq/libzmq_cmake_version.patch
UPDATE_DISCONNECTED 1
)
else()
if(SLS_FETCH_ZMQ_FROM_GITHUB)
# Opt in to pull down a zmq version from github instead of
# using the bundled version
FetchContent_Declare(
libzmq
GIT_REPOSITORY https://github.com/zeromq/libzmq.git
GIT_TAG v${SLS_LIBZMQ_VERSION}
PATCH_COMMAND ${CMAKE_COMMAND} -E chdir <SOURCE_DIR> patch -p1 < ${CMAKE_CURRENT_SOURCE_DIR}/libs/libzmq/libzmq_cmake_version.patch
UPDATE_DISCONNECTED 1
)
else()
# Standard behaviour use libzmq included in this repo (libs/libzmq)
FetchContent_Declare(
libzmq
URL ${CMAKE_CURRENT_SOURCE_DIR}/libs/libzmq/libzmq-${SLS_LIBZMQ_VERSION}.tar.gz
URL_HASH MD5=cc20b769ac10afa352e5ed2769bb23b3
PATCH_COMMAND ${CMAKE_COMMAND} -E chdir <SOURCE_DIR> patch -p1 < ${CMAKE_CURRENT_SOURCE_DIR}/libs/libzmq/libzmq_cmake_version.patch
UPDATE_DISCONNECTED 1
)
endif()
# Disable unwanted options from libzmq
set(BUILD_TESTS OFF CACHE BOOL "Switch off libzmq test build")
set(BUILD_SHARED OFF CACHE BOOL "Switch off libzmq shared libs")
set(WITH_PERF_TOOL OFF CACHE BOOL "")
set(ENABLE_CPACK OFF CACHE BOOL "")
set(ENABLE_CLANG OFF CACHE BOOL "")
set(ENABLE_CURVE OFF CACHE BOOL "")
set(ENABLE_DRAFTS OFF CACHE BOOL "")
set(ENABLE_PRECOMPILED OFF CACHE BOOL "")
set(WITH_DOC OFF CACHE BOOL "")
set(WITH_DOCS OFF CACHE BOOL "")
# Using GetProperties and Populate to be able to exclude zmq
# from install (not possible with FetchContent_MakeAvailable(libzmq))
FetchContent_GetProperties(libzmq)
if(NOT libzmq_POPULATED)
FetchContent_Populate(libzmq)
add_subdirectory(${libzmq_SOURCE_DIR} ${libzmq_BINARY_DIR} EXCLUDE_FROM_ALL)
endif()
# Standard behaviour use libzmq included in this repo (libs/libzmq)
FetchContent_Declare(
libzmq
URL ${CMAKE_CURRENT_SOURCE_DIR}/libs/libzmq/libzmq-${SLS_LIBZMQ_VERSION}.tar.gz
URL_HASH MD5=cc20b769ac10afa352e5ed2769bb23b3
PATCH_COMMAND ${CMAKE_COMMAND} -E chdir <SOURCE_DIR> patch -p1 < ${CMAKE_CURRENT_SOURCE_DIR}/libs/libzmq/libzmq_cmake_version.patch
UPDATE_DISCONNECTED 1
)
endif()
# Disable unwanted options from libzmq
set(BUILD_TESTS OFF CACHE BOOL "Switch off libzmq test build")
set(BUILD_SHARED OFF CACHE BOOL "Switch off libzmq shared libs")
set(WITH_PERF_TOOL OFF CACHE BOOL "")
set(ENABLE_CPACK OFF CACHE BOOL "")
set(ENABLE_CLANG OFF CACHE BOOL "")
set(ENABLE_CURVE OFF CACHE BOOL "")
set(ENABLE_DRAFTS OFF CACHE BOOL "")
set(ENABLE_PRECOMPILED OFF CACHE BOOL "")
set(WITH_DOC OFF CACHE BOOL "")
set(WITH_DOCS OFF CACHE BOOL "")
# Using GetProperties and Populate to be able to exclude zmq
# from install (not possible with FetchContent_MakeAvailable(libzmq))
FetchContent_GetProperties(libzmq)
if(NOT libzmq_POPULATED)
FetchContent_Populate(libzmq)
add_subdirectory(${libzmq_SOURCE_DIR} ${libzmq_BINARY_DIR} EXCLUDE_FROM_ALL)
endif()
include(GNUInstallDirs)
# If conda build, always set lib dir to 'lib'
@@ -192,7 +122,7 @@ endif()
option(SLS_USE_HDF5 "HDF5 File format" OFF)
option(SLS_BUILD_SHARED_LIBRARIES "Build shared libaries" OFF)
option(SLS_BUILD_SHARED_LIBRARIES "Build shared libaries" ON)
option(SLS_USE_TEXTCLIENT "Text Client" ON)
option(SLS_USE_DETECTOR "Detector libs" ON)
option(SLS_USE_RECEIVER "Receiver" ON)
@@ -341,9 +271,6 @@ if (NOT TARGET slsProjectCSettings)
-Wno-format-truncation
)
sls_disable_c_warning("-Wstringop-truncation")
target_link_libraries(slsProjectCSettings INTERFACE
Threads::Threads
)
endif()

View File

@@ -1,41 +1,55 @@
SLS Detector Package Major Release x.x.x released on xx.xx.202x
===============================================================
SLS Detector Package Minor Release 10.0.1 released on ?
================================================================
This document describes the differences between vx.x.x and v10.0.0
This document describes the differences between v10.0.1 and v10.0.0
CONTENTS
--------
1 New, Changed or Resolved Features
1.1 Compilation
1.2 Callback
1.3 Python
1.4 Client
1.5 Detector Server
1.6 Simulator
1.7 Receiver
1.8 Gui
2 On-board Detector Server Compatibility
3 Firmware Requirements
4 Kernel Requirements
5 Download, Documentation & Support
1 Changes
1.1 Compilation Changes
1.2 New or Changed Features
1.2.1 Breaking API
1.2.2 Resolved or Changed Features
1.2.3 New Features
3 On-board Detector Server Compatibility
4 Firmware Requirements
5 Kernel Requirements
6 Download, Documentation & Support
1 New, Changed or Resolved Features
=====================================
1 Changes
==========
Building shared libraries is disabled by default. If you need to link
against any of the libSls*.so libraries, you can enable this by passing
-DSLS_BUILD_SHARED_LIBRARIES=ON to CMake.
Added SLS_USE_SYSTEM_ZMQ option (default OFF) to use the libzmq of the host
instead of the one included in our repo.
Experimental support for building the detector client (including python bindings) on macOS
1.1 Compilation Changes
========================
1.2 New or Changed Features
============================
Python
-------
* receiver ROI can be set from Python using command ``rx_roi``(it supports any sequence of four or two (for mythen3 and gotthard) ints e.g. a tuple (xmin, xmax, ymin, ymax) or a sequence of such for multiple ROIS)
* one can clear all ROI's from Python using command ``rx_clearroi``
1.2.1 Breaking API
===================
1.2.2 Resolved or Changed Features
===================================
1.2.3 New Features
===================
``rx_dbitlist`` keeps the order of the passed bit list
2 On-board Detector Server Compatibility
==========================================

View File

@@ -1 +1 @@
0.0.0
10.0.0

View File

@@ -19,7 +19,6 @@ cmake .. -G Ninja \
-DSLS_USE_PYTHON=OFF \
-DCMAKE_BUILD_TYPE=Release \
-DSLS_USE_HDF5=OFF \
-DSLS_USE_SYSTEM_ZMQ=ON \
NCORES=$(getconf _NPROCESSORS_ONLN)
echo "Building using: ${NCORES} cores"

View File

@@ -29,7 +29,6 @@ requirements:
- libtiff
- zlib
- expat
- zeromq
run:
- libstdcxx-ng

View File

@@ -2,8 +2,6 @@ python:
- 3.11
- 3.12
- 3.13
- 3.14
c_compiler:
- gcc # [linux]
@@ -15,4 +13,4 @@ cxx_compiler:
- gxx # [linux]
c_stdlib_version: # [linux]
- 2.17 # [linux]
- 2.17 # [linux]

View File

@@ -9,11 +9,11 @@ package:
build:
number: 0
script:
- unset CMAKE_GENERATOR && {{ PYTHON }} -m pip install . -vv --config-settings=cmake.define.SLS_USE_SYSTEM_ZMQ=ON # [not win]
- unset CMAKE_GENERATOR && {{ PYTHON }} -m pip install . -vv # [not win]
requirements:
build:
- python
- python {{python}}
- {{ compiler('c') }}
- {{ stdlib("c") }}
- {{ compiler('cxx') }}
@@ -21,7 +21,7 @@ requirements:
host:
- cmake
- ninja
- python
- python {{python}}
- pip
- scikit-build-core
- pybind11 >=2.13.0
@@ -31,7 +31,7 @@ requirements:
- catch2
run:
- python
- python {{python}}
- numpy

View File

@@ -11,8 +11,7 @@ add_executable(gendoc src/gendoc.cpp)
# This is a bit hacky, but better than exposing stuff?
target_include_directories(gendoc PRIVATE ${PROJECT_SOURCE_DIR}/slsDetectorSoftware/src)
target_link_libraries(gendoc PRIVATE
slsDetectorStatic
slsDetectorShared
)
set_target_properties(gendoc PROPERTIES
RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin

View File

@@ -20,7 +20,7 @@ print(sys.path)
# -- Project information -----------------------------------------------------
project = 'slsDetectorPackage @PROJECT_VERSION@'
project = 'slsDetectorPackage'
copyright = '2020, PSD Detector Group'
author = 'PSD Detector Group'
version = '@PROJECT_VERSION@'

View File

@@ -3,13 +3,13 @@
You can adapt this file completely to your liking, but it should at least
contain the root `toctree` directive.
slsDetectorPackage
Welcome to slsDetectorPackage's documentation!
==============================================
.. note ::
This is the documentation for the latest development version of slsDetectorPackage.
For further detector specific documentation, visit `this page <https://www.psi.ch/en/detectors/documentation>`__.
For further documentation, visit the official page: https://www.psi.ch/en/detectors/documentation
.. toctree::
:maxdepth: 3

View File

@@ -28,7 +28,7 @@ This instructs the firmware to execute the commands from address 0 to 4 (includi
.. code-block::
start [Ctb, Xilinx_Ctb]
patternstart [Mythen3, Ctb, Xilinx_Ctb]
patternstart [Mythen3]
The maximal number of patword addresses is 8192. However, it is possible to extend the length of the pattern sequence using loops and wait commands. Loops can be configured with the following commands:
@@ -70,11 +70,11 @@ The mappings of bit positions in the pattern word to signals/pads of the FPGA ar
.. table::
+----+---+------+----+----------+----------+----------------+
| 63 | 62| 61-57| 56 | 55-48 | 47-32 | 31-0 |
+----+---+------+----+----------+----------+----------------+
| A | D| --- | T | EXTIO | DO | DIO |
+----+---+------+----+----------+----------+----------------+
+----+---+------+----+----------+-------------------+----------------+
| 63 | 62| 61-57| 56 | 55-48 | 47-32 | 31-0 |
+----+---+------+----+----------+-------------------+----------------+
| A | D| --- | T | EXTIO | DO, stream source | DIO |
+----+---+------+----+----------+-------------------+----------------+
DIO: Driving the 32 FPGA pins corresponding to the lowest 32 bits of the patioctrl command. If bits in patioctrl are 0, the same bit positions in DIO will switch to input pins and connect to dbit sampling. Additionally, some of these 32 bits have an automatic override by detector-specific statemachines which is active whenever one of these statemachines is running (currently bits 7,8,11,14 and 20).
@@ -119,12 +119,4 @@ DIO: Driving the 32 FPGA pins corresponding to the lowest 32 bits of the patioct
| SR_MODE | clk | EN | PULSE | RD | CHSIN | ANAMode | TBLOAD |
+---------+-----+-------+-------+----+-------+---------+--------+
For Mythen3 the pattern word only connects to output pins of the FPGA when the pattern is running. Afterwards the signals will switch back to other logic in the FPGA. Both CTB's hold the last executed pattern word until a new pattern is started.
**Relation of received data to pattern execution**
In the default configuration the Ctb will send out udp packets to the sls_receiver for every end of a pattern execution. This behavior can be changed using STREAMING_CTRL_REG, where one can configure a bit position in the 64-bit pattern word to trigger udp packets. This allows to send more than one packet per pattern or also no packets at all.
The "patternstart" command on the ctb exectues the pattern. As long as streaming_ctrl_reg is disabeld, every pattern execution using this command will not send UDP packets.
For Mythen3 the sending of udp packets is not connected to pattern execution.
For Mythen3 the pattern word only connects to output pins of the FPGA when the pattern is running. Afterwards the signals will switch back to other logic in the FPGA. Both CTB's hold the last executed pattern word until a new pattern is started.

View File

@@ -50,12 +50,6 @@ datetime.timedelta, DurationWrapper or by setting the time in seconds.
>>> d.getExptime()
[sls::DurationWrapper(total_seconds: 181.23 count: 181230000000)]
# In C++ it is possible to use chrono literals to set time more easily
# d.setExptime(7ms). However, this is not possible due to pythons syntax.
# instead we can create a unit that we use for conversion.
>>> ms = dt.timedelta(milliseconds = 1)
>>> d.exptime = 7.5*ms
------------------------------------

View File

@@ -154,8 +154,6 @@ class AdcTab(QtWidgets.QWidget):
self.mainWindow.analogPlots[i].setData(waveform)
plotName = getattr(self.view, f"labelADC{i}").text()
waveforms[plotName] = waveform
elif checkBoxEn.isChecked():
idx += 1
return waveforms
@recordOrApplyPedestal

View File

@@ -50,20 +50,20 @@ class AcquisitionTab(QtWidgets.QWidget):
self.plotTab = self.mainWindow.plotTab
self.toggleStartButton(False)
if self.det.type == detectorType.XILINX_CHIPTESTBOARD:
self.view.labelRunF.setDisabled(True)
self.view.labelADCF.setDisabled(True)
self.view.labelADCPhase.setDisabled(True)
self.view.labelADCPipeline.setDisabled(True)
self.view.labelDBITF.setDisabled(True)
self.view.labelDBITPhase.setDisabled(True)
self.view.labelDBITPipeline.setDisabled(True)
self.view.spinBoxRunF.setDisabled(True)
self.view.spinBoxADCF.setDisabled(True)
self.view.spinBoxADCPhase.setDisabled(True)
self.view.spinBoxADCPipeline.setDisabled(True)
self.view.spinBoxDBITF.setDisabled(True)
self.view.spinBoxDBITPhase.setDisabled(True)
self.view.spinBoxDBITPipeline.setDisabled(True)
self.view.labelRunF.setText("Run Clock Frequency (kHz):")
self.view.labelDBITF.setText("DBIT Clock Frequency (kHz):")
self.view.labelADCF.setText("ADC Clock Frequency (kHz):")
self.view.spinBoxRunF.setMaximum(250000)
self.view.spinBoxDBITF.setMaximum(250000)
self.view.spinBoxADCF.setMaximum(250000)
def connect_ui(self):
# For Acquistions Tab
@@ -72,13 +72,12 @@ class AcquisitionTab(QtWidgets.QWidget):
self.view.spinBoxAnalog.editingFinished.connect(self.setAnalog)
self.view.spinBoxDigital.editingFinished.connect(self.setDigital)
if self.det.type in [detectorType.CHIPTESTBOARD, detectorType.XILINX_CHIPTESTBOARD]:
if self.det.type == detectorType.CHIPTESTBOARD:
self.view.spinBoxRunF.editingFinished.connect(self.setRunFrequency)
self.view.spinBoxADCF.editingFinished.connect(self.setADCFrequency)
self.view.spinBoxDBITF.editingFinished.connect(self.setDBITFrequency)
if self.det.type == detectorType.CHIPTESTBOARD:
self.view.spinBoxADCPhase.editingFinished.connect(self.setADCPhase)
self.view.spinBoxADCPipeline.editingFinished.connect(self.setADCPipeline)
self.view.spinBoxDBITF.editingFinished.connect(self.setDBITFrequency)
self.view.spinBoxDBITPhase.editingFinished.connect(self.setDBITPhase)
self.view.spinBoxDBITPipeline.editingFinished.connect(self.setDBITPipeline)
@@ -99,13 +98,12 @@ class AcquisitionTab(QtWidgets.QWidget):
self.getAnalog()
self.getDigital()
if self.det.type in [detectorType.CHIPTESTBOARD, detectorType.XILINX_CHIPTESTBOARD]:
if self.det.type == detectorType.CHIPTESTBOARD:
self.getRunFrequency()
self.getADCFrequency()
self.getDBITFrequency()
if self.det.type == detectorType.CHIPTESTBOARD:
self.getADCPhase()
self.getADCPipeline()
self.getDBITFrequency()
self.getDBITPhase()
self.getDBITPipeline()

View File

@@ -17,7 +17,7 @@ dependencies = [
[tool.cibuildwheel]
before-all = "uname -a"
build = "cp{311,312,313,314}-manylinux_x86_64"
build = "cp{311,312,313}-manylinux_x86_64"
[tool.scikit-build.build]
verbose = true

View File

@@ -12,7 +12,6 @@ pybind11_add_module(_slsdet
src/duration.cpp
src/DurationWrapper.cpp
src/pedestal.cpp
src/bit.cpp
)
target_link_libraries(_slsdet PUBLIC

View File

@@ -27,9 +27,6 @@ from .defines import *
IpAddr = _slsdet.IpAddr
MacAddr = _slsdet.MacAddr
RegisterAddress = _slsdet.RegisterAddress
BitAddress = _slsdet.BitAddress
RegisterValue = _slsdet.RegisterValue
scanParameters = _slsdet.scanParameters
currentSrcParameters = _slsdet.currentSrcParameters
DurationWrapper = _slsdet.DurationWrapper

View File

@@ -3,7 +3,6 @@
from ._slsdet import CppDetectorApi
from ._slsdet import slsDetectorDefs
from ._slsdet import IpAddr, MacAddr
from ._slsdet import RegisterAddress, RegisterValue, BitAddress
runStatus = slsDetectorDefs.runStatus
timingMode = slsDetectorDefs.timingMode
@@ -1814,109 +1813,6 @@ class Detector(CppDetectorApi):
[Eiger] Address is +0x100 for only left, +0x200 for only right.
"""
return self._register
def define_reg(self, name, addr):
"""
[Ctb] Define a name for a register to be used later with reg.
Example
--------
d.define_reg('myreg',addr=0x6)
"""
addr = RegisterAddress(addr)
self.setRegisterDefinition(name, addr)
def define_bit(self, name, addr, bit):
"""
[Ctb] Define a name for a bit in a register to be used later with setBit/clearBit/getBit
Example
--------
d.define_bit('mybit',addr=0x6, bit=7)
"""
addr = RegisterAddress(addr)
bit = BitAddress(addr, bit)
self.setBitDefinition(name, bit)
def setBit(self, bit_or_addr, number=None):
"""
Set a bit in a register
[Ctb] Can use a named bit address
Example
--------
d.setBit(0x5, 3)
#Ctb
d.setBit('mybit')
myreg = RegisterAddress(0x5)
mybit = BitAddress(myreg, 5)
d.setBit(mybit)
"""
#Old usage passing two ints
if isinstance(bit_or_addr, int):
return super().setBit(bit_or_addr, number)
#New usage with str or BitAddress
if isinstance(bit_or_addr, str):
bit_or_addr = self.getBitDefinition(bit_or_addr)
return super().setBit(bit_or_addr)
def clearBit(self, bit_or_addr, number=None):
"""
Clear a bit in a register
[Ctb] Can use a named bit address
Example
--------
d.clearBit(0x5, 3)
#Ctb
d.clearBit('mybit')
myreg = RegisterAddress(0x5)
mybit = BitAddress(myreg, 5)
d.clearBit(mybit)
"""
#Old usage passing two ints
if isinstance(bit_or_addr, int):
return super().clearBit(bit_or_addr, number)
#New usage with str or BitAddress
if isinstance(bit_or_addr, str):
bit_or_addr = self.getBitDefinition(bit_or_addr)
return super().clearBit(bit_or_addr)
@element
def getBit(self, bit_or_addr, number=None):
"""
Get a bit from a register
[Ctb] Can use a named bit address
Example
--------
d.getBit(0x5, 3)
#Ctb
d.getBit('mybit')
myreg = RegisterAddress(0x5)
mybit = BitAddress(myreg, 5)
d.getBit(mybit)
"""
#Old usage passing two ints
if isinstance(bit_or_addr, int):
return super().getBit(bit_or_addr, number)
#New usage with str or BitAddress
if isinstance(bit_or_addr, str):
bit_or_addr = self.getBitDefinition(bit_or_addr)
return super().getBit(bit_or_addr)
@property
def slowadc(self):
@@ -3450,11 +3346,7 @@ class Detector(CppDetectorApi):
@property
@element
def runclk(self):
"""
[Ctb] Sets Run clock frequency in MHz. \n
[Xilinx Ctb] Sets Run clock frequency in kHz.
"""
"""[Ctb] Run clock in MHz."""
return self.getRUNClock()
@runclk.setter
@@ -3535,11 +3427,7 @@ class Detector(CppDetectorApi):
@property
@element
def dbitclk(self):
"""
[Ctb] Sets clock for latching the digital bits in MHz. \n
[Xilinx Ctb] clock for latching the digital bits in kHz.
"""
"""[Ctb] Clock for latching the digital bits in MHz."""
return self.getDBITClock()
@dbitclk.setter
@@ -3666,11 +3554,7 @@ class Detector(CppDetectorApi):
@property
@element
def adcclk(self):
"""
[Ctb] Sets ADC clock frequency in MHz. \n
[Xilinx Ctb] Sets ADC clock frequency in kHz.
"""
"""[Ctb] Sets ADC clock frequency in MHz. """
return self.getADCClock()
@adcclk.setter

View File

@@ -1,28 +1,13 @@
# SPDX-License-Identifier: LGPL-3.0-or-other
# Copyright (C) 2021 Contributors to the SLS Detector Package
from ._slsdet import RegisterValue, RegisterAddress
from .utils import element
class Register:
def __init__(self, detector):
self._detector = detector
@element
def __getitem__(self, key):
if isinstance(key, str):
key = self._detector.getRegisterDefinition(key)
return self._detector.readRegister(key)
def __setitem__(self, key, value):
if isinstance(key, str):
key = self._detector.getRegisterDefinition(key)
elif isinstance(key, int):
key = RegisterAddress(key)
if isinstance(value, int):
value = RegisterValue(value)
self._detector.writeRegister(key, value, False)
class Adc_register:

View File

@@ -141,38 +141,21 @@ def make_ip(arg):
def make_mac(arg):
return _make(arg, _slsdet.MacAddr)
def make_register_address(arg):
return _make(arg, _slsdet.RegisterAddress)
def make_bit_address(arg):
return _make(arg, _slsdet.BitAddress)
def make_register_value(arg):
return _make(arg, _slsdet.RegisterValue)
def make_path(arg):
return _make(arg, Path)
def _make(arg, transform):
"""Helper function for make_mac, make_ip and other special cases for
"""Helper function for make_mac and make_ip special cases for
dict, list and tuple. Otherwise just calls transform"""
if isinstance(arg, dict):
return {key: _make(value, transform) for key, value in arg.items()}
return {key: transform(value) for key, value in arg.items()}
elif isinstance(arg, list):
return [_make(a, transform) for a in arg]
return [transform(a) for a in arg]
elif isinstance(arg, tuple):
# special case for BitAddress
if transform is _slsdet.BitAddress:
addr, bit = arg
if isinstance(addr, int):
addr = _slsdet.RegisterAddress(addr)
return transform(addr, bit)
else:
# general case: recursively transform each element
return tuple(_make(a, transform) for a in arg)
return tuple(transform(a) for a in arg)
else:
# single element
return transform(arg)

View File

@@ -1,55 +0,0 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
/*
This file contains Python bindings for the RegisterAddr, BitAddress and
RegisterValue classes.
*/
#include "py_headers.h"
#include "sls/bit_utils.h"
namespace py = pybind11;
using sls::BitAddress;
using sls::RegisterAddress;
using sls::RegisterValue;
void init_bit(py::module &m) {
py::class_<RegisterAddress>(m, "RegisterAddress")
.def(py::init())
.def(py::init<const std::string &>())
.def(py::init<uint32_t>())
.def(py::init<const RegisterAddress &>())
.def("__repr__", &RegisterAddress::str)
.def("str", &RegisterAddress::str)
.def("uint32", [](const RegisterAddress &v) { return static_cast<uint32_t>(v); })
.def(py::self == py::self)
.def(py::self != py::self);
py::class_<BitAddress>(m, "BitAddress")
.def(py::init())
.def(py::init<RegisterAddress, int>())
.def("__repr__", &BitAddress::str)
.def("str", &BitAddress::str)
.def("address", &BitAddress::address)
.def("bitPosition", &BitAddress::bitPosition)
.def("setAddress", &BitAddress::setAddress)
.def("setBitPosition", &BitAddress::setBitPosition)
.def(py::self == py::self)
.def(py::self != py::self);
py::class_<RegisterValue>(m, "RegisterValue")
.def(py::init<>())
.def(py::init<const std::string &>())
.def(py::init<uint32_t>())
.def(py::init<const RegisterValue &>())
.def("__repr__", &RegisterValue::str)
.def("str", &RegisterValue::str)
.def("uint32", [](const RegisterValue &v) { return static_cast<uint32_t>(v); })
.def(py::self == py::self)
.def(py::self != py::self)
.def("__ior__", [](RegisterValue &v, uint32_t rhs) -> RegisterValue& {
v |= rhs;
return v;
}, py::return_value_policy::reference_internal);
}

View File

@@ -8,7 +8,6 @@
#include "sls/Detector.h"
#include "sls/TimeHelper.h"
#include "sls/ToString.h"
#include "sls/bit_utils.h"
#include "sls/network_utils.h"
#include "sls/sls_detector_defs.h"
@@ -16,13 +15,10 @@
#include <chrono>
namespace py = pybind11;
void init_det(py::module &m) {
using sls::BitAddress;
using sls::defs;
using sls::Detector;
using sls::ns;
using sls::Positions;
using sls::RegisterAddress;
using sls::RegisterValue;
using sls::Result;
m.def("freeSharedMemory",
@@ -946,6 +942,7 @@ void init_det(py::module &m) {
(void (Detector::*)(const std::vector<defs::ROI> &)) &
Detector::setRxROI,
py::arg());
CppDetectorApi.def("clearRxROI",
(void (Detector::*)()) & Detector::clearRxROI);
CppDetectorApi.def(
@@ -1799,78 +1796,6 @@ void init_det(py::module &m) {
(std::string(Detector::*)(const defs::dacIndex) const) &
Detector::getSlowADCName,
py::arg());
CppDetectorApi.def("getRegisterDefinitionsCount",
(int (Detector::*)() const) &
Detector::getRegisterDefinitionsCount);
CppDetectorApi.def(
"setRegisterDefinition",
(void (Detector::*)(const std::string &, sls::RegisterAddress)) &
Detector::setRegisterDefinition,
py::arg(), py::arg());
CppDetectorApi.def("hasRegisterDefinition",
(bool (Detector::*)(const std::string &) const) &
Detector::hasRegisterDefinition,
py::arg());
CppDetectorApi.def("hasRegisterDefinition",
(bool (Detector::*)(sls::RegisterAddress) const) &
Detector::hasRegisterDefinition,
py::arg());
CppDetectorApi.def(
"getRegisterDefinitionAddress",
(sls::RegisterAddress(Detector::*)(const std::string &) const) &
Detector::getRegisterDefinitionAddress,
py::arg());
CppDetectorApi.def("getRegisterDefinitionName",
(std::string(Detector::*)(sls::RegisterAddress) const) &
Detector::getRegisterDefinitionName,
py::arg());
CppDetectorApi.def("clearRegisterDefinitions",
(void (Detector::*)()) &
Detector::clearRegisterDefinitions);
CppDetectorApi.def(
"setRegisterDefinitions",
(void (Detector::*)(const std::map<std::string, RegisterAddress> &)) &
Detector::setRegisterDefinitions,
py::arg());
CppDetectorApi.def(
"getRegisterDefinitions",
(std::map<std::string, RegisterAddress>(Detector::*)() const) &
Detector::getRegisterDefinitions);
CppDetectorApi.def("getBitDefinitionsCount",
(int (Detector::*)() const) &
Detector::getBitDefinitionsCount);
CppDetectorApi.def(
"setBitDefinition",
(void (Detector::*)(const std::string &, sls::BitAddress)) &
Detector::setBitDefinition,
py::arg(), py::arg());
CppDetectorApi.def("hasBitDefinition",
(bool (Detector::*)(const std::string &) const) &
Detector::hasBitDefinition,
py::arg());
CppDetectorApi.def("hasBitDefinition",
(bool (Detector::*)(sls::BitAddress) const) &
Detector::hasBitDefinition,
py::arg());
CppDetectorApi.def(
"getBitDefinitionAddress",
(sls::BitAddress(Detector::*)(const std::string &) const) &
Detector::getBitDefinitionAddress,
py::arg());
CppDetectorApi.def("getBitDefinitionName",
(std::string(Detector::*)(sls::BitAddress) const) &
Detector::getBitDefinitionName,
py::arg());
CppDetectorApi.def("clearBitDefinitions",
(void (Detector::*)()) & Detector::clearBitDefinitions);
CppDetectorApi.def(
"setBitDefinitions",
(void (Detector::*)(const std::map<std::string, BitAddress> &)) &
Detector::setBitDefinitions,
py::arg());
CppDetectorApi.def("getBitDefinitions", (std::map<std::string, BitAddress>(
Detector::*)() const) &
Detector::getBitDefinitions);
CppDetectorApi.def("configureTransceiver",
(void (Detector::*)(sls::Positions)) &
Detector::configureTransceiver,
@@ -2044,58 +1969,6 @@ void init_det(py::module &m) {
(void (Detector::*)(const bool, sls::Positions)) &
Detector::setUpdateMode,
py::arg(), py::arg() = Positions{});
CppDetectorApi.def("readRegister",
(Result<sls::RegisterValue>(Detector::*)(
sls::RegisterAddress, sls::Positions) const) &
Detector::readRegister,
py::arg(), py::arg() = Positions{});
CppDetectorApi.def(
"writeRegister",
(void (Detector::*)(sls::RegisterAddress, sls::RegisterValue, bool,
sls::Positions)) &
Detector::writeRegister,
py::arg(), py::arg(), py::arg() = false, py::arg() = Positions{});
CppDetectorApi.def(
"setBit",
(void (Detector::*)(sls::BitAddress, bool, sls::Positions)) &
Detector::setBit,
py::arg(), py::arg() = false, py::arg() = Positions{});
CppDetectorApi.def(
"clearBit",
(void (Detector::*)(sls::BitAddress, bool, sls::Positions)) &
Detector::clearBit,
py::arg(), py::arg() = false, py::arg() = Positions{});
CppDetectorApi.def(
"getBit",
(Result<int>(Detector::*)(sls::BitAddress, sls::Positions) const) &
Detector::getBit,
py::arg(), py::arg() = Positions{});
CppDetectorApi.def("readRegister",
(Result<sls::RegisterValue>(Detector::*)(
const std::string &, sls::Positions) const) &
Detector::readRegister,
py::arg(), py::arg() = Positions{});
CppDetectorApi.def(
"writeRegister",
(void (Detector::*)(const std::string &, sls::RegisterValue, bool,
sls::Positions)) &
Detector::writeRegister,
py::arg(), py::arg(), py::arg() = false, py::arg() = Positions{});
CppDetectorApi.def(
"setBit",
(void (Detector::*)(const std::string &, bool, sls::Positions)) &
Detector::setBit,
py::arg(), py::arg() = false, py::arg() = Positions{});
CppDetectorApi.def(
"clearBit",
(void (Detector::*)(const std::string &, bool, sls::Positions)) &
Detector::clearBit,
py::arg(), py::arg() = false, py::arg() = Positions{});
CppDetectorApi.def(
"getBit",
(Result<int>(Detector::*)(const std::string &, sls::Positions) const) &
Detector::getBit,
py::arg(), py::arg() = Positions{});
CppDetectorApi.def(
"readRegister",
(Result<uint32_t>(Detector::*)(uint32_t, sls::Positions) const) &
@@ -2118,7 +1991,7 @@ void init_det(py::module &m) {
py::arg(), py::arg(), py::arg() = false, py::arg() = Positions{});
CppDetectorApi.def(
"getBit",
(Result<int>(Detector::*)(uint32_t, int, sls::Positions) const) &
(Result<int>(Detector::*)(uint32_t, int, sls::Positions)) &
Detector::getBit,
py::arg(), py::arg(), py::arg() = Positions{});
CppDetectorApi.def("executeFirmwareTest",

View File

@@ -7,19 +7,15 @@
#include "sls/network_utils.h"
#include "sls/sls_detector_defs.h"
#include "sls/TimeHelper.h"
#include "sls/bit_utils.h"
#include <array>
#include <chrono>
namespace py = pybind11;
void init_det(py::module &m) {
using sls::BitAddress;
using sls::defs;
using sls::Detector;
using sls::ns;
using sls::Positions;
using sls::RegisterAddress;
using sls::RegisterValue;
using sls::Result;
m.def("freeSharedMemory", (void (*)(const int, const int)) &sls::freeSharedMemory, py::arg() = 0, py::arg() = -1);

View File

@@ -20,7 +20,6 @@ void init_scan(py::module &);
void init_source(py::module &);
void init_duration(py::module &);
void init_pedestal(py::module &);
void init_bit(py::module &);
PYBIND11_MODULE(_slsdet, m) {
m.doc() = R"pbdoc(
@@ -41,7 +40,6 @@ PYBIND11_MODULE(_slsdet, m) {
init_source(m);
init_duration(m);
init_pedestal(m);
init_bit(m);
// init_experimental(m);
py::module io = m.def_submodule("io", "Submodule for io");

View File

@@ -8,7 +8,7 @@ Testing functions from utils.py
import pytest
from slsdet.utils import *
from slsdet import IpAddr, MacAddr, DurationWrapper, RegisterAddress, RegisterValue, BitAddress
from slsdet import IpAddr, MacAddr, DurationWrapper
import datetime as dt
import pathlib
from pathlib import Path
@@ -199,7 +199,6 @@ def test_make_mac_from_tuple():
MacAddr("84:a9:3e:24:32:aa"))
def test_make_path_from_str():
assert make_path("/") == Path("/")
assert make_path("/home") == Path("/home")

View File

@@ -3,21 +3,15 @@
add_executable(using_logger using_logger.cpp)
target_link_libraries(using_logger
slsSupportShared
pthread
rt
)
set_target_properties(using_logger PROPERTIES
RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin
)
add_executable(using_registers using_registers.cpp)
target_link_libraries(using_registers
slsDetectorShared
)
set_target_properties(using_registers PROPERTIES
RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin
)
# add_executable(result useResult.cpp)
# target_link_libraries(result
# slsDetectorShared

View File

@@ -3,23 +3,15 @@
#include "sls/logger.h"
#include <iostream>
#include <chrono>
using sls::logINFO;
using sls::logINFORED;
using sls::logINFOBLUE;
using sls::logINFOGREEN;
using sls::logERROR;
using sls::logWARNING;
int main() {
//compare old and new
std::cout << "Compare output between old and new:\n";
LOG(logINFO) << "Some info message";
LOG(logERROR) << "This is an error";
LOG(logWARNING) << "While this is only a warning";
LOG(logWARNING) << "While this is only a warning"; prefix="/afs/psi.ch/project/sls_det_software/dhanya_softwareDevelopment/mySoft/slsDetectorPackage/"
p=${file#"$prefix"}
//Logging level can be configure at runtime
std::cout << "\n\n";
std::cout << "The default macro controlled level is: "

View File

@@ -1,49 +0,0 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
/* This example assumes that you have a ctb configured or using the virtual ctb detector server*/
#include "sls/Detector.h"
#include "sls/bit_utils.h"
#include <iostream>
void somefunc(uint32_t addr){
std::cout << "somefunc called with: " << addr << std::endl;
}
int main(){
// Config file has the following defines
// define addr somereg 0x5
// define bit mybit somereg 7
sls::Detector d;
auto somereg = d.getRegisterDefinition("somereg");
d.writeRegister(somereg, sls::RegisterValue(0));
auto val = d.readRegister(somereg);
std::cout << "somereg has the address: " << somereg << " and value " << val.squash() << std::endl;
auto mybit = d.getBitDefinition("mybit");
std::cout << "mybit refers to register: " << mybit.address() << " bit nr: " << mybit.bitPosition() << std::endl;
d.setBit(mybit);
val = d.readRegister(somereg);
std::cout << "somereg has the address: " << somereg << " and value " << val.squash() << std::endl;
std::cout << "mybit: " << d.getBit(mybit) << std::endl;
//Let's define a bit
sls::BitAddress newbit(sls::RegisterAddress(0x6), 4);
d.setBitDefinition("newbit", newbit);
//This can now be usef from command line "g getbit newbit"
uint32_t addr = somereg; //I'm not sure this should compile
somefunc(somereg); //This should also not compile
}

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@@ -76,8 +76,11 @@ foreach(exe ${JUNGFRAU_EXECUTABLES})
target_link_libraries(${exe}
PUBLIC
slsSupportStatic
pthread
tiffio
fmt::fmt
#-L/usr/lib64/
#-lm -lstdc++ -lrt
PRIVATE
slsProjectWarnings

View File

@@ -69,6 +69,7 @@ foreach(exe ${MOENCH_EXECUTABLES})
PUBLIC
slsSupportStatic
${ZeroMQ_LIBRARIES}
pthread
tiffio
PRIVATE

View File

@@ -37,9 +37,7 @@ target_compile_definitions(ctbDetectorServer_virtual
)
target_link_libraries(ctbDetectorServer_virtual
PUBLIC
m
slsProjectCSettings
PUBLIC pthread rt m slsProjectCSettings
)
set_target_properties(ctbDetectorServer_virtual PROPERTIES

View File

@@ -5,7 +5,6 @@
/* Definitions for FPGA */
#define MEM_MAP_SHIFT 1
#define REG_OFFSET (2)
/* FPGA Version RO register */
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
@@ -66,8 +65,8 @@
(0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x677FF)
/* Register containing the git hash of the FPGA firmware */
#define FIRMWARE_GIT_HASH_REG (0x03 << MEM_MAP_SHIFT)
/* Look at me RO register TODO */
#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT)
/* System Status RO register */
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
@@ -120,7 +119,7 @@
#define MOD_SERIAL_NUMBER_VRSN_MSK (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
/* API Version RO register */
#define API_VERSION_REG (0x0B << MEM_MAP_SHIFT)
#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
@@ -129,24 +128,24 @@
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
* CONTROL_CRST. TODO */
#define TIME_FROM_START_LSB_REG (0x97 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x98 << MEM_MAP_SHIFT)
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
/* Delay Left 64 bit RO register. t = DLY x 50 ns. TODO */
#define DELAY_LEFT_LSB_REG (0x8D << MEM_MAP_SHIFT)
#define DELAY_LEFT_MSB_REG (0x8E << MEM_MAP_SHIFT)
#define DELAY_LEFT_LSB_REG (0x12 << MEM_MAP_SHIFT)
#define DELAY_LEFT_MSB_REG (0x13 << MEM_MAP_SHIFT)
/* Triggers Left 64 bit RO register TODO */
#define CYCLES_LEFT_LSB_REG (0x8F << MEM_MAP_SHIFT)
#define CYCLES_LEFT_MSB_REG (0x90 << MEM_MAP_SHIFT)
#define CYCLES_LEFT_LSB_REG (0x14 << MEM_MAP_SHIFT)
#define CYCLES_LEFT_MSB_REG (0x15 << MEM_MAP_SHIFT)
/* Frames Left 64 bit RO register TODO */
#define FRAMES_LEFT_LSB_REG (0x91 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_MSB_REG (0x92 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_LSB_REG (0x16 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_MSB_REG (0x17 << MEM_MAP_SHIFT)
/* Period Left 64 bit RO register. t = T x 50 ns. TODO */
#define PERIOD_LEFT_LSB_REG (0x93 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_MSB_REG (0x94 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_LSB_REG (0x18 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
/* Exposure Time Left 64 bit RO register */
// #define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not
@@ -161,34 +160,34 @@
//// Not used in FW
/* Data In 64 bit RO register TODO */
#define DATA_IN_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define DATA_IN_MSB_REG (0x11 << MEM_MAP_SHIFT)
#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
#define DATA_IN_MSB_REG (0x1F << MEM_MAP_SHIFT)
/* Pattern Out 64 bit RO register */
#define PATTERN_OUT_LSB_REG (0x80 << MEM_MAP_SHIFT)
#define PATTERN_OUT_MSB_REG (0x81 << MEM_MAP_SHIFT)
#define PATTERN_OUT_LSB_REG (0x20 << MEM_MAP_SHIFT)
#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
/* Frame number of next acquisition register (64 bit register) */
#define NEXT_FRAME_NUMB_LOCAL_LSB_REG (0x12 << MEM_MAP_SHIFT)
#define NEXT_FRAME_NUMB_LOCAL_MSB_REG (0x13 << MEM_MAP_SHIFT)
#define NEXT_FRAME_NUMB_LOCAL_LSB_REG (0x22 << MEM_MAP_SHIFT)
#define NEXT_FRAME_NUMB_LOCAL_MSB_REG (0x23 << MEM_MAP_SHIFT)
/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
#define FRAMES_FROM_START_PG_LSB_REG (0x99 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x9A << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
* start until reset) TODO */
#define START_FRAME_TIME_LSB_REG (0x9B << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x9C << MEM_MAP_SHIFT)
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
/* Power Status RO register */
#define POWER_STATUS_REG (0x18 << MEM_MAP_SHIFT)
#define POWER_STATUS_REG (0x29 << MEM_MAP_SHIFT)
#define POWER_STATUS_ALRT_OFST (27)
#define POWER_STATUS_ALRT_MSK (0x0000001F << POWER_STATUS_ALRT_OFST)
/* FIFO Transceiver In Status RO register */
#define FIFO_TIN_STATUS_REG (0x1A << MEM_MAP_SHIFT)
#define FIFO_TIN_STATUS_REG (0x30 << MEM_MAP_SHIFT)
#define FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST (4)
#define FIFO_TIN_STATUS_FIFO_EMPTY_1_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST)
#define FIFO_TIN_STATUS_FIFO_EMPTY_2_OFST (5)
@@ -199,54 +198,23 @@
#define FIFO_TIN_STATUS_FIFO_EMPTY_4_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_4_OFST)
#define FIFO_TIN_STATUS_FIFO_EMPTY_ALL_MSK (0x0000000F << FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST)
/* FIFO Transceiver Fill level RO register */
#define FIFO_TIN_FILL_REG (0x25 << MEM_MAP_SHIFT)
#define FIFO_TIN_FILL_FIFO_1_OFST (0)
#define FIFO_TIN_FILL_FIFO_1_MSK (0x00003FFF << FIFO_TIN_FILL_FIFO__1_OFST)
#define FIFO_TIN_FILL_FIFO_2_OFST (16)
#define FIFO_TIN_FILL_FIFO_2_MSK (0x00003FFF << FIFO_TIN_FILL_FIFO__2_OFST)
/* FIFO ADC Fill level RO register */
#define FIFO_ADC_FILL_REG (0x26 << MEM_MAP_SHIFT)
#define FIFO_ADC_FILL_FIFO_OFST (0)
#define FIFO_ADC_FILL_FIFO_MSK (0x00003FFF << FIFO_ADC_FILL_FIFO_OFST)
/* Enable continuos readout register */
#define CONTINUOUS_RO_ENABLE_REG (0x27 << MEM_MAP_SHIFT)
#define CONTINUOUS_RO_ADC_ENABLE_OFST (0)
#define CONTINUOUS_RO_TIN_ENABLE_OFST (1)
#define CONTINUOUS_RO_DBIT_ENABLE_OFST (2)
#define CONTINUOUS_RO_ADC_ENABLE_MSK (0x00000001 << CONTINUOUS_RO_ADC_ENABLE_OFST)
#define CONTINUOUS_RO_TIN_ENABLE_MSK (0x00000001 << CONTINUOUS_RO_TIN_ENABLE_OFST)
#define CONTINUOUS_RO_DBIT_ENABLE_MSK (0x00000001 << CONTINUOUS_RO_DBIT_ENABLE_OFST)
#define DBIT_INJECT_COUNTER_ENA_OFST (3) // continuously injects fake-data into the dbit fifo when enabled.
#define DBIT_INJECT_COUNTER_ENA_MSK (0x00000001 << DBIT_INJECT_COUNTER_ENA_OFST)
#define DBIT_INJECT_COUNTER_CLKDIV_OFST (8) // Additional clock divider for fake-data injection
#define DBIT_INJECT_COUNTER_CLKDIV_MSK (0x000000FF << DBIT_INJECT_COUNTER_CLKDIV_OFST)
/* 64-bit FPGA chip ID. Unique for every device. read-only */
#define FPGA_chipID_0_REG (0x28 << MEM_MAP_SHIFT)
#define FPGA_chipID_1_REG (0x29 << MEM_MAP_SHIFT)
/* FIFO Transceiver In 64 bit RO register */
#define FIFO_TIN_LSB_REG (0x1B << MEM_MAP_SHIFT)
#define FIFO_TIN_MSB_REG (0x1C << MEM_MAP_SHIFT)
#define FIFO_TIN_LSB_REG (0x31 << MEM_MAP_SHIFT)
#define FIFO_TIN_MSB_REG (0x32 << MEM_MAP_SHIFT)
/* FIFO Digital In Status RO register */
#define FIFO_DIN_STATUS_REG (0x1D << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FILL_OFST (0)
#define FIFO_DIN_STATUS_FIFO_FILL_MSK (0x00003FFF)
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
/* FIFO Digital In 64 bit RO register */
#define FIFO_DIN_LSB_REG (0x1E << MEM_MAP_SHIFT)
#define FIFO_DIN_MSB_REG (0x1F << MEM_MAP_SHIFT)
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
#define FIFO_DIN_MSB_REG (0x3D << MEM_MAP_SHIFT)
/* SPI (Serial Peripheral Interface) DAC, HV RW register */
#define SPI_REG (0x20 << MEM_MAP_SHIFT)
#define SPI_REG (0x40 << MEM_MAP_SHIFT)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
@@ -262,7 +230,7 @@
#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
/* ADC SPI (Serial Peripheral Interface) RW register */
#define ADC_SPI_REG (0x21 << MEM_MAP_SHIFT)
#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
@@ -272,7 +240,7 @@
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
/* ADC Offset RW register */
#define ADC_OFFSET_REG (0x22 << MEM_MAP_SHIFT)
#define ADC_OFFSET_REG (0x42 << MEM_MAP_SHIFT)
#define ADC_OFFSET_ADC_PPLN_OFST (0)
#define ADC_OFFSET_ADC_PPLN_MSK (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
@@ -280,7 +248,7 @@
#define ADC_OFFSET_DBT_PPLN_MSK (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
/* ADC Port Invert RW register */
#define ADC_PORT_INVERT_REG (0x23 << MEM_MAP_SHIFT)
#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
#define ADC_PORT_INVERT_0_INPT_OFST (0)
#define ADC_PORT_INVERT_0_INPT_MSK (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
@@ -292,7 +260,7 @@
#define ADC_PORT_INVERT_3_INPT_MSK (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
/* Dummy RW register */
#define DUMMY_REG (0x24 << MEM_MAP_SHIFT)
#define DUMMY_REG (0x44 << MEM_MAP_SHIFT)
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
@@ -305,8 +273,46 @@
#define DUMMY_TRNSCVR_FIFO_RD_STRBE_OFST (14)
#define DUMMY_TRNSCVR_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_TRNSCVR_FIFO_RD_STRBE_OFST)
/* Receiver IP Address RW register */
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
/* UDP Port RW register */
#define UDP_PORT_REG (0x46 << MEM_MAP_SHIFT)
#define UDP_PORT_RX_OFST (0)
#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
#define UDP_PORT_TX_OFST (16)
#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
/* Receiver Mac Address 64 bit RW register */
#define RX_MAC_LSB_REG (0x47 << MEM_MAP_SHIFT)
#define RX_MAC_MSB_REG (0x48 << MEM_MAP_SHIFT)
#define RX_MAC_LSB_OFST (0)
#define RX_MAC_LSB_MSK (0xFFFFFFFF << RX_MAC_LSB_OFST)
#define RX_MAC_MSB_OFST (0)
#define RX_MAC_MSB_MSK (0x0000FFFF << RX_MAC_MSB_OFST)
/* Detector/ Transmitter Mac Address 64 bit RW register */
#define TX_MAC_LSB_REG (0x49 << MEM_MAP_SHIFT)
#define TX_MAC_MSB_REG (0x4A << MEM_MAP_SHIFT)
#define TX_MAC_LSB_OFST (0)
#define TX_MAC_LSB_MSK (0xFFFFFFFF << TX_MAC_LSB_OFST)
#define TX_MAC_MSB_OFST (0)
#define TX_MAC_MSB_MSK (0x0000FFFF << TX_MAC_MSB_OFST)
/* Detector/ Transmitter IP Address RW register */
#define TX_IP_REG (0x4B << MEM_MAP_SHIFT)
/* Detector/ Transmitter IP Checksum RW register */
#define TX_IP_CHECKSUM_REG (0x4C << MEM_MAP_SHIFT)
#define TX_IP_CHECKSUM_OFST (0)
#define TX_IP_CHECKSUM_MSK (0x0000FFFF << TX_IP_CHECKSUM_OFST)
/* Configuration RW register */
#define CONFIG_REG (0x2D << MEM_MAP_SHIFT)
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
#define CONFIG_LED_DSBL_OFST (0)
#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
@@ -321,7 +327,7 @@
#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
/* External Signal RW register */
#define EXT_SIGNAL_REG (0x2E << MEM_MAP_SHIFT)
#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
@@ -329,7 +335,7 @@
#define EXT_SIGNAL_TRGGR_VAL ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/* Control RW register */
#define CONTROL_REG (0x2F << MEM_MAP_SHIFT)
#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
@@ -369,10 +375,10 @@
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
/* Reconfiguratble PLL Paramater RW register */
#define PLL_PARAM_REG (0x30 << MEM_MAP_SHIFT)
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
/* Reconfiguratble PLL Control RW regiser */
#define PLL_CNTRL_REG (0x31 << MEM_MAP_SHIFT)
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
@@ -384,15 +390,8 @@
#define PLL_CNTRL_ADDR_OFST (16)
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
/* Streaming Control RW regiser */
#define STREAMING_CTRL_REG (0x3D << MEM_MAP_SHIFT)
#define STREAMING_CTRL_ENA_OFST (15)
#define STREAMING_CTRL_ENA_MSK (0x00000001 << STREAMING_CTRL_ENA_OFST)
#define STREAMING_CTRL_SELECT_OFST (0)
#define STREAMING_CTRL_SELECT_MSK (0x0000003F << STREAMING_CTRL_SELECT_OFST)
/* Pattern Control RW register */
#define PATTERN_CNTRL_REG (0x88 << MEM_MAP_SHIFT)
#define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)
#define PATTERN_CNTRL_WR_OFST (0)
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
@@ -402,31 +401,70 @@
#define PATTERN_CNTRL_ADDR_MSK (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
/* Pattern Limit RW regiser */
#define PATTERN_LIMIT_REG (0x89 << MEM_MAP_SHIFT)
#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
/** Pattern Loop and Wait Definitions, 5 regs each */
#define PATTERN_LOOPDEF_BASE (0xA0 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_ADDR_WORD_OFST (0)
#define PATTERN_LOOP_ITERATION_WORD_OFST (1)
#define PATTERN_WAIT_ADDR_WORD_OFST (2)
#define PATTERN_WAIT_TIMER_LSB_WORD_OFST (3)
#define PATTERN_WAIT_TIMER_MSB_WORD_OFST (4)
#define PATTERN_LOOPDEF_NWORDS_OFST (5)
/* Pattern Loop 0 Address RW regiser */
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_ADDR_OFST (0)
#define PATTERN_WAIT_ADDR_MSK (0x00001FFF << PATTERN_WAIT_ADDR_OFST)
#define PATTERN_LOOP_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_ADDR_STRT_OFST)
#define PATTERN_LOOP_ADDR_STP_OFST (16)
#define PATTERN_LOOP_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_ADDR_STP_OFST)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
/* Pattern Loop 0 Iteration RW regiser */
#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
/* Pattern Loop 1 Address RW regiser */
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
/* Pattern Loop 1 Iteration RW regiser */
#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
/* Pattern Loop 2 Address RW regiser */
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
/* Pattern Loop 2 Iteration RW regiser */
#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
/* Pattern Wait 0 RW regiser */
#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
// FIXME: is mask 3FF
/* Pattern Wait 1 RW regiser */
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
/* Pattern Wait 2 RW regiser */
#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
/* Samples RW register */
#define SAMPLES_REG (0x32 << MEM_MAP_SHIFT)
#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
#define SAMPLES_DIGITAL_OFST (0)
#define SAMPLES_DIGITAL_MSK (0x0000FFFF << SAMPLES_DIGITAL_OFST)
@@ -434,7 +472,7 @@
#define SAMPLES_ANALOG_MSK (0x0000FFFF << SAMPLES_ANALOG_OFST)
/** Power RW register */
#define POWER_REG (0x33 << MEM_MAP_SHIFT)
#define POWER_REG (0x5E << MEM_MAP_SHIFT)
#define POWER_ENBL_VLTG_RGLTR_OFST (16)
#define POWER_ENBL_VLTG_RGLTR_MSK (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
@@ -442,25 +480,25 @@
#define POWER_HV_INTERNAL_SLCT_MSK (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
/* Number of samples from transceiver RW register */
#define SAMPLES_TRANSCEIVER_REG (0x34 << MEM_MAP_SHIFT)
#define SAMPLES_TRANSCEIVER_REG (0x5F << MEM_MAP_SHIFT)
#define SAMPLES_TRANSCEIVER_OFST (0)
#define SAMPLES_TRANSCEIVER_MSK (0x0000FFFF << SAMPLES_TRANSCEIVER_OFST)
/* Delay 64 bit RW register. t = DLY x 50 ns. */
#define DELAY_LSB_REG (0x8D << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x8E << MEM_MAP_SHIFT)
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
/* Triggers 64 bit RW register */
#define CYCLES_LSB_REG (0x8F << MEM_MAP_SHIFT)
#define CYCLES_MSB_REG (0x90 << MEM_MAP_SHIFT)
#define CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
#define CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
/* Frames 64 bit RW register */
#define FRAMES_LSB_REG (0x91 << MEM_MAP_SHIFT)
#define FRAMES_MSB_REG (0x92 << MEM_MAP_SHIFT)
#define FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
#define FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
#define PERIOD_LSB_REG (0x93 << MEM_MAP_SHIFT)
#define PERIOD_MSB_REG (0x94 << MEM_MAP_SHIFT)
#define PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
// #define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) //
@@ -475,15 +513,33 @@
/* Pattern IO Control 64 bit RW regiser
* Each bit configured as output(1)/ input(0) */
#define PATTERN_IO_CNTRL_LSB_REG (0x8A << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_MSB_REG (0x8B << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_LSB_REG (0x6C << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_MSB_REG (0x6D << MEM_MAP_SHIFT)
/* Pattern IO Clock Control 64 bit RW regiser
* When bit n enabled (1), clocked output for DIO[n] (T run clock)
* When bit n disabled (0), Dio[n] driven by its pattern output */
#define PATTERN_IO_CLK_CNTRL_LSB_REG (0x6E << MEM_MAP_SHIFT)
#define PATTERN_IO_CLK_CNTRL_MSB_REG (0x6F << MEM_MAP_SHIFT)
/* Pattern In 64 bit RW register */
#define PATTERN_IN_LSB_REG (0x82 << MEM_MAP_SHIFT)
#define PATTERN_IN_MSB_REG (0x83 << MEM_MAP_SHIFT)
#define PATTERN_IN_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define PATTERN_IN_MSB_REG (0x71 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 0 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x72 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x73 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 1 64 bit RW register. t = PWT2 x T run clock */
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x74 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x75 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 2 64 bit RW register. t = PWT3 x T run clock */
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
/* Readout enable RW register */
#define READOUT_10G_ENABLE_REG (0x3C << MEM_MAP_SHIFT)
#define READOUT_10G_ENABLE_REG (0x79 << MEM_MAP_SHIFT)
#define READOUT_10G_ENABLE_ANLG_OFST (0)
#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
@@ -494,7 +550,7 @@
(0x0000000F << READOUT_10G_ENABLE_TRNSCVR_OFST)
/* Digital Bit External Trigger RW register */
#define DBIT_EXT_TRG_REG (0x3E << MEM_MAP_SHIFT)
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
#define DBIT_EXT_TRG_SRC_OFST (0)
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
@@ -502,7 +558,7 @@
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
/* Pin Delay 0 RW register */
#define OUTPUT_DELAY_0_REG (0x3F << MEM_MAP_SHIFT)
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT)
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST \
(0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
@@ -518,21 +574,87 @@
/* Pin Delay 1 RW register
* Each bit configured as enable for dynamic output delay configuration */
#define PIN_DELAY_1_REG (0x40 << MEM_MAP_SHIFT)
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT)
/** Pattern Mask 64 bit RW regiser */
#define PATTERN_MASK_LSB_REG (0x84 << MEM_MAP_SHIFT)
#define PATTERN_MASK_MSB_REG (0x85 << MEM_MAP_SHIFT)
#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
#define PATTERN_MASK_MSB_REG (0x81 << MEM_MAP_SHIFT)
/** Pattern Set 64 bit RW regiser */
#define PATTERN_SET_LSB_REG (0x86 << MEM_MAP_SHIFT)
#define PATTERN_SET_MSB_REG (0x87 << MEM_MAP_SHIFT)
#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
/* Pattern Loop 3 Address RW regiser */
#define PATTERN_LOOP_3_ADDR_REG (0x84 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_3_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_3_ADDR_STRT_OFST)
#define PATTERN_LOOP_3_ADDR_STP_OFST (16)
#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_3_ADDR_STP_OFST)
/* Pattern Loop 3 Iteration RW regiser */
#define PATTERN_LOOP_3_ITERATION_REG (0x85 << MEM_MAP_SHIFT)
/* Pattern Loop 4 Address RW regiser */
#define PATTERN_LOOP_4_ADDR_REG (0x86 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_4_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_4_ADDR_STRT_OFST)
#define PATTERN_LOOP_4_ADDR_STP_OFST (16)
#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_4_ADDR_STP_OFST)
/* Pattern Loop 4 Iteration RW regiser */
#define PATTERN_LOOP_4_ITERATION_REG (0x87 << MEM_MAP_SHIFT)
/* Pattern Loop 5 Address RW regiser */
#define PATTERN_LOOP_5_ADDR_REG (0x88 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_5_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_5_ADDR_STRT_OFST)
#define PATTERN_LOOP_5_ADDR_STP_OFST (16)
#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_5_ADDR_STP_OFST)
/* Pattern Loop 5 Iteration RW regiser */
#define PATTERN_LOOP_5_ITERATION_REG (0x89 << MEM_MAP_SHIFT)
/* Pattern Wait 3 RW regiser */
#define PATTERN_WAIT_3_ADDR_REG (0x8A << MEM_MAP_SHIFT)
#define PATTERN_WAIT_3_ADDR_OFST (0)
#define PATTERN_WAIT_3_ADDR_MSK (0x00001FFF << PATTERN_WAIT_3_ADDR_OFST)
/* Pattern Wait 4 RW regiser */
#define PATTERN_WAIT_4_ADDR_REG (0x8B << MEM_MAP_SHIFT)
#define PATTERN_WAIT_4_ADDR_OFST (0)
#define PATTERN_WAIT_4_ADDR_MSK (0x00001FFF << PATTERN_WAIT_4_ADDR_OFST)
/* Pattern Wait 5 RW regiser */
#define PATTERN_WAIT_5_ADDR_REG (0x8C << MEM_MAP_SHIFT)
#define PATTERN_WAIT_5_ADDR_OFST (0)
#define PATTERN_WAIT_5_ADDR_MSK (0x00001FFF << PATTERN_WAIT_5_ADDR_OFST)
/* Pattern Wait Timer 3 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_3_LSB_REG (0x8D << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_3_MSB_REG (0x8E << MEM_MAP_SHIFT)
/* Pattern Wait Timer 4 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_4_LSB_REG (0x8F << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_4_MSB_REG (0x90 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 5 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_5_LSB_REG (0x91 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_5_MSB_REG (0x92 << MEM_MAP_SHIFT)
/* Slow ADC SPI Value RO register */
#define ADC_SLOW_DATA_REG (0x41 << MEM_MAP_SHIFT)
#define ADC_SLOW_DATA_REG (0x93 << MEM_MAP_SHIFT)
/* Slow ADC SPI Value Config register */
#define ADC_SLOW_CFG_REG (0x42 << MEM_MAP_SHIFT)
#define ADC_SLOW_CFG_REG (0x94 << MEM_MAP_SHIFT)
/** Read back CFG Register */
#define ADC_SLOW_CFG_RB_OFST (2)
#define ADC_SLOW_CFG_RB_MSK (0x00000001 << ADC_SLOW_CFG_RB_OFST)
@@ -611,7 +733,7 @@
((0x1 << ADC_SLOW_CFG_CFG_OFST) & ADC_SLOW_CFG_CFG_MSK)
/* Slow ADC SPI Value Control register */
#define ADC_SLOW_CTRL_REG (0x43 << MEM_MAP_SHIFT)
#define ADC_SLOW_CTRL_REG (0x95 << MEM_MAP_SHIFT)
#define ADC_SLOW_CTRL_STRT_OFST (0)
#define ADC_SLOW_CTRL_STRT_MSK (0x00000001 << ADC_SLOW_CTRL_STRT_OFST)

View File

@@ -54,7 +54,6 @@
#define DEFAULT_ADC_CLK (40) // 20
#define DEFAULT_SYNC_CLK (40) // 20
#define DEFAULT_DBIT_CLK (200)
#define NS_TO_CLK_CYCLE (1E-3) // ns to MHz
#define DEFAULT_TRANSCEIVER_MASK (0x3)
#define MAX_TRANSCEIVER_MASK (0xF)

View File

@@ -30,8 +30,7 @@ target_compile_definitions(eigerDetectorServer_virtual
)
target_link_libraries(eigerDetectorServer_virtual
PUBLIC
slsProjectCSettings
PUBLIC pthread rt slsProjectCSettings
)
set_target_properties(eigerDetectorServer_virtual PROPERTIES

View File

@@ -31,8 +31,7 @@ target_compile_definitions(gotthard2DetectorServer_virtual
)
target_link_libraries(gotthard2DetectorServer_virtual
PUBLIC
slsProjectCSettings
PUBLIC pthread rt slsProjectCSettings
)
set_target_properties(gotthard2DetectorServer_virtual PROPERTIES

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@@ -29,8 +29,7 @@ target_compile_definitions(jungfrauDetectorServer_virtual
)
target_link_libraries(jungfrauDetectorServer_virtual
PUBLIC
slsProjectCSettings
PUBLIC pthread rt slsProjectCSettings
)
set_target_properties(jungfrauDetectorServer_virtual PROPERTIES

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@@ -29,8 +29,7 @@ target_compile_definitions(moenchDetectorServer_virtual
)
target_link_libraries(moenchDetectorServer_virtual
PUBLIC
slsProjectCSettings
PUBLIC pthread rt slsProjectCSettings
)
set_target_properties(moenchDetectorServer_virtual PROPERTIES

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@@ -33,8 +33,7 @@ target_compile_definitions(mythen3DetectorServer_virtual
)
target_link_libraries(mythen3DetectorServer_virtual
PUBLIC
slsProjectCSettings
PUBLIC pthread rt slsProjectCSettings
)
set_target_properties(mythen3DetectorServer_virtual PROPERTIES

View File

@@ -348,21 +348,68 @@
#define PATTERN_SET_LSB_REG (0x44 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_SET_MSB_REG (0x45 * REG_OFFSET + BASE_PATTERN_CONTROL)
/** Pattern Loop and Wait Definitions, 5 regs each */
#define PATTERN_LOOPDEF_BASE (0x60 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOPDEF_NWORDS_OFST (5)
#define PATTERN_WAIT_TIMER_LSB_WORD_OFST (0)
#define PATTERN_WAIT_TIMER_MSB_WORD_OFST (1)
#define PATTERN_WAIT_ADDR_WORD_OFST (2)
#define PATTERN_LOOP_ITERATION_WORD_OFST (3)
#define PATTERN_LOOP_ADDR_WORD_OFST (4)
/* Pattern Wait Timer 0 64bit RW Register */
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x60 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x61 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_ADDR_OFST (0)
#define PATTERN_WAIT_ADDR_MSK (0x00001FFF << PATTERN_WAIT_ADDR_OFST)
#define PATTERN_LOOP_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_ADDR_STRT_OFST)
#define PATTERN_LOOP_ADDR_STP_OFST (16)
#define PATTERN_LOOP_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_ADDR_STP_OFST)
/* Pattern Wait 0 RW Register*/
#define PATTERN_WAIT_0_ADDR_REG (0x62 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
/* Pattern Loop 0 Iteration RW Register */
#define PATTERN_LOOP_0_ITERATION_REG (0x63 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Loop 0 Address RW Register */
#define PATTERN_LOOP_0_ADDR_REG (0x64 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
/* Pattern Wait Timer 1 64bit RW Register */
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x65 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x66 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Wait 1 RW Register*/
#define PATTERN_WAIT_1_ADDR_REG (0x67 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
/* Pattern Loop 1 Iteration RW Register */
#define PATTERN_LOOP_1_ITERATION_REG (0x68 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Loop 1 Address RW Register */
#define PATTERN_LOOP_1_ADDR_REG (0x69 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
/* Pattern Wait Timer 2 64bit RW Register */
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x6A * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x6B * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Wait 2 RW Register*/
#define PATTERN_WAIT_2_ADDR_REG (0x6C * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
/* Pattern Loop 2 Iteration RW Register */
#define PATTERN_LOOP_2_ITERATION_REG (0x6D * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Loop 0 Address RW Register */
#define PATTERN_LOOP_2_ADDR_REG (0x6E * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
/* Pattern RAM registers --------------------------------------------------*/

View File

@@ -63,7 +63,6 @@
#define DEFAULT_SYSTEM_C1 (6) //(166666666) // str_clk, 166 MHz const
#define DEFAULT_SYSTEM_C2 (5) //(200000000) // smp_clk, 200 MHz const
#define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz
#define NS_TO_CLK_CYCLE (1E-3) // ns to MHz
#define FULL_SPEED_CLKDIV (10) //(100000000) 100 MHz
#define HALF_SPEED_CLKDIV (20) //( 50000000) 50 MHz

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@@ -1,12 +0,0 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#include <stdbool.h>
#include <stdint.h>
int XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq);
uint32_t XILINX_PLL_getFrequency(uint32_t clkIDX);
bool XILINX_PLL_isLocked();
void XILINX_PLL_reset();
void XILINX_PLL_waitForLock();
void XILINX_PLL_load();

View File

@@ -6,9 +6,7 @@
#include <sys/types.h>
void bus_w(u_int32_t offset, u_int32_t data);
void bus_w_csp2(u_int32_t offset, u_int32_t data);
u_int32_t bus_r(u_int32_t offset);
u_int32_t bus_r_csp2(u_int32_t offset);
uint64_t getU64BitReg(int aLSB, int aMSB);
void setU64BitReg(uint64_t value, int aLSB, int aMSB);
u_int32_t readRegister(u_int32_t offset);

View File

@@ -58,8 +58,7 @@ uint64_t getPatternMask();
void setPatternBitMask(uint64_t mask);
uint64_t getPatternBitMask();
#if defined(MYTHEN3D) || defined(XILINX_CHIPTESTBOARDD) || \
defined(CHIPTESTBOARDD)
#ifdef MYTHEN3D
void startPattern();
#endif
char *getPatternFileName();

View File

@@ -398,8 +398,8 @@ int getPower();
void setPower(enum DACINDEX ind, int val);
void powerOff();
#elif XILINX_CHIPTESTBOARDD
int getBitOffsetFromDACIndex(enum DACINDEX ind);
int isPowerValid(enum DACINDEX ind, int val);
int getPower();
void setPower(enum DACINDEX ind, int val);
#endif
@@ -518,6 +518,8 @@ int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
int setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
void configureSyncFrequency(enum CLKINDEX ind);
void setADCPipeline(int val);
int getADCPipeline();
@@ -527,11 +529,6 @@ int setLEDEnable(int enable);
void setDigitalIODelay(uint64_t pinMask, int delay);
#endif
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
int setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
#endif
// jungfrau/moench specific - powerchip, autocompdisable, clockdiv, asictimer,
// clock, pll, flashing firmware
#if defined(MOENCHD)

View File

@@ -1,201 +0,0 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#include "XILINX_PLL.h"
#include "arm64.h"
#include "clogger.h"
#include <math.h>
#include <stdbool.h>
#include <unistd.h>
// https://docs.amd.com/r/en-US/pg065-clk-wiz/Register-Space (simplified, we
// leave some things away)
// clang-format off
#define XILINX_PLL_INPUT_FREQ (100000) // 100 MHz
#define XILINX_PLL_MIN_FREQ (10000)
#define XILINX_PLL_MAX_FREQ (250000)
#define XILINX_PLL_MAX_CLK_DIV (256)
#define XILINX_PLL_NUM_CLKS (7)
#define XILINX_PLL_MAX_NUM_CLKS_FOR_GET (3)
#define XILINX_PLL_STEP_SIZE (125)
#define XILINX_PLL_HALF_STEP_SIZE (62)
#define XILINX_PLL_BASE_ADDR (0x0)
#define XILINX_PLL_MEASURE_BASE_ADDR0 (0x1000) // added externally, not part of CLKWIZ core for clks 0 and 1
#define XILINX_PLL_MEASURE_BASE_ADDR0_MAX_CLKS (2)
#define XILINX_PLL_MEASURE_BASE_ADDR1 (0x2000) // for clks 2 to 6
#define XILINX_PLL_MEASURE_WIDTH (8) // per clock
#define XILINX_PLL_RESET_REG (0x000)
#define XILINX_PLL_RESET_VAL (0xA)
#define XILINX_PLL_STATUS_REG (0x004)
#define XILINX_PLL_STATUS_LOCKED_OFST (0)
#define XILINX_PLL_STATUS_LOCKED_MSK (0x00000001 << XILINX_PLL_STATUS_LOCKED_OFST)
#define XILINX_PLL_CLKCONFIG_REG (XILINX_PLL_BASE_ADDR + 0x200)
#define XILINX_PLL_DIVCLK_DIVIDE_OFST (0)
#define XILINX_PLL_DIVCLK_DIVIDE_MSK (0x000000FF << XILINX_PLL_DIVCLK_DIVIDE_OFST)
#define XILINX_PLL_CLKFBOUT_MULT_OFST (8)
#define XILINX_PLL_CLKFBOUT_MULT_MSK (0x000000FF << XILINX_PLL_CLKFBOUT_MULT_OFST)
#define XILINX_PLL_CLKFBOUT_FRAC_OFST (16)
#define XILINX_PLL_CLKFBOUT_FRAC_MSK (0x000003FF << XILINX_PLL_CLKFBOUT_FRAC_OFST)
// The value from 0 to 875 representing the fractional multiplied by 1000
#define XILINX_PLL_CLKFBOUT_FRAC_MAX_VAL (875)
#define XILINX_PLL_CLKCONFIG_BASE_ADDR (XILINX_PLL_BASE_ADDR + 0x208)
#define XILINX_PLL_CLKCONFIG_WIDTH (3 * 4) // per clock (7 clocks)
#define XILINX_PLL_CLK_DIV_REG_OFST (0)
#define XILINX_PLL_CLK_DIV_DIVIDE_OFST (0)
#define XILINX_PLL_CLK_DIV_DIVIDE_MSK (0x000000FF << XILINX_PLL_CLK_DIV_DIVIDE_OFST)
#define XILINX_PLL_CLK_DIV_FRAC_OFST (8) // works on IDX 0 only
#define XILINX_PLL_CLK_DIV_FRAC_MSK (0x000003FF << XILINX_PLL_CLK_DIV_FRAC_OFST)
#define XILINX_PLL_CLK_PHASE_REG_OFST (4) // signed num for +/- phase
#define XILINX_PLL_CLK_PHASE_OFST (0)
#define XILINX_PLL_CLK_PHASE_MSK (0x0000FFFF << XILINX_PLL_CLK_PHASE_OFST)
#define XILINX_PLL_CLK_DUTY_REG_OFST (8) // (in %) * 1000
#define XILINX_PLL_CLK_DUTY_OFST (0)
#define XILINX_PLL_CLK_DUTY_MSK (0x0000FFFF << XILINX_PLL_CLK_DUTY_OFST)
#define XILINX_PLL_LOAD_REG (0x25C)
#define XILINX_PLL_LOAD_RECONFIGURE_OFST (0) // load and reconfigure state machine
#define XILINX_PLL_LOAD_RECONFIGURE_MSK (0x00000001 << XILINX_PLL_LOAD_RECONFIGURE_OFST)
#define XILINX_PLL_LOAD_FROM_REGS_OFST (1) // 0 for default values as compiled into firmware
#define XILINX_PLL_LOAD_FROM_REGS_MSK (0x00000001 << XILINX_PLL_LOAD_FROM_REGS_OFST)
// clang-format on
// freq in kHz !!
int XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
if (clk_index >= XILINX_PLL_NUM_CLKS) {
LOG(logERROR, ("XILINX_PLL: Invalid clock index %d\n", clk_index));
return 1;
}
if (freq < XILINX_PLL_MIN_FREQ || freq > XILINX_PLL_MAX_FREQ) {
LOG(logERROR, ("XILINX_PLL: Frequency %d kHz is out of range\n", freq));
return 1;
}
// calculate base clock frequency
uint32_t global_reg = bus_r_csp2(XILINX_PLL_CLKCONFIG_REG);
#ifdef VIRTUAL
global_reg = 3073;
#endif
uint32_t clkfbout_mult = ((global_reg & XILINX_PLL_CLKFBOUT_MULT_MSK) >>
XILINX_PLL_CLKFBOUT_MULT_OFST);
uint32_t clkfbout_frac = ((global_reg & XILINX_PLL_CLKFBOUT_FRAC_MSK) >>
XILINX_PLL_CLKFBOUT_FRAC_OFST);
uint32_t divclk_divide = ((global_reg & XILINX_PLL_DIVCLK_DIVIDE_MSK) >>
XILINX_PLL_DIVCLK_DIVIDE_OFST);
uint32_t base_clk_freq = clkfbout_mult * XILINX_PLL_INPUT_FREQ;
base_clk_freq += (clkfbout_frac * XILINX_PLL_INPUT_FREQ /
XILINX_PLL_CLKFBOUT_FRAC_MAX_VAL);
base_clk_freq /= divclk_divide;
// calcualte clock divider
uint32_t clk_div = base_clk_freq / freq;
if (clk_div < 1 || clk_div > XILINX_PLL_MAX_CLK_DIV) {
LOG(logERROR,
("XILINX_PLL: Invalid clock divider, need to change base clock\n"));
return 1;
}
uint32_t clk_div_frac = 0;
// the first clock supports fractional division, increase the precision for
// that one fractional divide is not allowed in fixed or dynamic phase shift
// mode !!!!
if (clk_index == 0) {
float clk_div_frac_f =
(float)base_clk_freq / freq - clk_div; // eg. 2.333 => 0.333
clk_div_frac = (uint32_t)round(clk_div_frac_f * 1000); // 0.333 => 333
clk_div_frac = ((clk_div_frac + XILINX_PLL_HALF_STEP_SIZE) /
XILINX_PLL_STEP_SIZE) *
XILINX_PLL_STEP_SIZE; // round to multiples of step size,
// 333 = > 375
if (clk_div_frac == 1000) {
clk_div_frac = 0;
clk_div++;
}
}
LOG(logINFOBLUE, ("XILINX_PLL: Setting clock divider to %u.%u\n", clk_div,
clk_div_frac));
uint32_t clk_addr = XILINX_PLL_CLKCONFIG_BASE_ADDR +
clk_index * XILINX_PLL_CLKCONFIG_WIDTH +
XILINX_PLL_CLK_DIV_REG_OFST;
uint32_t clk_config_val = ((clk_div << XILINX_PLL_CLK_DIV_DIVIDE_OFST) &
XILINX_PLL_CLK_DIV_DIVIDE_MSK) |
((clk_div_frac << XILINX_PLL_CLK_DIV_FRAC_OFST) &
XILINX_PLL_CLK_DIV_FRAC_MSK);
bus_w_csp2(clk_addr, clk_config_val);
XILINX_PLL_load();
XILINX_PLL_waitForLock();
// wait for firmware to measure the actual frequency
usleep(2 * 1000 * 1000);
return 0;
}
uint32_t XILINX_PLL_getFrequency(uint32_t clk_index) {
if (clk_index >= XILINX_PLL_NUM_CLKS) {
LOG(logERROR, ("XILINX_PLL: Invalid clock index %d\n", clk_index));
return -1;
}
if (clk_index > XILINX_PLL_MAX_NUM_CLKS_FOR_GET) {
LOG(logERROR,
("XILINX_PLL: get frequency not implemented for this clock %d\n",
clk_index));
return -1;
}
uint32_t base_addr = XILINX_PLL_MEASURE_BASE_ADDR0;
if (clk_index >= XILINX_PLL_MEASURE_BASE_ADDR0_MAX_CLKS) {
clk_index -= XILINX_PLL_MEASURE_BASE_ADDR0_MAX_CLKS;
base_addr = XILINX_PLL_MEASURE_BASE_ADDR1;
}
uint32_t addr = base_addr + clk_index * XILINX_PLL_MEASURE_WIDTH;
uint32_t counter_val = bus_r_csp2(addr);
// Hz => round to nearest kHz
uint32_t freq_kHz = (counter_val + 500) / 1000; // round to nearest kHz
return freq_kHz;
}
bool XILINX_PLL_isLocked() {
uint32_t status = bus_r_csp2(XILINX_PLL_BASE_ADDR + XILINX_PLL_STATUS_REG);
return ((status & XILINX_PLL_STATUS_LOCKED_MSK) >>
XILINX_PLL_STATUS_LOCKED_OFST);
}
void XILINX_PLL_reset() {
bus_w_csp2(XILINX_PLL_BASE_ADDR + XILINX_PLL_RESET_REG,
XILINX_PLL_RESET_VAL);
}
void XILINX_PLL_load() {
bus_w_csp2(
XILINX_PLL_BASE_ADDR + XILINX_PLL_LOAD_REG,
(XILINX_PLL_LOAD_RECONFIGURE_MSK | XILINX_PLL_LOAD_FROM_REGS_MSK));
}
void XILINX_PLL_waitForLock() {
#ifdef VIRTUAL
return;
#endif
int timeout_us = 10 * 1000;
int count = 500;
while (count > 0) {
usleep(timeout_us);
if (XILINX_PLL_isLocked())
return;
count--;
}
LOG(logERROR, ("XILINX_PLL: Timeout waiting for PLL to lock (%d ms)\n",
(count * timeout_us) / 1000));
}

View File

@@ -13,14 +13,11 @@
/* global variables */
#define CSP0 (0xB0080000)
#define CSP1 (0xB0050000) // udp
#define CSP2 (0xA0000000)
#define MEM_SIZE_CSP0 (0x20000)
#define MEM_SIZE_CSP0 (0x10000)
#define MEM_SIZE_CSP1 (0x2000) // smaller size for udp
#define MEM_SIZE_CSP2 (0x4000)
u_int32_t *csp0base = 0;
u_int32_t *csp1base = 0;
u_int32_t *csp2base = 0;
void bus_w(u_int32_t offset, u_int32_t data) {
volatile u_int32_t *ptr1;
@@ -34,18 +31,6 @@ u_int32_t bus_r(u_int32_t offset) {
return *ptr1;
}
void bus_w_csp2(u_int32_t offset, u_int32_t data) {
volatile u_int32_t *ptr1;
ptr1 = (u_int32_t *)(csp2base + offset / (sizeof(u_int32_t)));
*ptr1 = data;
}
u_int32_t bus_r_csp2(u_int32_t offset) {
volatile u_int32_t *ptr1;
ptr1 = (u_int32_t *)(csp2base + offset / (sizeof(u_int32_t)));
return *ptr1;
}
uint64_t getU64BitReg(int aLSB, int aMSB) {
uint64_t retval = bus_r(aMSB);
retval = (retval << 32) | bus_r(aLSB);
@@ -66,12 +51,12 @@ u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
int mapCSP0(void) {
LOG(logINFO, ("Mapping memory\n"));
u_int32_t csps[3] = {CSP0, CSP1, CSP2};
u_int32_t **cspbases[3] = {&csp0base, &csp1base, &csp2base};
u_int32_t memsize[3] = {MEM_SIZE_CSP0, MEM_SIZE_CSP1, MEM_SIZE_CSP2};
char names[3][10] = {"csp0base", "csp1base", "csp2base"};
u_int32_t csps[2] = {CSP0, CSP1};
u_int32_t **cspbases[2] = {&csp0base, &csp1base};
u_int32_t memsize[2] = {MEM_SIZE_CSP0, MEM_SIZE_CSP1};
char names[2][10] = {"csp0base", "csp1base"};
for (int i = 0; i < 3; ++i) {
for (int i = 0; i < 2; ++i) {
// if not mapped
if (*cspbases[i] == 0) {
LOG(logINFO, ("\tMapping memory for %s\n", names[i]));

View File

@@ -13,7 +13,7 @@
extern enum TLogLevel trimmingPrint;
extern uint32_t clkDivider[];
#endif
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
#ifdef CHIPTESTBOARDD
extern uint32_t clkFrequency[];
#endif
@@ -54,12 +54,27 @@ void initializePatternWord() {
memset(virtual_pattern, 0, sizeof(virtual_pattern));
}
#endif
#endif
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
uint64_t validate_readPatternIOControl() {
#if defined(CHIPTESTBOARDD)
return getU64BitReg(PATTERN_IO_CNTRL_LSB_REG, PATTERN_IO_CNTRL_MSB_REG);
#elif defined(XILINX_CHIPTESTBOARDD)
return (uint64_t)(bus_r(PINIOCTRLREG));
#endif
}
int validate_writePatternIOControl(char *message, uint64_t arg) {
// validate input
#ifdef XILINX_CHIPTESTBOARDD
if (arg > BIT32_MSK) {
strcpy(message, "Could not set pattern IO Control. Must be 32 bit for "
"this detector\n");
LOG(logERROR, (message));
return FAIL;
}
#endif
writePatternIOControl(arg);
@@ -80,9 +95,15 @@ int validate_writePatternIOControl(char *message, uint64_t arg) {
}
void writePatternIOControl(uint64_t word) {
#ifdef CHIPTESTBOARDD
LOG(logINFO,
("Setting Pattern I/O Control: 0x%llx\n", (long long int)word));
setU64BitReg(word, PATTERN_IO_CNTRL_LSB_REG, PATTERN_IO_CNTRL_MSB_REG);
#elif defined(XILINX_CHIPTESTBOARDD)
uint32_t val = (uint32_t)word;
LOG(logINFO, ("Setting Pattern I/O Control: 0x%x\n", val));
bus_w(PINIOCTRLREG, val);
#endif
}
#endif
@@ -101,7 +122,7 @@ int validate_readPatternWord(char *message, int addr, uint64_t *word) {
}
uint64_t readPatternWord(int addr) {
#if defined(MYTHEN3D) || defined(XILINX_CHIPTESTBOARDD)
#ifdef MYTHEN3D
LOG(logDEBUG1, (" Reading Pattern Word (addr:0x%x)\n", addr));
// the first word in RAM as base plus the offset of the word to write (addr)
uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr * REG_OFFSET * 2;
@@ -161,7 +182,7 @@ void writePatternWord(int addr, uint64_t word) {
LOG(logDEBUG1, ("Setting Pattern Word (addr:0x%x, word:0x%llx)\n", addr,
(long long int)word));
#ifdef CHIPTESTBOARDD
#ifndef MYTHEN3D
uint32_t reg = PATTERN_CNTRL_REG;
// write word
@@ -178,6 +199,7 @@ void writePatternWord(int addr, uint64_t word) {
#ifdef VIRTUAL
virtual_pattern[addr] = word;
#endif
// mythen
#else
// the first word in RAM as base plus the offset of the word to write (addr)
uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr * REG_OFFSET * 2;
@@ -201,15 +223,29 @@ int validate_getPatternWaitAddresses(char *message, int level, int *addr) {
}
int getPatternWaitAddress(int level) {
if (level < 0 || level >= MAX_LEVELS) {
switch (level) {
case 0:
return ((bus_r(PATTERN_WAIT_0_ADDR_REG) & PATTERN_WAIT_0_ADDR_MSK) >>
PATTERN_WAIT_0_ADDR_OFST);
case 1:
return ((bus_r(PATTERN_WAIT_1_ADDR_REG) & PATTERN_WAIT_1_ADDR_MSK) >>
PATTERN_WAIT_1_ADDR_OFST);
case 2:
return ((bus_r(PATTERN_WAIT_2_ADDR_REG) & PATTERN_WAIT_2_ADDR_MSK) >>
PATTERN_WAIT_2_ADDR_OFST);
#ifndef MYTHEN3D
case 3:
return ((bus_r(PATTERN_WAIT_3_ADDR_REG) & PATTERN_WAIT_3_ADDR_MSK) >>
PATTERN_WAIT_3_ADDR_OFST);
case 4:
return ((bus_r(PATTERN_WAIT_4_ADDR_REG) & PATTERN_WAIT_4_ADDR_MSK) >>
PATTERN_WAIT_4_ADDR_OFST);
case 5:
return ((bus_r(PATTERN_WAIT_5_ADDR_REG) & PATTERN_WAIT_5_ADDR_MSK) >>
PATTERN_WAIT_5_ADDR_OFST);
#endif
default:
return -1;
} else {
return ((bus_r(PATTERN_LOOPDEF_BASE +
(PATTERN_WAIT_ADDR_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET) &
PATTERN_WAIT_ADDR_MSK) >>
PATTERN_WAIT_ADDR_OFST);
}
}
@@ -253,13 +289,35 @@ void setPatternWaitAddress(int level, int addr) {
LOG(logINFO,
#endif
("Setting Pattern Wait Address (level:%d, addr:0x%x)\n", level, addr));
if (level < 0 || level >= MAX_LEVELS) {
switch (level) {
case 0:
bus_w(PATTERN_WAIT_0_ADDR_REG,
((addr << PATTERN_WAIT_0_ADDR_OFST) & PATTERN_WAIT_0_ADDR_MSK));
break;
case 1:
bus_w(PATTERN_WAIT_1_ADDR_REG,
((addr << PATTERN_WAIT_1_ADDR_OFST) & PATTERN_WAIT_1_ADDR_MSK));
break;
case 2:
bus_w(PATTERN_WAIT_2_ADDR_REG,
((addr << PATTERN_WAIT_2_ADDR_OFST) & PATTERN_WAIT_2_ADDR_MSK));
break;
#ifndef MYTHEN3D
case 3:
bus_w(PATTERN_WAIT_3_ADDR_REG,
((addr << PATTERN_WAIT_3_ADDR_OFST) & PATTERN_WAIT_3_ADDR_MSK));
break;
case 4:
bus_w(PATTERN_WAIT_4_ADDR_REG,
((addr << PATTERN_WAIT_4_ADDR_OFST) & PATTERN_WAIT_4_ADDR_MSK));
break;
case 5:
bus_w(PATTERN_WAIT_5_ADDR_REG,
((addr << PATTERN_WAIT_5_ADDR_OFST) & PATTERN_WAIT_5_ADDR_MSK));
break;
#endif
default:
return;
} else {
bus_w(PATTERN_LOOPDEF_BASE + (PATTERN_WAIT_ADDR_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET,
((addr << PATTERN_WAIT_ADDR_OFST) & PATTERN_WAIT_ADDR_MSK));
}
}
@@ -282,24 +340,39 @@ int validate_getPatternWaitClocksAndInterval(char *message, int level,
}
uint64_t getPatternWaitClocks(int level) {
if (level < 0 || level >= MAX_LEVELS) {
switch (level) {
case 0:
return getU64BitReg(PATTERN_WAIT_TIMER_0_LSB_REG,
PATTERN_WAIT_TIMER_0_MSB_REG);
case 1:
return getU64BitReg(PATTERN_WAIT_TIMER_1_LSB_REG,
PATTERN_WAIT_TIMER_1_MSB_REG);
case 2:
return getU64BitReg(PATTERN_WAIT_TIMER_2_LSB_REG,
PATTERN_WAIT_TIMER_2_MSB_REG);
#ifndef MYTHEN3D
case 3:
return getU64BitReg(PATTERN_WAIT_TIMER_3_LSB_REG,
PATTERN_WAIT_TIMER_3_MSB_REG);
case 4:
return getU64BitReg(PATTERN_WAIT_TIMER_4_LSB_REG,
PATTERN_WAIT_TIMER_4_MSB_REG);
case 5:
return getU64BitReg(PATTERN_WAIT_TIMER_5_LSB_REG,
PATTERN_WAIT_TIMER_5_MSB_REG);
#endif
default:
return -1;
} else {
return getU64BitReg(
PATTERN_LOOPDEF_BASE + (PATTERN_WAIT_TIMER_LSB_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET,
PATTERN_LOOPDEF_BASE + (PATTERN_WAIT_TIMER_MSB_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET);
}
}
uint64_t getPatternWaitInterval(int level) {
uint64_t numClocks = getPatternWaitClocks(level);
int runclk = 0;
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
#ifdef CHIPTESTBOARDD
runclk = clkFrequency[RUN_CLK];
#elif XILINX_CHIPTESTBOARDD
runclk = RUN_CLK;
#elif MYTHEN3D
runclk = clkDivider[SYSTEM_C0];
#endif
@@ -307,7 +380,7 @@ uint64_t getPatternWaitInterval(int level) {
LOG(logERROR, ("runclk is 0. Cannot divide by 0. Returning -1.\n"));
return -1;
}
return numClocks / (NS_TO_CLK_CYCLE * runclk);
return numClocks / (1E-3 * runclk);
}
int validate_setPatternWaitClocksAndInterval(char *message, int level,
@@ -352,18 +425,35 @@ void setPatternWaitClocks(int level, uint64_t t) {
#endif
("Setting Pattern Wait Time in clocks (level:%d) :%lld\n", level,
(long long int)t));
if (level < 0 || level >= MAX_LEVELS) {
switch (level) {
case 0:
setU64BitReg(t, PATTERN_WAIT_TIMER_0_LSB_REG,
PATTERN_WAIT_TIMER_0_MSB_REG);
break;
case 1:
setU64BitReg(t, PATTERN_WAIT_TIMER_1_LSB_REG,
PATTERN_WAIT_TIMER_1_MSB_REG);
break;
case 2:
setU64BitReg(t, PATTERN_WAIT_TIMER_2_LSB_REG,
PATTERN_WAIT_TIMER_2_MSB_REG);
break;
#ifndef MYTHEN3D
case 3:
setU64BitReg(t, PATTERN_WAIT_TIMER_3_LSB_REG,
PATTERN_WAIT_TIMER_3_MSB_REG);
break;
case 4:
setU64BitReg(t, PATTERN_WAIT_TIMER_4_LSB_REG,
PATTERN_WAIT_TIMER_4_MSB_REG);
break;
case 5:
setU64BitReg(t, PATTERN_WAIT_TIMER_5_LSB_REG,
PATTERN_WAIT_TIMER_5_MSB_REG);
break;
#endif
default:
return;
} else {
return setU64BitReg(
t,
PATTERN_LOOPDEF_BASE + (PATTERN_WAIT_TIMER_LSB_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET,
PATTERN_LOOPDEF_BASE + (PATTERN_WAIT_TIMER_MSB_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET);
}
}
@@ -376,12 +466,14 @@ void setPatternWaitInterval(int level, uint64_t t) {
("Setting Pattern Wait Time (level:%d) :%lld ns\n", level,
(long long int)t));
int runclk = 0;
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
#ifdef CHIPTESTBOARDD
runclk = clkFrequency[RUN_CLK];
#elif XILINX_CHIPTESTBOARDD
runclk = RUN_CLK;
#elif MYTHEN3D
runclk = clkDivider[SYSTEM_C0];
runclk = clkDivider[SYSTEM_C0];
#endif
uint64_t numClocks = t * (NS_TO_CLK_CYCLE * runclk);
uint64_t numClocks = t * (1E-3 * runclk);
setPatternWaitClocks(level, numClocks);
}
@@ -399,13 +491,23 @@ int validate_getPatternLoopCycles(char *message, int level, int *numLoops) {
}
int getPatternLoopCycles(int level) {
if (level < 0 || level >= MAX_LEVELS) {
switch (level) {
case 0:
return bus_r(PATTERN_LOOP_0_ITERATION_REG);
case 1:
return bus_r(PATTERN_LOOP_1_ITERATION_REG);
case 2:
return bus_r(PATTERN_LOOP_2_ITERATION_REG);
#ifndef MYTHEN3D
case 3:
return bus_r(PATTERN_LOOP_3_ITERATION_REG);
case 4:
return bus_r(PATTERN_LOOP_4_ITERATION_REG);
case 5:
return bus_r(PATTERN_LOOP_5_ITERATION_REG);
#endif
default:
return -1;
} else {
return bus_r(PATTERN_LOOPDEF_BASE +
(PATTERN_LOOP_ITERATION_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET);
}
}
@@ -444,13 +546,29 @@ void setPatternLoopCycles(int level, int nLoop) {
LOG(logINFO,
#endif
("Setting Pattern Loop Cycles(level:%d, nLoop:%d)\n", level, nLoop));
if (level < 0 || level >= MAX_LEVELS) {
switch (level) {
case 0:
bus_w(PATTERN_LOOP_0_ITERATION_REG, nLoop);
break;
case 1:
bus_w(PATTERN_LOOP_1_ITERATION_REG, nLoop);
break;
case 2:
bus_w(PATTERN_LOOP_2_ITERATION_REG, nLoop);
break;
#ifndef MYTHEN3D
case 3:
bus_w(PATTERN_LOOP_3_ITERATION_REG, nLoop);
break;
case 4:
bus_w(PATTERN_LOOP_4_ITERATION_REG, nLoop);
break;
case 5:
bus_w(PATTERN_LOOP_5_ITERATION_REG, nLoop);
break;
#endif
default:
return;
} else {
bus_w(PATTERN_LOOPDEF_BASE + (PATTERN_LOOP_ITERATION_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET,
nLoop);
}
}
@@ -521,22 +639,59 @@ int validate_getPatternLoopAddresses(char *message, int level, int *startAddr,
}
void getPatternLoopAddresses(int level, int *startAddr, int *stopAddr) {
if (level < 0 || level >= MAX_LEVELS) {
*startAddr = -1;
*stopAddr = -1;
} else {
*startAddr = ((bus_r(PATTERN_LOOPDEF_BASE +
(PATTERN_LOOP_ADDR_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET) &
PATTERN_LOOP_ADDR_STRT_MSK) >>
PATTERN_LOOP_ADDR_STRT_OFST);
*stopAddr = ((bus_r(PATTERN_LOOPDEF_BASE +
(PATTERN_LOOP_ADDR_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET) &
PATTERN_LOOP_ADDR_STP_MSK) >>
PATTERN_LOOP_ADDR_STP_OFST);
switch (level) {
case 0:
*startAddr =
((bus_r(PATTERN_LOOP_0_ADDR_REG) & PATTERN_LOOP_0_ADDR_STRT_MSK) >>
PATTERN_LOOP_0_ADDR_STRT_OFST);
*stopAddr =
((bus_r(PATTERN_LOOP_0_ADDR_REG) & PATTERN_LOOP_0_ADDR_STP_MSK) >>
PATTERN_LOOP_0_ADDR_STP_OFST);
break;
case 1:
*startAddr =
((bus_r(PATTERN_LOOP_1_ADDR_REG) & PATTERN_LOOP_1_ADDR_STRT_MSK) >>
PATTERN_LOOP_1_ADDR_STRT_OFST);
*stopAddr =
((bus_r(PATTERN_LOOP_1_ADDR_REG) & PATTERN_LOOP_1_ADDR_STP_MSK) >>
PATTERN_LOOP_1_ADDR_STP_OFST);
break;
case 2:
*startAddr =
((bus_r(PATTERN_LOOP_2_ADDR_REG) & PATTERN_LOOP_2_ADDR_STRT_MSK) >>
PATTERN_LOOP_2_ADDR_STRT_OFST);
*stopAddr =
((bus_r(PATTERN_LOOP_2_ADDR_REG) & PATTERN_LOOP_2_ADDR_STP_MSK) >>
PATTERN_LOOP_2_ADDR_STP_OFST);
break;
#ifndef MYTHEN3D
case 3:
*startAddr =
((bus_r(PATTERN_LOOP_3_ADDR_REG) & PATTERN_LOOP_3_ADDR_STRT_MSK) >>
PATTERN_LOOP_3_ADDR_STRT_OFST);
*stopAddr =
((bus_r(PATTERN_LOOP_3_ADDR_REG) & PATTERN_LOOP_3_ADDR_STP_MSK) >>
PATTERN_LOOP_3_ADDR_STP_OFST);
break;
case 4:
*startAddr =
((bus_r(PATTERN_LOOP_4_ADDR_REG) & PATTERN_LOOP_4_ADDR_STRT_MSK) >>
PATTERN_LOOP_4_ADDR_STRT_OFST);
*stopAddr =
((bus_r(PATTERN_LOOP_4_ADDR_REG) & PATTERN_LOOP_4_ADDR_STP_MSK) >>
PATTERN_LOOP_4_ADDR_STP_OFST);
break;
case 5:
*startAddr =
((bus_r(PATTERN_LOOP_5_ADDR_REG) & PATTERN_LOOP_5_ADDR_STRT_MSK) >>
PATTERN_LOOP_5_ADDR_STRT_OFST);
*stopAddr =
((bus_r(PATTERN_LOOP_5_ADDR_REG) & PATTERN_LOOP_5_ADDR_STP_MSK) >>
PATTERN_LOOP_5_ADDR_STP_OFST);
break;
#endif
default:
return;
}
}
@@ -592,16 +747,53 @@ void setPatternLoopAddresses(int level, int startAddr, int stopAddr) {
("Setting Pattern Loop Address (level:%d, startaddr:0x%x, "
"stopaddr:0x%x)\n",
level, startAddr, stopAddr));
if (level < 0 || level >= MAX_LEVELS) {
switch (level) {
case 0:
bus_w(PATTERN_LOOP_0_ADDR_REG,
((startAddr << PATTERN_LOOP_0_ADDR_STRT_OFST) &
PATTERN_LOOP_0_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_0_ADDR_STP_OFST) &
PATTERN_LOOP_0_ADDR_STP_MSK));
break;
case 1:
bus_w(PATTERN_LOOP_1_ADDR_REG,
((startAddr << PATTERN_LOOP_1_ADDR_STRT_OFST) &
PATTERN_LOOP_1_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_1_ADDR_STP_OFST) &
PATTERN_LOOP_1_ADDR_STP_MSK));
break;
case 2:
bus_w(PATTERN_LOOP_2_ADDR_REG,
((startAddr << PATTERN_LOOP_2_ADDR_STRT_OFST) &
PATTERN_LOOP_2_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_2_ADDR_STP_OFST) &
PATTERN_LOOP_2_ADDR_STP_MSK));
break;
#ifndef MYTHEN3D
case 3:
bus_w(PATTERN_LOOP_3_ADDR_REG,
((startAddr << PATTERN_LOOP_3_ADDR_STRT_OFST) &
PATTERN_LOOP_3_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_3_ADDR_STP_OFST) &
PATTERN_LOOP_3_ADDR_STP_MSK));
break;
case 4:
bus_w(PATTERN_LOOP_4_ADDR_REG,
((startAddr << PATTERN_LOOP_4_ADDR_STRT_OFST) &
PATTERN_LOOP_4_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_4_ADDR_STP_OFST) &
PATTERN_LOOP_4_ADDR_STP_MSK));
break;
case 5:
bus_w(PATTERN_LOOP_5_ADDR_REG,
((startAddr << PATTERN_LOOP_5_ADDR_STRT_OFST) &
PATTERN_LOOP_5_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_5_ADDR_STP_OFST) &
PATTERN_LOOP_5_ADDR_STP_MSK));
break;
#endif
default:
return;
} else {
bus_w(PATTERN_LOOPDEF_BASE + (PATTERN_LOOP_ADDR_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET,
((startAddr << PATTERN_LOOP_ADDR_STRT_OFST) &
PATTERN_LOOP_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_ADDR_STP_OFST) &
PATTERN_LOOP_ADDR_STP_MSK));
}
}
@@ -623,43 +815,17 @@ uint64_t getPatternBitMask() {
return getU64BitReg(PATTERN_SET_LSB_REG, PATTERN_SET_MSB_REG);
}
#ifdef MYTHEN3D
void startPattern() {
LOG(logINFOBLUE, ("Starting Pattern\n"));
#ifdef MYTHEN3D
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STRT_PATTERN_MSK);
usleep(1);
while (bus_r(PAT_STATUS_REG) & PAT_STATUS_RUN_BUSY_MSK) {
usleep(1);
}
#elif CHIPTESTBOARDD
// we only want to run the pattern here. No acquisition, no UDP packets
// disable 10G UDP temporarily
// except if the pattern explicitly contains udp trigger points
uint32_t conf_reg_tmp = bus_r(CONFIG_REG);
if ((bus_r(STREAMING_CTRL_REG) & STREAMING_CTRL_ENA_MSK) == 0) {
bus_w(CONFIG_REG, conf_reg_tmp & ~CONFIG_GB10_SND_UDP_MSK);
}
// run the pattern, wait till done
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STRT_ACQSTN_MSK);
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_STRT_ACQSTN_MSK);
usleep(1);
while (bus_r(STATUS_REG) & STATUS_RN_BSY_MSK) {
usleep(1);
}
// go back to original config
bus_w(CONFIG_REG, conf_reg_tmp);
#elif XILINX_CHIPTESTBOARDD
bus_w(FLOW_CONTROL_REG, bus_r(FLOW_CONTROL_REG) | START_F_MSK);
usleep(1);
while (bus_r(FLOW_CONTROL_REG) & RSM_BUSY_MSK) {
usleep(1);
}
#endif
LOG(logINFOBLUE, ("Pattern done\n"));
}
#endif
char *getPatternFileName() { return clientPatternfile; }

View File

@@ -5798,7 +5798,7 @@ int set_clock_frequency(int file_des) {
return printSocketReadError();
LOG(logDEBUG1, ("Setting clock (%d) frequency : %u\n", args[0], args[1]));
#if !defined(CHIPTESTBOARDD) && !defined(XILINX_CHIPTESTBOARDD)
#if !defined(CHIPTESTBOARDD)
functionNotImplemented();
#else
@@ -5811,7 +5811,7 @@ int set_clock_frequency(int file_des) {
case ADC_CLOCK:
c = ADC_CLK;
break;
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
#ifdef CHIPTESTBOARDD
case DBIT_CLOCK:
c = DBIT_CLK;
break;
@@ -5839,24 +5839,11 @@ int set_clock_frequency(int file_des) {
LOG(logINFO, ("Same %s: %d %s\n", modeName, val,
myDetectorType == GOTTHARD2 ? "Hz" : "MHz"));
} else {
int ret = setFrequency(c, val);
if (ret == FAIL) {
sprintf(mess, "Could not set %s to %d %s\n", modeName, val,
myDetectorType == XILINX_CHIPTESTBOARD ? "kHz"
: "MHz");
LOG(logERROR, (mess));
} else {
int retval = getFrequency(c);
LOG(logDEBUG1,
("retval %s: %d %s\n", modeName, retval,
myDetectorType == XILINX_CHIPTESTBOARD ? "kHz"
: "MHz"));
#if !defined(XILINX_CHIPTESTBOARDD)
// XCTB will give the actual frequency, which is not
// 100% identical to the set frequency
validate(&ret, mess, val, retval, modeName, DEC);
#endif
}
setFrequency(c, val);
int retval = getFrequency(c);
LOG(logDEBUG1, ("retval %s: %d %s\n", modeName, retval,
myDetectorType == GOTTHARD2 ? "Hz" : "MHz"));
validate(&ret, mess, val, retval, modeName, DEC);
}
}
}
@@ -5874,14 +5861,13 @@ int get_clock_frequency(int file_des) {
return printSocketReadError();
LOG(logDEBUG1, ("Getting clock (%d) frequency\n", arg));
#if !defined(CHIPTESTBOARDD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D) && \
!defined(XILINX_CHIPTESTBOARDD)
#if !defined(CHIPTESTBOARDD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D)
functionNotImplemented();
#else
// get only
enum CLKINDEX c = 0;
switch (arg) {
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
#if defined(CHIPTESTBOARDD)
case ADC_CLOCK:
c = ADC_CLK;
break;
@@ -5911,11 +5897,8 @@ int get_clock_frequency(int file_des) {
LOG(logDEBUG1,
("retval %s clock (%d) frequency: %d %s\n", clock_names[c], (int)c,
retval,
myDetectorType == XILINX_CHIPTESTBOARD
? "kHz"
: (myDetectorType == GOTTHARD2 || myDetectorType == MYTHEN3
? "Hz"
: "MHz")));
myDetectorType == GOTTHARD2 || myDetectorType == MYTHEN3 ? "Hz"
: "MHz"));
}
#endif
return Server_SendResult(file_des, INT32, &retval, sizeof(retval));
@@ -7480,8 +7463,7 @@ int start_pattern(int file_des) {
memset(mess, 0, sizeof(mess));
LOG(logDEBUG1, ("Starting Pattern\n"));
#if !defined(MYTHEN3D) && !defined(XILINX_CHIPTESTBOARDD) && \
!defined(CHIPTESTBOARDD)
#ifndef MYTHEN3D
functionNotImplemented();
#else
// only set

View File

@@ -6,7 +6,6 @@ add_executable(xilinx_ctbDetectorServer_virtual
../slsDetectorServer/src/slsDetectorServer_funcs.c
../slsDetectorServer/src/communication_funcs.c
../slsDetectorServer/src/arm64.c
../slsDetectorServer/src/XILINX_PLL.c
../slsDetectorServer/src/common.c
../slsDetectorServer/src/sharedMemory.c
../slsDetectorServer/src/loadPattern.c
@@ -31,9 +30,7 @@ target_compile_definitions(xilinx_ctbDetectorServer_virtual
)
target_link_libraries(xilinx_ctbDetectorServer_virtual
PUBLIC
m
slsProjectCSettings
PUBLIC pthread rt m slsProjectCSettings
)
set_target_properties(xilinx_ctbDetectorServer_virtual PROPERTIES

View File

@@ -23,7 +23,7 @@ DESTDIR ?= bin
INSTMODE = 0777
SRCS = slsDetectorFunctionList.c
SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)arm64.c $(main_src)XILINX_PLL.c $(main_src)common.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c $(main_src)programViaArm.c $(main_src)LTC2620_Driver.c
SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)arm64.c $(main_src)common.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c $(main_src)programViaArm.c $(main_src)LTC2620_Driver.c
OBJS = $(SRCS:.c=.o)

View File

@@ -2,16 +2,10 @@
// Copyright (C) 2021 Contributors to the SLS Detector Package
#pragma once
// clang-format off
#define REG_OFFSET (4)
#define PATTERN_STEP0_MSB_REG (0x10004)
#define PATTERN_STEP0_LSB_REG (0x10000)
#define CTRL_REG (0x8000)
#define POWER_VIO_OFST (0)
#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST)
#define POWER_VIO_OFST (0)
#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST)
#define POWER_VCC_A_OFST (1)
#define POWER_VCC_A_MSK (0x00000001 << POWER_VCC_A_OFST)
#define POWER_VCC_B_OFST (2)
@@ -23,20 +17,20 @@
#define STATUS_REG (0x8004)
#define PATTERN_RUNNING_OFST (0)
#define PATTERN_RUNNING_MSK (0x00000001 << PATTERN_RUNNING_OFST)
#define RX_BUSY_OFST (1)
#define RX_BUSY_MSK (0x00000001 << RX_BUSY_OFST)
#define PROCESSING_BUSY_OFST (2)
#define PROCESSING_BUSY_MSK (0x00000001 << PROCESSING_BUSY_OFST)
#define UDP_GEN_BUSY_OFST (3)
#define UDP_GEN_BUSY_MSK (0x00000001 << UDP_GEN_BUSY_OFST)
#define NETWORK_BUSY_OFST (4)
#define NETWORK_BUSY_MSK (0x00000001 << NETWORK_BUSY_OFST)
#define PATTERN_RUNNING_OFST (0)
#define PATTERN_RUNNING_MSK (0x00000001 << PATTERN_RUNNING_OFST)
#define RX_BUSY_OFST (1)
#define RX_BUSY_MSK (0x00000001 << RX_BUSY_OFST)
#define PROCESSING_BUSY_OFST (2)
#define PROCESSING_BUSY_MSK (0x00000001 << PROCESSING_BUSY_OFST)
#define UDP_GEN_BUSY_OFST (3)
#define UDP_GEN_BUSY_MSK (0x00000001 << UDP_GEN_BUSY_OFST)
#define NETWORK_BUSY_OFST (4)
#define NETWORK_BUSY_MSK (0x00000001 << NETWORK_BUSY_OFST)
#define WAIT_FOR_TRIGGER_OFST (5)
#define WAIT_FOR_TRIGGER_MSK (0x00000001 << WAIT_FOR_TRIGGER_OFST)
#define RX_NOT_GOOD_OFST (6)
#define RX_NOT_GOOD_MSK (0x00000001 << RX_NOT_GOOD_OFST)
#define RX_NOT_GOOD_OFST (6)
#define RX_NOT_GOOD_MSK (0x00000001 << RX_NOT_GOOD_OFST)
#define STATUS_REG2 (0x8008)
@@ -44,8 +38,8 @@
#define FPGACOMPDATE_OFST (0)
#define FPGACOMPDATE_MSK (0x00ffffff << FPGACOMPDATE_OFST)
#define FPGADETTYPE_OFST (24)
#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
#define FPGADETTYPE_OFST (24)
#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
#define FPGA_GIT_HEAD (0x8010)
@@ -56,8 +50,8 @@
#define APICOMPDATE_OFST (0)
#define APICOMPDATE_MSK (0x00ffffff << APICOMPDATE_OFST)
#define APIDETTYPE_OFST (24)
#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST)
#define APIDETTYPE_OFST (24)
#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST)
#define A_FIFO_OVERFLOW_STATUS_REG (0x9000)
@@ -109,22 +103,23 @@
#define FIFO_TO_GB_CONTROL_REG (0xA000)
#define ENABLED_CHANNELS_ADC_OFST (0)
#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
#define ENABLED_CHANNELS_D_OFST (8)
#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST)
#define ENABLED_CHANNELS_X_OFST (9)
#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST)
#define RO_MODE_ADC_OFST (13)
#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST)
#define RO_MODE_D_OFST (14)
#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST)
#define RO_MODE_X_OFST (15)
#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
#define ENABLED_CHANNELS_ADC_OFST (0)
#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
#define ENABLED_CHANNELS_D_OFST (8)
#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST)
#define ENABLED_CHANNELS_X_OFST (9)
#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST)
#define RO_MODE_ADC_OFST (13)
#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST)
#define RO_MODE_D_OFST (14)
#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST)
#define RO_MODE_X_OFST (15)
#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
#define COUNT_FRAMES_FROM_UPDATE_OFST (16)
#define COUNT_FRAMES_FROM_UPDATE_MSK (0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
#define START_STREAMING_P_OFST (17)
#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
#define COUNT_FRAMES_FROM_UPDATE_MSK \
(0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
#define START_STREAMING_P_OFST (17)
#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
#define STREAM_BUFFER_CLEAR_OFST (18)
#define STREAM_BUFFER_CLEAR_MSK (0x00000001 << STREAM_BUFFER_CLEAR_OFST)
@@ -153,26 +148,26 @@
#define PKTPACKETLENGTHREG (0xA020)
#define PACKETLENGTH1G_OFST (0)
#define PACKETLENGTH1G_MSK (0x0000ffff << PACKETLENGTH1G_OFST)
#define PACKETLENGTH1G_OFST (0)
#define PACKETLENGTH1G_MSK (0x0000ffff << PACKETLENGTH1G_OFST)
#define PACKETLENGTH10G_OFST (16)
#define PACKETLENGTH10G_MSK (0x0000ffff << PACKETLENGTH10G_OFST)
#define PKTNOPACKETSREG (0xA024)
#define NOPACKETS1G_OFST (0)
#define NOPACKETS1G_MSK (0x0000003f << NOPACKETS1G_OFST)
#define NOPACKETS1G_OFST (0)
#define NOPACKETS1G_MSK (0x0000003f << NOPACKETS1G_OFST)
#define NOPACKETS10G_OFST (16)
#define NOPACKETS10G_MSK (0x0000003f << NOPACKETS10G_OFST)
#define PKTCTRLREG (0xA028)
#define NOSERVERS_OFST (0)
#define NOSERVERS_MSK (0x0000003f << NOSERVERS_OFST)
#define NOSERVERS_OFST (0)
#define NOSERVERS_MSK (0x0000003f << NOSERVERS_OFST)
#define SERVERSTART_OFST (8)
#define SERVERSTART_MSK (0x0000001f << SERVERSTART_OFST)
#define ETHINTERF_OFST (16)
#define ETHINTERF_MSK (0x00000001 << ETHINTERF_OFST)
#define ETHINTERF_OFST (16)
#define ETHINTERF_MSK (0x00000001 << ETHINTERF_OFST)
#define PKTCOORDREG1 (0xA02C)
@@ -186,282 +181,363 @@
#define COORDZ_OFST (0)
#define COORDZ_MSK (0x0000ffff << COORDZ_OFST)
#define PATTERN_OUT_LSB_REG (0xB000)
#define FLOW_STATUS_REG (0xB000)
#define PATTERN_OUT_MSB_REG (0xB004)
#define RSM_BUSY_OFST (0)
#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
#define RSM_TRG_WAIT_OFST (3)
#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST)
#define CSM_BUSY_OFST (17)
#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
#define PATTERN_IN_LSB_REG (0xB008)
#define FLOW_CONTROL_REG (0xB004)
#define PATTERN_IN_MSB_REG (0xB00C)
#define START_F_OFST (0)
#define START_F_MSK (0x00000001 << START_F_OFST)
#define STOP_F_OFST (1)
#define STOP_F_MSK (0x00000001 << STOP_F_OFST)
#define RST_F_OFST (2)
#define RST_F_MSK (0x00000001 << RST_F_OFST)
#define SW_TRIGGER_F_OFST (3)
#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
#define TRIGGER_ENABLE_OFST (4)
#define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST)
#define PATTERN_MASK_LSB_REG (0xB010)
#define TIME_FROM_START_OUT_REG_1 (0xB008)
#define PATTERN_MASK_MSB_REG (0xB014)
#define TIME_FROM_START_OUT_REG_2 (0xB00C)
#define PATTERN_SET_LSB_REG (0xB018)
#define FRAMES_FROM_START_OUT_REG_1 (0xB010)
#define PATTERN_SET_MSB_REG (0xB01C)
#define FRAMES_FROM_START_OUT_REG_2 (0xB014)
#define PATTERN_CNTRL_REG (0xB020)
#define FRAME_TIME_OUT_REG_1 (0xB018)
#define PATTERN_CNTRL_WR_OFST (0)
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
#define PATTERN_CNTRL_RD_OFST (1)
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
#define FRAME_TIME_OUT_REG_2 (0xB01C)
#define DELAY_OUT_REG_1 (0xB020)
#define DELAY_OUT_REG_2 (0xB024)
#define CYCLES_OUT_REG_1 (0xB028)
#define CYCLES_OUT_REG_2 (0xB02C)
#define FRAMES_OUT_REG_1 (0xB030)
#define FRAMES_OUT_REG_2 (0xB034)
#define PERIOD_OUT_REG_1 (0xB038)
#define PERIOD_OUT_REG_2 (0xB03C)
#define DELAY_IN_REG_1 (0xB040)
#define DELAY_IN_REG_2 (0xB044)
#define CYCLES_IN_REG_1 (0xB048)
#define CYCLES_IN_REG_2 (0xB04C)
#define FRAMES_IN_REG_1 (0xB050)
#define FRAMES_IN_REG_2 (0xB054)
#define PERIOD_IN_REG_1 (0xB058)
#define PERIOD_IN_REG_2 (0xB05C)
#define PATTERN_OUT_LSB_REG (0xB100)
#define PATTERN_OUT_MSB_REG (0xB104)
#define PATTERN_IN_LSB_REG (0xB108)
#define PATTERN_IN_MSB_REG (0xB10C)
#define PATTERN_MASK_LSB_REG (0xB110)
#define PATTERN_MASK_MSB_REG (0xB114)
#define PATTERN_SET_LSB_REG (0xB118)
#define PATTERN_SET_MSB_REG (0xB11C)
#define PATTERN_CNTRL_REG (0xB120)
#define PATTERN_CNTRL_WR_OFST (0)
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
#define PATTERN_CNTRL_RD_OFST (1)
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
#define PATTERN_CNTRL_ADDR_OFST (16)
#define PATTERN_CNTRL_ADDR_MSK (0x00001fff << PATTERN_CNTRL_ADDR_OFST)
#define PATTERN_LIMIT_REG (0xB024)
#define PATTERN_LIMIT_REG (0xB124)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x00001fff << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST)
#define PATTERN_IO_CNTRL_LSB_REG (0xB028)
#define PATTERN_LOOP_0_ADDR_REG (0xB128)
#define PATTERN_IO_CNTRL_MSB_REG (0xB02C)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STP_OFST)
#define FLOW_CONTROL_REG (0xB030)
#define PATTERN_LOOP_0_ITERATION_REG (0xB12C)
#define START_F_OFST (0)
#define START_F_MSK (0x00000001 << START_F_OFST)
#define STOP_F_OFST (1)
#define STOP_F_MSK (0x00000001 << STOP_F_OFST)
#define RST_F_OFST (2)
#define RST_F_MSK (0x00000001 << RST_F_OFST)
#define SW_TRIGGER_F_OFST (3)
#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
#define TRIGGER_ENABLE_OFST (4)
#define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST)
#define RSM_BUSY_OFST (5)
#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
#define RSM_TRG_WAIT_OFST (6)
#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST)
#define CSM_BUSY_OFST (7)
#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
#define PATTERN_WAIT_0_ADDR_REG (0xB130)
#define DELAY_IN_REG_1 (0xB034)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001fff << PATTERN_WAIT_0_ADDR_OFST)
#define DELAY_IN_REG_2 (0xB038)
#define PATTERN_WAIT_TIMER_0_LSB_REG (0xB134)
#define CYCLES_IN_REG_1 (0xB03C)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0xB138)
#define CYCLES_IN_REG_2 (0xB040)
#define PATTERN_LOOP_1_ADDR_REG (0xB13C)
#define FRAMES_IN_REG_1 (0xB044)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STP_OFST)
#define FRAMES_IN_REG_2 (0xB048)
#define PATTERN_LOOP_1_ITERATION_REG (0xB140)
#define PERIOD_IN_REG_1 (0xB04C)
#define PATTERN_WAIT_1_ADDR_REG (0xB144)
#define PERIOD_IN_REG_2 (0xB050)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001fff << PATTERN_WAIT_1_ADDR_OFST)
#define PATTERN_TEST_REG (0xB054)
#define PATTERN_WAIT_TIMER_1_LSB_REG (0xB148)
#define PATTERN_FIRMWARE_REG (0xB058)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0xB14C)
#define PATTERN_WIDTH_OFST (0)
#define PATTERN_WIDTH_MSK (0x000000ff << PATTERN_WIDTH_OFST)
#define PATTERN_ADDR_WIDTH_OFST (8)
#define PATTERN_ADDR_WIDTH_MSK (0x000000ff << PATTERN_ADDR_WIDTH_OFST)
#define PATTERN_NLOOPS_NWAITS_OFST (16)
#define PATTERN_NLOOPS_NWAITS_MSK (0x000000ff << PATTERN_NLOOPS_NWAITS_OFST)
#define DIRECT_PATTERN_RAM_OFST (24)
#define DIRECT_PATTERN_RAM_MSK (0x00000001 << DIRECT_PATTERN_RAM_OFST)
#define PATTERN_LOOP_2_ADDR_REG (0xB150)
#define TIME_FROM_START_OUT_REG_1 (0xB05C)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STP_OFST)
#define TIME_FROM_START_OUT_REG_2 (0xB060)
#define PATTERN_LOOP_2_ITERATION_REG (0xB154)
#define FRAMES_FROM_START_OUT_REG_1 (0xB064)
#define PATTERN_WAIT_2_ADDR_REG (0xB158)
#define FRAMES_FROM_START_OUT_REG_2 (0xB068)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001fff << PATTERN_WAIT_2_ADDR_OFST)
#define FRAME_TIME_OUT_REG_1 (0xB06C)
#define PATTERN_WAIT_TIMER_2_LSB_REG (0xB15C)
#define FRAME_TIME_OUT_REG_2 (0xB070)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0xB160)
#define PATTERN_LOOPDEF_BASE (0xB080)
#define PATTERN_LOOP_3_ADDR_REG (0xB164)
#define PATTERN_LOOP_ADDR_WORD_OFST (0)
#define PATTERN_LOOP_ADDR_WORD_MSK (0x00000001 << PATTERN_LOOP_ADDR_WORD_OFST)
#define PATTERN_LOOP_ITERATION_WORD_OFST (1)
#define PATTERN_LOOP_ITERATION_WORD_MSK (0x00000001 << PATTERN_LOOP_ITERATION_WORD_OFST)
#define PATTERN_WAIT_ADDR_WORD_OFST (2)
#define PATTERN_WAIT_ADDR_WORD_MSK (0x00000001 << PATTERN_WAIT_ADDR_WORD_OFST)
#define PATTERN_WAIT_TIMER_LSB_WORD_OFST (3)
#define PATTERN_WAIT_TIMER_LSB_WORD_MSK (0x00000001 << PATTERN_WAIT_TIMER_LSB_WORD_OFST)
#define PATTERN_WAIT_TIMER_MSB_WORD_OFST (4)
#define PATTERN_WAIT_TIMER_MSB_WORD_MSK (0x00000001 << PATTERN_WAIT_TIMER_MSB_WORD_OFST)
#define PATTERN_LOOPDEF_NWORDS_OFST (5)
#define PATTERN_LOOPDEF_NWORDS_MSK (0x00000001 << PATTERN_LOOPDEF_NWORDS_OFST)
#define PATTERN_WAIT_ADDR_OFST (0)
#define PATTERN_WAIT_ADDR_MSK (0x00001fff << PATTERN_WAIT_ADDR_OFST)
#define PATTERN_LOOP_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_ADDR_STRT_OFST)
#define PATTERN_LOOP_ADDR_STP_OFST (16)
#define PATTERN_LOOP_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_ADDR_STP_OFST)
#define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_3_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_3_ADDR_STRT_OFST)
#define PATTERN_LOOP_3_ADDR_STP_OFST (16)
#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STP_OFST)
#define DBITFIFOCTRLREG (0xC000)
#define PATTERN_LOOP_3_ITERATION_REG (0xB168)
#define DBITRD_OFST (0)
#define DBITRD_MSK (0x00000001 << DBITRD_OFST)
#define DBITRST_OFST (1)
#define DBITRST_MSK (0x00000001 << DBITRST_OFST)
#define DBITFULL_OFST (2)
#define DBITFULL_MSK (0x00000001 << DBITFULL_OFST)
#define DBITEMPTY_OFST (3)
#define DBITEMPTY_MSK (0x00000001 << DBITEMPTY_OFST)
#define PATTERN_WAIT_3_ADDR_REG (0xB16C)
#define PATTERN_WAIT_3_ADDR_OFST (0)
#define PATTERN_WAIT_3_ADDR_MSK (0x00001fff << PATTERN_WAIT_3_ADDR_OFST)
#define PATTERN_WAIT_TIMER_3_LSB_REG (0xB170)
#define PATTERN_WAIT_TIMER_3_MSB_REG (0xB174)
#define PATTERN_LOOP_4_ADDR_REG (0xB178)
#define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_4_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_4_ADDR_STRT_OFST)
#define PATTERN_LOOP_4_ADDR_STP_OFST (16)
#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STP_OFST)
#define PATTERN_LOOP_4_ITERATION_REG (0xB17C)
#define PATTERN_WAIT_4_ADDR_REG (0xB180)
#define PATTERN_WAIT_4_ADDR_OFST (0)
#define PATTERN_WAIT_4_ADDR_MSK (0x00001fff << PATTERN_WAIT_4_ADDR_OFST)
#define PATTERN_WAIT_TIMER_4_LSB_REG (0xB184)
#define PATTERN_WAIT_TIMER_4_MSB_REG (0xB188)
#define PATTERN_LOOP_5_ADDR_REG (0xB18C)
#define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_5_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_5_ADDR_STRT_OFST)
#define PATTERN_LOOP_5_ADDR_STP_OFST (16)
#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STP_OFST)
#define PATTERN_LOOP_5_ITERATION_REG (0xB190)
#define PATTERN_WAIT_5_ADDR_REG (0xB194)
#define PATTERN_WAIT_5_ADDR_OFST (0)
#define PATTERN_WAIT_5_ADDR_MSK (0x00001fff << PATTERN_WAIT_5_ADDR_OFST)
#define PATTERN_WAIT_TIMER_5_LSB_REG (0xB198)
#define PATTERN_WAIT_TIMER_5_MSB_REG (0xB19C)
#define PINIOCTRLREG (0xB1A0)
#define DBITFIFOCTRLREG (0xB1A4)
#define DBITRD_OFST (0)
#define DBITRD_MSK (0x00000001 << DBITRD_OFST)
#define DBITRST_OFST (1)
#define DBITRST_MSK (0x00000001 << DBITRST_OFST)
#define DBITFULL_OFST (2)
#define DBITFULL_MSK (0x00000001 << DBITFULL_OFST)
#define DBITEMPTY_OFST (3)
#define DBITEMPTY_MSK (0x00000001 << DBITEMPTY_OFST)
#define DBITUNDERFLOW_OFST (4)
#define DBITUNDERFLOW_MSK (0x00000001 << DBITUNDERFLOW_OFST)
#define DBITOVERFLOW_OFST (5)
#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST)
#define DBITOVERFLOW_OFST (5)
#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST)
#define DBITFIFODATAREG1 (0xC004)
#define DBITFIFODATAREG1 (0xB1A8)
#define DBITFIFODATAREG2 (0xC008)
#define DBITFIFODATAREG2 (0xB1AC)
#define MATTERHORNSPIREG1 (0xC00C)
#define MATTERHORNSPIREG1 (0xB1B0)
#define MATTERHORNSPIREG2 (0xC010)
#define MATTERHORNSPIREG2 (0xB1B4)
#define MATTERHORNSPICTRL (0xC014)
#define MATTERHORNSPICTRL (0xB1B8)
#define CONFIGSTART_P_OFST (0)
#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST)
#define PERIPHERYRST_P_OFST (1)
#define PERIPHERYRST_P_MSK (0x00000001 << PERIPHERYRST_P_OFST)
#define STARTREAD_P_OFST (2)
#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST)
#define BUSY_OFST (3)
#define BUSY_MSK (0x00000001 << BUSY_OFST)
#define CONFIGSTART_P_OFST (0)
#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST)
#define PERIPHERYRST_P_OFST (1)
#define PERIPHERYRST_P_MSK (0x00000001 << PERIPHERYRST_P_OFST)
#define STARTREAD_P_OFST (2)
#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST)
#define BUSY_OFST (3)
#define BUSY_MSK (0x00000001 << BUSY_OFST)
#define READOUTFROMASIC_OFST (4)
#define READOUTFROMASIC_MSK (0x00000001 << READOUTFROMASIC_OFST)
#define TRANSCEIVERRXCTRL0REG1 (0xC100)
#define TRANSCEIVERRXCTRL0REG1 (0xB800)
#define TRANSCEIVERRXCTRL0REG2 (0xC104)
#define TRANSCEIVERRXCTRL0REG2 (0xB804)
#define TRANSCEIVERRXCTRL1REG1 (0xC108)
#define TRANSCEIVERRXCTRL1REG1 (0xB808)
#define TRANSCEIVERRXCTRL1REG2 (0xC10C)
#define TRANSCEIVERRXCTRL1REG2 (0xB80C)
#define TRANSCEIVERRXCTRL2REG (0xC110)
#define TRANSCEIVERRXCTRL2REG (0xB810)
#define TRANSCEIVERRXCTRL3REG (0xC114)
#define TRANSCEIVERRXCTRL3REG (0xB814)
#define TRANSCEIVERSTATUS (0xC118)
#define TRANSCEIVERSTATUS (0xB818)
#define LINKDOWNLATCHEDOUT_OFST (0)
#define LINKDOWNLATCHEDOUT_MSK (0x00000001 << LINKDOWNLATCHEDOUT_OFST)
#define TXUSERCLKACTIVE_OFST (1)
#define TXUSERCLKACTIVE_MSK (0x00000001 << TXUSERCLKACTIVE_OFST)
#define RXUSERCLKACTIVE_OFST (2)
#define RXUSERCLKACTIVE_MSK (0x00000001 << RXUSERCLKACTIVE_OFST)
#define RXCOMMADET_OFST (3)
#define RXCOMMADET_MSK (0x0000000f << RXCOMMADET_OFST)
#define RXBYTEREALIGN_OFST (7)
#define RXBYTEREALIGN_MSK (0x0000000f << RXBYTEREALIGN_OFST)
#define RXBYTEISALIGNED_OFST (11)
#define RXBYTEISALIGNED_MSK (0x0000000f << RXBYTEISALIGNED_OFST)
#define GTWIZRXCDRSTABLE_OFST (15)
#define GTWIZRXCDRSTABLE_MSK (0x00000001 << GTWIZRXCDRSTABLE_OFST)
#define RESETTXDONE_OFST (16)
#define RESETTXDONE_MSK (0x00000001 << RESETTXDONE_OFST)
#define RESETRXDONE_OFST (17)
#define RESETRXDONE_MSK (0x00000001 << RESETRXDONE_OFST)
#define RXPMARESETDONE_OFST (18)
#define RXPMARESETDONE_MSK (0x0000000f << RXPMARESETDONE_OFST)
#define TXPMARESETDONE_OFST (22)
#define TXPMARESETDONE_MSK (0x0000000f << TXPMARESETDONE_OFST)
#define GTTPOWERGOOD_OFST (26)
#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
#define TXUSERCLKACTIVE_OFST (1)
#define TXUSERCLKACTIVE_MSK (0x00000001 << TXUSERCLKACTIVE_OFST)
#define RXUSERCLKACTIVE_OFST (2)
#define RXUSERCLKACTIVE_MSK (0x00000001 << RXUSERCLKACTIVE_OFST)
#define RXCOMMADET_OFST (3)
#define RXCOMMADET_MSK (0x0000000f << RXCOMMADET_OFST)
#define RXBYTEREALIGN_OFST (7)
#define RXBYTEREALIGN_MSK (0x0000000f << RXBYTEREALIGN_OFST)
#define RXBYTEISALIGNED_OFST (11)
#define RXBYTEISALIGNED_MSK (0x0000000f << RXBYTEISALIGNED_OFST)
#define GTWIZRXCDRSTABLE_OFST (15)
#define GTWIZRXCDRSTABLE_MSK (0x00000001 << GTWIZRXCDRSTABLE_OFST)
#define RESETTXDONE_OFST (16)
#define RESETTXDONE_MSK (0x00000001 << RESETTXDONE_OFST)
#define RESETRXDONE_OFST (17)
#define RESETRXDONE_MSK (0x00000001 << RESETRXDONE_OFST)
#define RXPMARESETDONE_OFST (18)
#define RXPMARESETDONE_MSK (0x0000000f << RXPMARESETDONE_OFST)
#define TXPMARESETDONE_OFST (22)
#define TXPMARESETDONE_MSK (0x0000000f << TXPMARESETDONE_OFST)
#define GTTPOWERGOOD_OFST (26)
#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
#define TRANSCEIVERSTATUS2 (0xC11C)
#define TRANSCEIVERSTATUS2 (0xB81C)
#define RXLOCKED_OFST (0)
#define RXLOCKED_MSK (0x0000000f << RXLOCKED_OFST)
#define TRANSCEIVERCONTROL (0xC120)
#define TRANSCEIVERCONTROL (0xB820)
#define GTWIZRESETALL_OFST (0)
#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST)
#define GTWIZRESETALL_OFST (0)
#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST)
#define RESETTXPLLANDDATAPATH_OFST (1)
#define RESETTXPLLANDDATAPATH_MSK (0x00000001 << RESETTXPLLANDDATAPATH_OFST)
#define RESETTXDATAPATHIN_OFST (2)
#define RESETTXDATAPATHIN_MSK (0x00000001 << RESETTXDATAPATHIN_OFST)
#define RESETTXDATAPATHIN_OFST (2)
#define RESETTXDATAPATHIN_MSK (0x00000001 << RESETTXDATAPATHIN_OFST)
#define RESETRXPLLANDDATAPATH_OFST (3)
#define RESETRXPLLANDDATAPATH_MSK (0x00000001 << RESETRXPLLANDDATAPATH_OFST)
#define RESETRXDATAPATHIN_OFST (4)
#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST)
#define RXPOLARITY_OFST (5)
#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST)
#define RXERRORCNTRESET_OFST (9)
#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST)
#define RXMSBLSBINVERT_OFST (13)
#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
#define RESETRXDATAPATHIN_OFST (4)
#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST)
#define RXPOLARITY_OFST (5)
#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST)
#define RXERRORCNTRESET_OFST (9)
#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST)
#define RXMSBLSBINVERT_OFST (13)
#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
#define TRANSCEIVERERRCNT_REG0 (0xC124)
#define TRANSCEIVERERRCNT_REG0 (0xB824)
#define TRANSCEIVERERRCNT_REG1 (0xC128)
#define TRANSCEIVERERRCNT_REG1 (0xB828)
#define TRANSCEIVERERRCNT_REG2 (0xC12C)
#define TRANSCEIVERERRCNT_REG2 (0xB82C)
#define TRANSCEIVERERRCNT_REG3 (0xC130)
#define TRANSCEIVERERRCNT_REG3 (0xB830)
#define TRANSCEIVERALIGNCNT_REG0 (0xC134)
#define TRANSCEIVERALIGNCNT_REG0 (0xB834)
#define RXALIGNCNTCH0_OFST (0)
#define RXALIGNCNTCH0_MSK (0x0000ffff << RXALIGNCNTCH0_OFST)
#define TRANSCEIVERALIGNCNT_REG1 (0xC138)
#define TRANSCEIVERALIGNCNT_REG1 (0xB838)
#define RXALIGNCNTCH1_OFST (0)
#define RXALIGNCNTCH1_MSK (0x0000ffff << RXALIGNCNTCH1_OFST)
#define TRANSCEIVERALIGNCNT_REG2 (0xC13C)
#define TRANSCEIVERALIGNCNT_REG2 (0xB83C)
#define RXALIGNCNTCH2_OFST (0)
#define RXALIGNCNTCH2_MSK (0x0000ffff << RXALIGNCNTCH2_OFST)
#define TRANSCEIVERALIGNCNT_REG3 (0xC140)
#define TRANSCEIVERALIGNCNT_REG3 (0xB840)
#define RXALIGNCNTCH3_OFST (0)
#define RXALIGNCNTCH3_MSK (0x0000ffff << RXALIGNCNTCH3_OFST)
#define TRANSCEIVERLASTWORD_REG0 (0xC144)
#define TRANSCEIVERLASTWORD_REG0 (0xB844)
#define RXDATACH0_OFST (0)
#define RXDATACH0_MSK (0x0000ffff << RXDATACH0_OFST)
#define TRANSCEIVERLASTWORD_REG1 (0xC148)
#define TRANSCEIVERLASTWORD_REG1 (0xB848)
#define RXDATACH1_OFST (0)
#define RXDATACH1_MSK (0x0000ffff << RXDATACH1_OFST)
#define TRANSCEIVERLASTWORD_REG2 (0xC14C)
#define TRANSCEIVERLASTWORD_REG2 (0xB84C)
#define RXDATACH2_OFST (0)
#define RXDATACH2_MSK (0x0000ffff << RXDATACH2_OFST)
#define TRANSCEIVERLASTWORD_REG3 (0xC150)
#define TRANSCEIVERLASTWORD_REG3 (0xB850)
#define RXDATACH3_OFST (0)
#define RXDATACH3_MSK (0x0000ffff << RXDATACH3_OFST)
// ----------------------------------------------------
// TODO: fix these in the firmware reg generator:
// ----------------------------------------------------:
#define DELAY_OUT_REG_1 (0xB054)
#define DELAY_OUT_REG_2 (0xB058)
#define CYCLES_OUT_REG_1 (0xB05C)
#define CYCLES_OUT_REG_2 (0xB060)
#define FRAMES_OUT_REG_1 (0xB064)
#define FRAMES_OUT_REG_2 (0xB068)
#define PERIOD_OUT_REG_1 (0xB06C)
#define PERIOD_OUT_REG_2 (0xB070)
// clang-format on

View File

@@ -1,24 +1,24 @@
# Prepare MH02 configuration
reg 0xC00C 0x00040041
reg 0xC010 0x01200004
reg 0xB1B0 0x00000041
reg 0xB1B4 0x01200004
# configure Matterhorn SPI
setbit 0xC014 0
setbit 0xB1B8 0
# wait till config is done
pollbit 0xC014 3 0
pollbit 0xB1B8 3 0
# reset transceiver
reg 0xC120 0x0
reg 0xC120 0x1
reg 0xC120 0x0
reg 0xB820 0x0
reg 0xB820 0x1
reg 0xB820 0x0
# set MSB LSB inversions and polarity for transceiver
reg 0xC120 0x1e0
reg 0xB820 0x61e0
# Enable MH02 PLL clock
pattern enable_clock_pattern.pyat
# start the flow
setbit 0xB030 0
clearbit 0xB030 0
setbit 0xB004 0
clearbit 0xB004 0
sleep 1

View File

@@ -1,29 +1,30 @@
# turn off clock
clearbit 0xB018 15
setbit 0xB010 15
setbit 0xB1B0 16
setbit 0xB1B8 0
sleep 1
# reset Matterhorn periphery
setbit 0xC014 1
setbit 0xB1B8 1
sleep 1
# turn on clock
clearbit 0xB010 15
clearbit 0xB1B0 16
setbit 0xB1B8 0
sleep 1
# reset rx transceiver datapath
setbit 0xC120 4
setbit 0xB820 4
sleep 1
# reset 8b10b counters
setbit 0xC120 9
setbit 0xC120 10
setbit 0xC120 11
setbit 0xC120 12
setbit 0xB820 9
setbit 0xB820 10
setbit 0xB820 11
setbit 0xB820 12
sleep 1
clearbit 0xC120 9
clearbit 0xC120 10
clearbit 0xB820 9
clearbit 0xB820 10
# reset buffer fifos
reg 0x9024 0xFFFFFFFF

View File

@@ -9,7 +9,6 @@
#include "sls/versionAPI.h"
#include "LTC2620_Driver.h"
#include "XILINX_PLL.h"
#include "loadPattern.h"
#ifdef VIRTUAL
@@ -40,7 +39,6 @@ char initErrorMessage[MAX_STR_LENGTH];
int detPos[2] = {0, 0};
uint32_t clkFrequency[NUM_CLOCKS] = {};
int chipConfigured = 0;
int analogEnable = 0;
int digitalEnable = 0;
@@ -375,10 +373,6 @@ void setupDetector() {
LOG(logINFO, ("Setting up Server for 1 Xilinx Chip Test Board\n"));
// default variables
clkFrequency[RUN_CLK] = DEFAULT_RUN_CLK;
clkFrequency[ADC_CLK] = DEFAULT_ADC_CLK;
clkFrequency[SYNC_CLK] = DEFAULT_SYNC_CLK;
clkFrequency[DBIT_CLK] = DEFAULT_DBIT_CLK;
chipConfigured = 0;
analogEnable = 0;
digitalEnable = 0;
@@ -440,18 +434,14 @@ void cleanFifos() {
#ifdef VIRTUAL
return;
#endif
uint32_t t_enable_mask = getTransceiverEnableMask();
uint32_t tclean_msk =
((t_enable_mask << X_FIFO_CLEAN_OFST) & X_FIFO_CLEAN_MSK);
uint32_t t_before_reg = bus_r(X_FIFO_CLEAN_REG);
LOG(logINFO, ("Clearing Acquisition Fifos\n"));
bus_w(A_FIFO_CLEAN_REG, bus_r(A_FIFO_CLEAN_REG) | BIT32_MSK);
bus_w(D_FIFO_CLEAN_REG, bus_r(D_FIFO_CLEAN_REG) | D_FIFO_CLEAN_MSK);
bus_w(X_FIFO_CLEAN_REG, t_before_reg | tclean_msk);
bus_w(X_FIFO_CLEAN_REG, bus_r(X_FIFO_CLEAN_REG) | X_FIFO_CLEAN_MSK);
bus_w(A_FIFO_CLEAN_REG, 0);
bus_w(D_FIFO_CLEAN_REG, bus_r(D_FIFO_CLEAN_REG) & ~D_FIFO_CLEAN_MSK);
bus_w(X_FIFO_CLEAN_REG, t_before_reg);
bus_w(X_FIFO_CLEAN_REG, bus_r(X_FIFO_CLEAN_REG) & ~X_FIFO_CLEAN_MSK);
}
void resetFlow() {
@@ -1068,12 +1058,12 @@ int setPeriod(int64_t val) {
return FAIL;
}
LOG(logINFO, ("Setting period %lld ns\n", (long long int)val));
val *= (NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
val *= (1E-3 * RUN_CLK);
setU64BitReg(val, PERIOD_IN_REG_1, PERIOD_IN_REG_2);
// validate for tolerance
int64_t retval = getPeriod();
val /= (NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
val /= (1E-3 * RUN_CLK);
if (val != retval) {
return FAIL;
}
@@ -1081,8 +1071,7 @@ int setPeriod(int64_t val) {
}
int64_t getPeriod() {
return getU64BitReg(PERIOD_IN_REG_1, PERIOD_IN_REG_2) /
(NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
return getU64BitReg(PERIOD_IN_REG_1, PERIOD_IN_REG_2) / (1E-3 * RUN_CLK);
}
int setDelayAfterTrigger(int64_t val) {
@@ -1091,12 +1080,12 @@ int setDelayAfterTrigger(int64_t val) {
return FAIL;
}
LOG(logINFO, ("Setting delay after trigger %ld ns\n", val));
val *= (NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
val *= (1E-3 * RUN_CLK);
setU64BitReg(val, DELAY_IN_REG_1, DELAY_IN_REG_2);
// validate for tolerance
int64_t retval = getDelayAfterTrigger();
val /= (NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
val /= (1E-3 * RUN_CLK);
if (val != retval) {
return FAIL;
}
@@ -1104,8 +1093,7 @@ int setDelayAfterTrigger(int64_t val) {
}
int64_t getDelayAfterTrigger() {
return getU64BitReg(DELAY_IN_REG_1, DELAY_IN_REG_2) /
(NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
return getU64BitReg(DELAY_IN_REG_1, DELAY_IN_REG_2) / (1E-3 * RUN_CLK);
}
int64_t getNumFramesLeft() {
@@ -1117,13 +1105,11 @@ int64_t getNumTriggersLeft() {
}
int64_t getDelayAfterTriggerLeft() {
return getU64BitReg(DELAY_OUT_REG_1, DELAY_OUT_REG_2) /
(NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
return getU64BitReg(DELAY_OUT_REG_1, DELAY_OUT_REG_2) / (1E-3 * RUN_CLK);
}
int64_t getPeriodLeft() {
return getU64BitReg(PERIOD_OUT_REG_1, PERIOD_OUT_REG_2) /
(NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
return getU64BitReg(PERIOD_OUT_REG_1, PERIOD_OUT_REG_2) / (1E-3 * RUN_CLK);
}
int64_t getFramesFromStart() {
@@ -1133,12 +1119,12 @@ int64_t getFramesFromStart() {
int64_t getActualTime() {
return getU64BitReg(TIME_FROM_START_OUT_REG_1, TIME_FROM_START_OUT_REG_2) /
(NS_TO_CLK_CYCLE * clkFrequency[SYNC_CLK]);
(1E-3 * TICK_CLK);
}
int64_t getMeasurementTime() {
return getU64BitReg(FRAME_TIME_OUT_REG_1, FRAME_TIME_OUT_REG_2) /
(NS_TO_CLK_CYCLE * clkFrequency[SYNC_CLK]);
(1E-3 * TICK_CLK);
}
/* parameters - dac, adc, hv */
@@ -1205,26 +1191,6 @@ void setVLimit(int l) {
vLimit = l;
}
int getBitOffsetFromDACIndex(enum DACINDEX ind) {
switch (ind) {
case D_PWR_IO:
return POWER_VIO_OFST;
case D_PWR_A:
return POWER_VCC_A_OFST;
case D_PWR_B:
return POWER_VCC_B_OFST;
case D_PWR_C:
return POWER_VCC_C_OFST;
case D_PWR_D:
return POWER_VCC_D_OFST;
default:
LOG(logERROR,
("DAC index %d is not defined to get offset in ctrl register\n",
ind));
return -1;
}
}
int isPowerValid(enum DACINDEX ind, int val) {
char *powerNames[] = {PWR_NAMES};
int pwrIndex = (int)(ind - D_PWR_D);
@@ -1247,23 +1213,10 @@ int isPowerValid(enum DACINDEX ind, int val) {
}
int getPower(enum DACINDEX ind) {
// get bit offset in ctrl register
int bitOffset = getBitOffsetFromDACIndex(ind);
if (bitOffset == -1) {
return -1;
}
// powered enable off
{
uint32_t addr = CTRL_REG;
uint32_t mask = (1 << bitOffset);
if (!(bus_r(addr) & mask))
return 0;
}
char *powerNames[] = {PWR_NAMES};
int pwrIndex = (int)(ind - D_PWR_D);
// check dac value
// not set yet
if (dacValues[ind] == -1) {
LOG(logERROR,
@@ -1273,8 +1226,7 @@ int getPower(enum DACINDEX ind) {
// dac powered off
if (dacValues[ind] == LTC2620_D_GetPowerDownValue()) {
LOG(logWARNING, ("Power V%s enabled, but voltage is at minimum or 0.\n",
powerNames[pwrIndex]));
LOG(logWARNING, ("Power V%s is powered down\n", powerNames[pwrIndex]));
return LTC2620_D_GetPowerDownValue();
}
@@ -1288,43 +1240,26 @@ int getPower(enum DACINDEX ind) {
}
void setPower(enum DACINDEX ind, int val) {
// validate index and get bit offset in ctrl register
int bitOffset = getBitOffsetFromDACIndex(ind);
if (bitOffset == -1) {
return;
}
uint32_t addr = CTRL_REG;
uint32_t mask = (1 << bitOffset);
if (val == -1)
return;
char *powerNames[] = {PWR_NAMES};
int pwrIndex = (int)(ind - D_PWR_D);
LOG(logINFO, ("Setting Power V%s to %d mV\n", powerNames[pwrIndex], val));
// validate value (already checked at tcp (funcs.c))
if (!isPowerValid(ind, val)) {
LOG(logERROR, ("Invalid power value for V%s: %d mV\n",
powerNames[pwrIndex], val));
return;
}
// Switch off power enable
LOG(logDEBUG1, ("Switching off power enable\n"));
bus_w(addr, bus_r(addr) & ~(mask));
// power down dac
LOG(logINFO, ("\tPowering down V%d\n", powerNames[pwrIndex]));
setDAC(ind, LTC2620_D_GetPowerDownValue(), 0);
if (val == LTC2620_D_GetPowerDownValue()) {
LOG(logINFO, ("\tPowering down V%d\n", powerNames[pwrIndex]));
setDAC(ind, LTC2620_D_GetPowerDownValue(), 0);
}
//(power off is anyway done with power enable)
if (val == 0)
val = LTC2620_D_GetPowerDownValue();
// set dac
else if (val >= 0) {
LOG(logINFO,
("Setting Power V%s to %d mV\n", powerNames[pwrIndex], val));
// convert voltage to dac (power off is anyway done with power enable)
if (val != LTC2620_D_GetPowerDownValue()) {
// validate value (already checked at tcp (funcs.c))
if (!isPowerValid(ind, val)) {
return;
}
// convert voltage to dac
int dacval = -1;
if (ConvertToDifferentRange(
POWER_RGLTR_MIN, POWER_RGLTR_MAX, LTC2620_D_GetMaxInput(),
@@ -1341,12 +1276,6 @@ void setPower(enum DACINDEX ind, int val) {
LOG(logINFO, ("Setting Power V%s: %d mV (%d dac)\n",
powerNames[pwrIndex], val, dacval));
setDAC(ind, dacval, 0);
// if valid, enable power
if (dacval >= 0) {
LOG(logDEBUG1, ("Switching on power enable\n"));
bus_w(addr, bus_r(addr) | mask);
}
}
}
@@ -1700,7 +1629,7 @@ int stopStateMachine() {
#endif
// stop state machine
bus_w(FLOW_CONTROL_REG, bus_r(FLOW_CONTROL_REG) | STOP_F_MSK);
cleanFifos();
return OK;
}
@@ -1849,37 +1778,3 @@ void getNumberOfChannels(int *nchanx, int *nchany) {
int getNumberOfChips() { return NCHIP; }
int getNumberOfDACs() { return NDAC; }
int getNumberOfChannelsPerChip() { return NCHAN; }
int setFrequency(enum CLKINDEX ind, int val) {
if (ind < 0 || ind >= NUM_CLOCKS) {
LOG(logERROR, ("Unknown clock index %d to set frequency\n", ind));
return FAIL;
}
if (val <= 0) {
return FAIL;
}
char *clock_names[] = {CLK_NAMES};
LOG(logINFO, ("\tSetting %s clock (%d) frequency to %d kHz\n",
clock_names[ind], ind, val));
if (XILINX_PLL_setFrequency(ind, val) == FAIL) {
LOG(logERROR, ("\tCould not set %s clock (%d) frequency to %d kHz\n",
clock_names[ind], ind, val));
return FAIL;
}
clkFrequency[ind] = val;
// TODO later: connect setPhase as phase gets reset on freq change
return OK;
}
int getFrequency(enum CLKINDEX ind) {
if (ind < 0 || ind >= NUM_CLOCKS) {
LOG(logERROR, ("Unknown clock index %d to get frequency\n", ind));
return -1;
}
#ifndef VIRTUAL
clkFrequency[ind] = XILINX_PLL_getFrequency(ind);
#endif
return clkFrequency[ind];
}

View File

@@ -71,6 +71,12 @@
#define POWER_RGLTR_MAX (2661)
#define VIO_MIN_MV (1200) // for fpga to function
#define TICK_CLK (20) // MHz (trig_timeFromStart, frametime, timeFromStart)
#define RUN_CLK \
(100) // MHz (framesFromStart, c_swTrigger, run, waitForTrigger, starting,
// acquiring, waitForPeriod, internalStop, c_framesFromSTart_reset,
// s_start, c_stop, triggerEnable, period, frames, cycles, delay)
/* Defines in the Firmware */
#define WAIT_TIME_PATTERN_READ (10)
#define WAIT_TIME_OUT_0US_TIMES (35000) // 2s
@@ -152,12 +158,3 @@ typedef struct udp_header_struct {
#define IP_HEADER_SIZE (20)
#define UDP_IP_HEADER_LENGTH_BYTES (28)
enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "sync", "dbit"
#define DEFAULT_RUN_CLK (20000) // 20 MHz
#define DEFAULT_ADC_CLK (100000) // 100 MHz
#define DEFAULT_SYNC_CLK (20000) // 20 MHz
#define DEFAULT_DBIT_CLK (100000) // 100 MHz
#define NS_TO_CLK_CYCLE (1E-6) // ns to kHz

View File

@@ -28,11 +28,12 @@ target_link_libraries(slsDetectorObject
PUBLIC
slsProjectOptions
slsSupportStatic
pthread
rt
PRIVATE
slsProjectWarnings
)
set(DETECTOR_LIBRARY_TARGETS slsDetectorObject)
@@ -97,7 +98,8 @@ if(SLS_USE_TEXTCLIENT)
add_executable(${val1} src/CmdApp.cpp)
target_link_libraries(${val1}
slsDetectorStatic
slsDetectorStatic
pthread
)
SET_SOURCE_FILES_PROPERTIES( src/Caller.cpp PROPERTIES COMPILE_FLAGS "-Wno-unused-variable -Wno-unused-but-set-variable")

View File

@@ -74,11 +74,6 @@ class Caller {
static void EmptyDataCallBack(detectorData *data, uint64_t frameIndex,
uint32_t subFrameIndex, void *this_pointer);
std::string bitoperations(int action);
RegisterAddress parseAddress(const std::string &saddr) const;
bool parseValidate();
BitAddress parseBitAddress() const;
FunctionMap functions{
{"list", &Caller::list},

View File

@@ -80,7 +80,7 @@ _sd() {
local IS_PATH=0
local SLS_COMMANDS=" acquire activate adcclk adcenable adcenable10g adcindex adcinvert adclist adcname adcphase adcpipeline adcreg adcvpp apulse asamples autocompdisable badchannels blockingtrigger burstmode burstperiod bursts burstsl bustest cdsgain chipversion clearbit clearbusy clientversion clkdiv clkfreq clkphase collectionmode column compdisabletime confadc config configtransceiver counters currentsource dac dacindex daclist dacname dacvalues datastream dbitclk dbitphase dbitpipeline defaultdac defaultpattern define_bit define_reg definelist_bit definelist_reg delay delayl detectorserverversion detsize diodelay dpulse dr drlist dsamples execcommand exptime exptime1 exptime2 exptime3 extrastoragecells extsampling extsamplingsrc extsig fformat filtercells filterresistor findex firmwaretest firmwareversion fliprows flowcontrol10g fmaster fname foverwrite fpath framecounter frames framesl frametime free fwrite gaincaps gainmode gappixels gatedelay gatedelay1 gatedelay2 gatedelay3 gates getbit hardwareversion highvoltage hostname im_a im_b im_c im_d im_io imagetest initialchecks inj_ch interpolation interruptsubframe kernelversion lastclient led lock master maxadcphaseshift maxclkphaseshift maxdbitphaseshift measuredperiod measuredsubperiod moduleid nextframenumber nmod numinterfaces overflow packageversion parallel parameters partialreset patfname patioctrl patlimits patloop patloop0 patloop1 patloop2 patmask patnloop patnloop0 patnloop1 patnloop2 patsetbit pattern patternstart patwait patwait0 patwait1 patwait2 patwaittime patwaittime0 patwaittime1 patwaittime2 patword pedestalmode period periodl polarity port powerchip powerindex powerlist powername powervalues programfpga pulse pulsechip pulsenmove pumpprobe quad ratecorr readnrows readout readoutspeed readoutspeedlist rebootcontroller reg resetdacs resetfpga romode row runclk runtime rx_arping rx_clearroi rx_dbitlist rx_dbitoffset rx_dbitreorder rx_discardpolicy rx_fifodepth rx_frameindex rx_framescaught rx_framesperfile rx_hostname rx_jsonaddheader rx_jsonpara rx_lastclient rx_lock rx_missingpackets rx_padding rx_printconfig rx_realudpsocksize rx_roi rx_silent rx_start rx_status rx_stop rx_tcpport rx_threads rx_udpsocksize rx_version rx_zmqfreq rx_zmqhwm rx_zmqip rx_zmqport rx_zmqstartfnum rx_zmqstream samples savepattern scan scanerrmsg selinterface serialnumber setbit settings settingslist settingspath signalindex signallist signalname sleep slowadc slowadcindex slowadclist slowadcname slowadcvalues start status stop stopport storagecell_delay storagecell_start subdeadtime subexptime sync syncclk temp_10ge temp_adc temp_control temp_dcdc temp_event temp_fpga temp_fpgaext temp_fpgafl temp_fpgafr temp_slowadc temp_sodl temp_sodr temp_threshold templist tempvalues tengiga threshold thresholdnotb timing timing_info_decoder timinglist timingsource top transceiverenable trigger triggers triggersl trimbits trimen trimval tsamples txdelay txdelay_frame txdelay_left txdelay_right type udp_cleardst udp_dstip udp_dstip2 udp_dstlist udp_dstmac udp_dstmac2 udp_dstport udp_dstport2 udp_firstdst udp_numdst udp_reconfigure udp_srcip udp_srcip2 udp_srcmac udp_srcmac2 udp_validate update updatedetectorserver updatekernel updatemode user v_a v_b v_c v_chip v_d v_io v_limit vchip_comp_adc vchip_comp_fe vchip_cs vchip_opa_1st vchip_opa_fd vchip_ref_comp_fe versions veto vetoalg vetofile vetophoton vetoref vetostream virtual vm_a vm_b vm_c vm_d vm_io zmqhwm zmqip zmqport "
local SLS_COMMANDS=" acquire activate adcclk adcenable adcenable10g adcindex adcinvert adclist adcname adcphase adcpipeline adcreg adcvpp apulse asamples autocompdisable badchannels blockingtrigger burstmode burstperiod bursts burstsl bustest cdsgain chipversion clearbit clearbusy clientversion clkdiv clkfreq clkphase collectionmode column compdisabletime confadc config configtransceiver counters currentsource dac dacindex daclist dacname dacvalues datastream dbitclk dbitphase dbitpipeline defaultdac defaultpattern delay delayl detectorserverversion detsize diodelay dpulse dr drlist dsamples execcommand exptime exptime1 exptime2 exptime3 extrastoragecells extsampling extsamplingsrc extsig fformat filtercells filterresistor findex firmwaretest firmwareversion fliprows flowcontrol10g fmaster fname foverwrite fpath framecounter frames framesl frametime free fwrite gaincaps gainmode gappixels gatedelay gatedelay1 gatedelay2 gatedelay3 gates getbit hardwareversion highvoltage hostname im_a im_b im_c im_d im_io imagetest initialchecks inj_ch interpolation interruptsubframe kernelversion lastclient led lock master maxadcphaseshift maxclkphaseshift maxdbitphaseshift measuredperiod measuredsubperiod moduleid nextframenumber nmod numinterfaces overflow packageversion parallel parameters partialreset patfname patioctrl patlimits patloop patloop0 patloop1 patloop2 patmask patnloop patnloop0 patnloop1 patnloop2 patsetbit pattern patternstart patwait patwait0 patwait1 patwait2 patwaittime patwaittime0 patwaittime1 patwaittime2 patword pedestalmode period periodl polarity port powerchip powerindex powerlist powername powervalues programfpga pulse pulsechip pulsenmove pumpprobe quad ratecorr readnrows readout readoutspeed readoutspeedlist rebootcontroller reg resetdacs resetfpga romode row runclk runtime rx_arping rx_clearroi rx_dbitlist rx_dbitoffset rx_dbitreorder rx_discardpolicy rx_fifodepth rx_frameindex rx_framescaught rx_framesperfile rx_hostname rx_jsonaddheader rx_jsonpara rx_lastclient rx_lock rx_missingpackets rx_padding rx_printconfig rx_realudpsocksize rx_roi rx_silent rx_start rx_status rx_stop rx_tcpport rx_threads rx_udpsocksize rx_version rx_zmqfreq rx_zmqhwm rx_zmqip rx_zmqport rx_zmqstartfnum rx_zmqstream samples savepattern scan scanerrmsg selinterface serialnumber setbit settings settingslist settingspath signalindex signallist signalname sleep slowadc slowadcindex slowadclist slowadcname slowadcvalues start status stop stopport storagecell_delay storagecell_start subdeadtime subexptime sync syncclk temp_10ge temp_adc temp_control temp_dcdc temp_event temp_fpga temp_fpgaext temp_fpgafl temp_fpgafr temp_slowadc temp_sodl temp_sodr temp_threshold templist tempvalues tengiga threshold thresholdnotb timing timing_info_decoder timinglist timingsource top transceiverenable trigger triggers triggersl trimbits trimen trimval tsamples txdelay txdelay_frame txdelay_left txdelay_right type udp_cleardst udp_dstip udp_dstip2 udp_dstlist udp_dstmac udp_dstmac2 udp_dstport udp_dstport2 udp_firstdst udp_numdst udp_reconfigure udp_srcip udp_srcip2 udp_srcmac udp_srcmac2 udp_validate update updatedetectorserver updatekernel updatemode user v_a v_b v_c v_chip v_d v_io v_limit vchip_comp_adc vchip_comp_fe vchip_cs vchip_opa_1st vchip_opa_fd vchip_ref_comp_fe versions veto vetoalg vetofile vetophoton vetoref vetostream virtual vm_a vm_b vm_c vm_d vm_io zmqhwm zmqip zmqport "
__acquire() {
FCN_RETURN=""
return 0
@@ -682,54 +682,6 @@ fi
fi
return 0
}
__define_bit() {
FCN_RETURN=""
if [[ ${IS_GET} -eq 1 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN=""
fi
if [[ "${cword}" == "3" ]]; then
FCN_RETURN=""
fi
fi
if [[ ${IS_GET} -eq 0 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN=""
fi
if [[ "${cword}" == "3" ]]; then
FCN_RETURN=""
fi
if [[ "${cword}" == "4" ]]; then
FCN_RETURN=""
fi
fi
return 0
}
__define_reg() {
FCN_RETURN=""
if [[ ${IS_GET} -eq 1 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN=""
fi
fi
if [[ ${IS_GET} -eq 0 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN=""
fi
if [[ "${cword}" == "3" ]]; then
FCN_RETURN=""
fi
fi
return 0
}
__definelist_bit() {
FCN_RETURN=""
return 0
}
__definelist_reg() {
FCN_RETURN=""
return 0
}
__delay() {
FCN_RETURN=""
if [[ ${IS_GET} -eq 1 ]]; then

View File

@@ -4,7 +4,7 @@
_sd() {
local SLS_COMMANDS=" acquire activate adcclk adcenable adcenable10g adcindex adcinvert adclist adcname adcphase adcpipeline adcreg adcvpp apulse asamples autocompdisable badchannels blockingtrigger burstmode burstperiod bursts burstsl bustest cdsgain chipversion clearbit clearbusy clientversion clkdiv clkfreq clkphase collectionmode column compdisabletime confadc config configtransceiver counters currentsource dac dacindex daclist dacname dacvalues datastream dbitclk dbitphase dbitpipeline defaultdac defaultpattern define_bit define_reg definelist_bit definelist_reg delay delayl detectorserverversion detsize diodelay dpulse dr drlist dsamples execcommand exptime exptime1 exptime2 exptime3 extrastoragecells extsampling extsamplingsrc extsig fformat filtercells filterresistor findex firmwaretest firmwareversion fliprows flowcontrol10g fmaster fname foverwrite fpath framecounter frames framesl frametime free fwrite gaincaps gainmode gappixels gatedelay gatedelay1 gatedelay2 gatedelay3 gates getbit hardwareversion highvoltage hostname im_a im_b im_c im_d im_io imagetest initialchecks inj_ch interpolation interruptsubframe kernelversion lastclient led lock master maxadcphaseshift maxclkphaseshift maxdbitphaseshift measuredperiod measuredsubperiod moduleid nextframenumber nmod numinterfaces overflow packageversion parallel parameters partialreset patfname patioctrl patlimits patloop patloop0 patloop1 patloop2 patmask patnloop patnloop0 patnloop1 patnloop2 patsetbit pattern patternstart patwait patwait0 patwait1 patwait2 patwaittime patwaittime0 patwaittime1 patwaittime2 patword pedestalmode period periodl polarity port powerchip powerindex powerlist powername powervalues programfpga pulse pulsechip pulsenmove pumpprobe quad ratecorr readnrows readout readoutspeed readoutspeedlist rebootcontroller reg resetdacs resetfpga romode row runclk runtime rx_arping rx_clearroi rx_dbitlist rx_dbitoffset rx_dbitreorder rx_discardpolicy rx_fifodepth rx_frameindex rx_framescaught rx_framesperfile rx_hostname rx_jsonaddheader rx_jsonpara rx_lastclient rx_lock rx_missingpackets rx_padding rx_printconfig rx_realudpsocksize rx_roi rx_silent rx_start rx_status rx_stop rx_tcpport rx_threads rx_udpsocksize rx_version rx_zmqfreq rx_zmqhwm rx_zmqip rx_zmqport rx_zmqstartfnum rx_zmqstream samples savepattern scan scanerrmsg selinterface serialnumber setbit settings settingslist settingspath signalindex signallist signalname sleep slowadc slowadcindex slowadclist slowadcname slowadcvalues start status stop stopport storagecell_delay storagecell_start subdeadtime subexptime sync syncclk temp_10ge temp_adc temp_control temp_dcdc temp_event temp_fpga temp_fpgaext temp_fpgafl temp_fpgafr temp_slowadc temp_sodl temp_sodr temp_threshold templist tempvalues tengiga threshold thresholdnotb timing timing_info_decoder timinglist timingsource top transceiverenable trigger triggers triggersl trimbits trimen trimval tsamples txdelay txdelay_frame txdelay_left txdelay_right type udp_cleardst udp_dstip udp_dstip2 udp_dstlist udp_dstmac udp_dstmac2 udp_dstport udp_dstport2 udp_firstdst udp_numdst udp_reconfigure udp_srcip udp_srcip2 udp_srcmac udp_srcmac2 udp_validate update updatedetectorserver updatekernel updatemode user v_a v_b v_c v_chip v_d v_io v_limit vchip_comp_adc vchip_comp_fe vchip_cs vchip_opa_1st vchip_opa_fd vchip_ref_comp_fe versions veto vetoalg vetofile vetophoton vetoref vetostream virtual vm_a vm_b vm_c vm_d vm_io zmqhwm zmqip zmqport "
local SLS_COMMANDS=" acquire activate adcclk adcenable adcenable10g adcindex adcinvert adclist adcname adcphase adcpipeline adcreg adcvpp apulse asamples autocompdisable badchannels blockingtrigger burstmode burstperiod bursts burstsl bustest cdsgain chipversion clearbit clearbusy clientversion clkdiv clkfreq clkphase collectionmode column compdisabletime confadc config configtransceiver counters currentsource dac dacindex daclist dacname dacvalues datastream dbitclk dbitphase dbitpipeline defaultdac defaultpattern delay delayl detectorserverversion detsize diodelay dpulse dr drlist dsamples execcommand exptime exptime1 exptime2 exptime3 extrastoragecells extsampling extsamplingsrc extsig fformat filtercells filterresistor findex firmwaretest firmwareversion fliprows flowcontrol10g fmaster fname foverwrite fpath framecounter frames framesl frametime free fwrite gaincaps gainmode gappixels gatedelay gatedelay1 gatedelay2 gatedelay3 gates getbit hardwareversion highvoltage hostname im_a im_b im_c im_d im_io imagetest initialchecks inj_ch interpolation interruptsubframe kernelversion lastclient led lock master maxadcphaseshift maxclkphaseshift maxdbitphaseshift measuredperiod measuredsubperiod moduleid nextframenumber nmod numinterfaces overflow packageversion parallel parameters partialreset patfname patioctrl patlimits patloop patloop0 patloop1 patloop2 patmask patnloop patnloop0 patnloop1 patnloop2 patsetbit pattern patternstart patwait patwait0 patwait1 patwait2 patwaittime patwaittime0 patwaittime1 patwaittime2 patword pedestalmode period periodl polarity port powerchip powerindex powerlist powername powervalues programfpga pulse pulsechip pulsenmove pumpprobe quad ratecorr readnrows readout readoutspeed readoutspeedlist rebootcontroller reg resetdacs resetfpga romode row runclk runtime rx_arping rx_clearroi rx_dbitlist rx_dbitoffset rx_dbitreorder rx_discardpolicy rx_fifodepth rx_frameindex rx_framescaught rx_framesperfile rx_hostname rx_jsonaddheader rx_jsonpara rx_lastclient rx_lock rx_missingpackets rx_padding rx_printconfig rx_realudpsocksize rx_roi rx_silent rx_start rx_status rx_stop rx_tcpport rx_threads rx_udpsocksize rx_version rx_zmqfreq rx_zmqhwm rx_zmqip rx_zmqport rx_zmqstartfnum rx_zmqstream samples savepattern scan scanerrmsg selinterface serialnumber setbit settings settingslist settingspath signalindex signallist signalname sleep slowadc slowadcindex slowadclist slowadcname slowadcvalues start status stop stopport storagecell_delay storagecell_start subdeadtime subexptime sync syncclk temp_10ge temp_adc temp_control temp_dcdc temp_event temp_fpga temp_fpgaext temp_fpgafl temp_fpgafr temp_slowadc temp_sodl temp_sodr temp_threshold templist tempvalues tengiga threshold thresholdnotb timing timing_info_decoder timinglist timingsource top transceiverenable trigger triggers triggersl trimbits trimen trimval tsamples txdelay txdelay_frame txdelay_left txdelay_right type udp_cleardst udp_dstip udp_dstip2 udp_dstlist udp_dstmac udp_dstmac2 udp_dstport udp_dstport2 udp_firstdst udp_numdst udp_reconfigure udp_srcip udp_srcip2 udp_srcmac udp_srcmac2 udp_validate update updatedetectorserver updatekernel updatemode user v_a v_b v_c v_chip v_d v_io v_limit vchip_comp_adc vchip_comp_fe vchip_cs vchip_opa_1st vchip_opa_fd vchip_ref_comp_fe versions veto vetoalg vetofile vetophoton vetoref vetostream virtual vm_a vm_b vm_c vm_d vm_io zmqhwm zmqip zmqport "
__acquire() {
FCN_RETURN=""
return 0
@@ -606,54 +606,6 @@ fi
fi
return 0
}
__define_bit() {
FCN_RETURN=""
if [[ ${IS_GET} -eq 1 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN=""
fi
if [[ "${cword}" == "3" ]]; then
FCN_RETURN=""
fi
fi
if [[ ${IS_GET} -eq 0 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN=""
fi
if [[ "${cword}" == "3" ]]; then
FCN_RETURN=""
fi
if [[ "${cword}" == "4" ]]; then
FCN_RETURN=""
fi
fi
return 0
}
__define_reg() {
FCN_RETURN=""
if [[ ${IS_GET} -eq 1 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN=""
fi
fi
if [[ ${IS_GET} -eq 0 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN=""
fi
if [[ "${cword}" == "3" ]]; then
FCN_RETURN=""
fi
fi
return 0
}
__definelist_bit() {
FCN_RETURN=""
return 0
}
__definelist_reg() {
FCN_RETURN=""
return 0
}
__delay() {
FCN_RETURN=""
if [[ ${IS_GET} -eq 1 ]]; then

View File

@@ -1272,7 +1272,7 @@ asamples:
function: setNumberOfAnalogSamples
adcclk:
help: "[n_clk in MHz]\n\t[Ctb] ADC clock frequency in MHz.\n\t[xilinx Ctb] ADC clock frequency in kHz."
help: "[n_clk in MHz]\n\t[Ctb] ADC clock frequency in MHz."
inherit_actions: INTEGER_COMMAND_VEC_ID
actions:
GET:
@@ -1281,7 +1281,7 @@ adcclk:
function: setADCClock
runclk:
help: "[n_clk in MHz]\n\t[Ctb] Run clock in MHz.\n\t[xilinx Ctb] Run clock in kHz."
help: "[n_clk in MHz]\n\t[Ctb] Run clock in MHz."
inherit_actions: INTEGER_COMMAND_VEC_ID
actions:
GET:
@@ -1318,7 +1318,7 @@ romode:
input_types: [ defs::readoutMode ]
dbitclk:
help: "[n_clk in MHz]\n\t[Ctb] Clock for latching the digital bits in MHz.\n\t[xilinx Ctb] Clock for latching the digital bits in kHz."
help: "[n_clk in MHz]\n\t[Ctb] Clock for latching the digital bits in MHz."
inherit_actions: INTEGER_COMMAND_VEC_ID
actions:
GET:
@@ -1791,7 +1791,7 @@ defaultpattern:
patternstart:
inherit_actions: EXECUTE_SET_COMMAND
help: "\n\t[Mythen3][Ctb][Xilinx Ctb] Starts Pattern"
help: "\n\t[Mythen3] Starts Pattern"
actions:
PUT:
function: startPattern
@@ -2761,90 +2761,6 @@ sleep:
- argc: 2
arg_types: [ int, special::time_unit ]
define_reg:
is_description: true
actions:
GET:
argc: 1
arg_types: [ std::string ]
PUT:
argc: 2
arg_types: [ std::string, int ]
define_bit:
is_description: true
actions:
GET:
args:
- argc: 1
arg_types: [ std::string ]
- argc: 2
arg_types: [ std::string, int ]
PUT:
argc: 3
arg_types: [ std::string, std::string, int ]
definelist_reg:
is_description: true
actions:
GET:
argc: 0
definelist_bit:
is_description: true
actions:
GET:
argc: 0
reg:
is_description: true
actions:
GET:
argc: 1
arg_types: [ std::string]
PUT:
args:
- argc: 2
arg_types: [ uint32_t, uint32_t ]
- argc: 3
arg_types: [ uint32_t, uint32_t, special::validate ]
getbit:
is_description: true
actions:
GET:
args:
- argc: 1
arg_types: [ std::string ]
- argc: 2
arg_types: [ std::string, std::string ]
setbit:
is_description: true
actions:
PUT:
args:
- argc: 1
arg_types: [ std::string ]
- argc: 2
arg_types: [ std::string, std::string ]
- argc: 3
arg_types: [ std::string, std::string, special::validate ]
clearbit:
is_description: true
actions:
PUT:
args:
- argc: 1
arg_types: [ std::string ]
- argc: 2
arg_types: [ std::string, std::string ]
- argc: 3
arg_types: [ std::string, std::string, special::validate ]
################# special commands ##########################
@@ -4256,6 +4172,36 @@ update:
input_types: [ std::string, std::string ]
output: [ '"successful"' ]
reg:
help: "[address] [32 bit value][(optional)--validate]\n\t[Mythen3][Gotthard2] Reads/writes to a 32 bit register in hex. Advanced Function!\n\tGoes to stop server. Hence, can be called while calling blocking acquire().\n\t\t Use --validate to force validation when writing to it.\n\t[Eiger] +0x100 for only left, +0x200 for only right."
actions:
GET:
argc: 1
require_det_id: true
function: readRegister
input: [ 'args[0]' ]
input_types: [ uint32_t ]
cast_input: [ true ]
output: [ OutStringHex(t) ]
PUT:
require_det_id: true
function: writeRegister
output: [ '"["', 'args[0]', '", "', 'args[1]', '"]"' ]
args:
- argc: 2
input: [ 'args[0]', 'args[1]', '"0"' ]
input_types: [ uint32_t, uint32_t, bool ]
arg_types: [ uint32_t, uint32_t ]
cast_input: [ true, true, true ]
- argc: 3
arg_types: [ uint32_t, uint32_t, special::validate ]
exceptions:
- condition: 'args[2] != "--validate"'
message: '"Could not scan third argument. Did you mean --validate?"'
input: [ 'args[0]', 'args[1]', '"1"' ]
input_types: [ uint32_t, uint32_t, bool ]
cast_input: [ true, true, true ]
adcreg:
help: "[address] [value]\n\t[Jungfrau][Moench][Ctb] Writes to an adc register in hex. Advanced user Function!"
actions:
@@ -4268,7 +4214,62 @@ adcreg:
cast_input: [ true, true ]
output: [ ToString(args) ]
getbit:
help: "[reg address in hex] [bit index]\n\tGets bit in address."
actions:
GET:
argc: 2
exceptions:
- condition: 'StringTo<int>(args[1]) < 0 || StringTo<int>(args[1]) > 31'
message: '"Bit number out of range: " + args[1]'
require_det_id: true
function: getBit
input: [ 'args[0]', 'args[1]' ]
input_types: [ uint32_t, int ]
cast_input: [ true, true ]
output: [ OutString(t) ]
Setbit:
template: true
actions:
PUT:
require_det_id: true
function: setBit
output: [ '"["', 'args[0]', '", "', 'args[1]', '"]"' ]
args:
- argc: 2
exceptions:
- condition: 'StringTo<int>(args[1]) < 0 || StringTo<int>(args[1]) > 31'
message: '"Bit number out of range: " + args[1]'
input: [ 'args[0]', 'args[1]', '"0"' ]
input_types: [ uint32_t, int, bool ]
arg_types: [ uint32_t, int ]
cast_input: [ true, true, true ]
- argc: 3
arg_types: [ uint32_t, int, special::validate ]
exceptions:
- condition: 'StringTo<int>(args[1]) < 0 || StringTo<int>(args[1]) > 31'
message: '"Bit number out of range: " + args[1]'
- condition: 'args[2] != "--validate"'
message: '"Could not scan third argument. Did you mean --validate?"'
input: [ 'args[0]', 'args[1]', '"1"' ]
input_types: [ uint32_t, int, bool ]
cast_input: [ true, true, true ]
setbit:
inherit_actions: Setbit
help: "[reg address in hex] [bit index]\n\tSets bit in address.\n\tUse --validate to force validation."
actions:
PUT:
function: setBit
clearbit:
inherit_actions: Setbit
help: "[reg address in hex] [bit index]\n\tClears bit in address.\n\tUse --validate to force validation."
actions:
PUT:
function: clearBit
initialchecks:
help: "[0, 1]\n\t[Mythen3][Gotthard2] Enable or disable intial compatibility and other checks at detector start up. It is enabled by default. Must come before 'hostname' command to take effect. Can be used to reprogram fpga when current firmware is incompatible.\n\tAdvanced User function!"

View File

@@ -106,8 +106,7 @@ adcclk:
store_result_in_t: false
command_name: adcclk
function_alias: adcclk
help: "[n_clk in MHz]\n\t[Ctb] ADC clock frequency in MHz.\n\t[xilinx Ctb] ADC clock\
\ frequency in kHz."
help: "[n_clk in MHz]\n\t[Ctb] ADC clock frequency in MHz."
infer_action: true
template: true
adcenable:
@@ -1096,49 +1095,74 @@ clearbit:
PUT:
args:
- arg_types:
- std::string
argc: 1
cast_input: []
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
store_result_in_t: false
- arg_types:
- std::string
- std::string
- uint32_t
- int
argc: 2
cast_input: []
cast_input:
- true
- true
- true
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
exceptions:
- condition: StringTo<int>(args[1]) < 0 || StringTo<int>(args[1]) > 31
message: '"Bit number out of range: " + args[1]'
function: clearBit
input:
- args[0]
- args[1]
- '"0"'
input_types:
- uint32_t
- int
- bool
output:
- '"["'
- args[0]
- '", "'
- args[1]
- '"]"'
require_det_id: true
store_result_in_t: false
- arg_types:
- std::string
- std::string
- uint32_t
- int
- special::validate
argc: 3
cast_input: []
cast_input:
- true
- true
- true
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
exceptions:
- condition: StringTo<int>(args[1]) < 0 || StringTo<int>(args[1]) > 31
message: '"Bit number out of range: " + args[1]'
- condition: args[2] != "--validate"
message: '"Could not scan third argument. Did you mean --validate?"'
function: clearBit
input:
- args[0]
- args[1]
- '"1"'
input_types:
- uint32_t
- int
- bool
output:
- '"["'
- args[0]
- '", "'
- args[1]
- '"]"'
require_det_id: true
store_result_in_t: false
command_name: clearbit
function_alias: clearbit
help: ''
help: "[reg address in hex] [bit index]\n\tClears bit in address.\n\tUse --validate\
\ to force validation."
infer_action: true
is_description: true
template: true
clearbusy:
actions:
PUT:
@@ -2195,8 +2219,7 @@ dbitclk:
store_result_in_t: false
command_name: dbitclk
function_alias: dbitclk
help: "[n_clk in MHz]\n\t[Ctb] Clock for latching the digital bits in MHz.\n\t[xilinx\
\ Ctb] Clock for latching the digital bits in kHz."
help: "[n_clk in MHz]\n\t[Ctb] Clock for latching the digital bits in MHz."
infer_action: true
template: true
dbitphase:
@@ -2475,132 +2498,6 @@ defaultpattern:
\ to go back to initial settings."
infer_action: true
template: true
define_bit:
actions:
GET:
args:
- arg_types:
- std::string
argc: 1
cast_input: []
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
store_result_in_t: true
- arg_types:
- std::string
- int
argc: 2
cast_input: []
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
store_result_in_t: true
PUT:
args:
- arg_types:
- std::string
- std::string
- int
argc: 3
cast_input: []
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
store_result_in_t: false
command_name: define_bit
function_alias: define_bit
help: ''
infer_action: true
is_description: true
define_reg:
actions:
GET:
args:
- arg_types:
- std::string
argc: 1
cast_input: []
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
store_result_in_t: true
PUT:
args:
- arg_types:
- std::string
- int
argc: 2
cast_input: []
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
store_result_in_t: false
command_name: define_reg
function_alias: define_reg
help: ''
infer_action: true
is_description: true
definelist_bit:
actions:
GET:
args:
- arg_types: []
argc: 0
cast_input: []
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
store_result_in_t: true
command_name: definelist_bit
function_alias: definelist_bit
help: ''
infer_action: true
is_description: true
definelist_reg:
actions:
GET:
args:
- arg_types: []
argc: 0
cast_input: []
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
store_result_in_t: true
command_name: definelist_reg
function_alias: definelist_reg
help: ''
infer_action: true
is_description: true
delay:
actions:
GET:
@@ -4807,35 +4704,32 @@ getbit:
GET:
args:
- arg_types:
- std::string
argc: 1
cast_input: []
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
store_result_in_t: true
- arg_types:
- std::string
- std::string
- uint32_t
- int
argc: 2
cast_input: []
cast_input:
- true
- true
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
exceptions:
- condition: StringTo<int>(args[1]) < 0 || StringTo<int>(args[1]) > 31
message: '"Bit number out of range: " + args[1]'
function: getBit
input:
- args[0]
- args[1]
input_types:
- uint32_t
- int
output:
- OutString(t)
require_det_id: true
store_result_in_t: true
command_name: getbit
function_alias: getbit
help: ''
help: "[reg address in hex] [bit index]\n\tGets bit in address."
infer_action: true
is_description: true
hardwareversion:
actions:
GET:
@@ -6621,7 +6515,7 @@ patternstart:
store_result_in_t: false
command_name: patternstart
function_alias: patternstart
help: "\n\t[Mythen3][Ctb][Xilinx Ctb] Starts Pattern"
help: "\n\t[Mythen3] Starts Pattern"
infer_action: true
template: true
patwait:
@@ -7974,16 +7868,20 @@ reg:
GET:
args:
- arg_types:
- std::string
- uint32_t
argc: 1
cast_input: []
cast_input:
- true
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
function: readRegister
input:
- args[0]
input_types:
- uint32_t
output:
- OutStringHex(t)
require_det_id: true
store_result_in_t: true
PUT:
args:
@@ -7991,34 +7889,68 @@ reg:
- uint32_t
- uint32_t
argc: 2
cast_input: []
cast_input:
- true
- true
- true
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
function: writeRegister
input:
- args[0]
- args[1]
- '"0"'
input_types:
- uint32_t
- uint32_t
- bool
output:
- '"["'
- args[0]
- '", "'
- args[1]
- '"]"'
require_det_id: true
store_result_in_t: false
- arg_types:
- uint32_t
- uint32_t
- special::validate
argc: 3
cast_input: []
cast_input:
- true
- true
- true
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
exceptions:
- condition: args[2] != "--validate"
message: '"Could not scan third argument. Did you mean --validate?"'
function: writeRegister
input:
- args[0]
- args[1]
- '"1"'
input_types:
- uint32_t
- uint32_t
- bool
output:
- '"["'
- args[0]
- '", "'
- args[1]
- '"]"'
require_det_id: true
store_result_in_t: false
command_name: reg
function_alias: reg
help: ''
help: "[address] [32 bit value][(optional)--validate]\n\t[Mythen3][Gotthard2] Reads/writes\
\ to a 32 bit register in hex. Advanced Function!\n\tGoes to stop server. Hence,\
\ can be called while calling blocking acquire().\n\t\t Use --validate to force\
\ validation when writing to it.\n\t[Eiger] +0x100 for only left, +0x200 for only\
\ right."
infer_action: true
is_description: true
resetdacs:
actions:
PUT:
@@ -8201,7 +8133,7 @@ runclk:
store_result_in_t: false
command_name: runclk
function_alias: runclk
help: "[n_clk in MHz]\n\t[Ctb] Run clock in MHz.\n\t[xilinx Ctb] Run clock in kHz."
help: "[n_clk in MHz]\n\t[Ctb] Run clock in MHz."
infer_action: true
template: true
runtime:
@@ -9643,49 +9575,74 @@ setbit:
PUT:
args:
- arg_types:
- std::string
argc: 1
cast_input: []
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
store_result_in_t: false
- arg_types:
- std::string
- std::string
- uint32_t
- int
argc: 2
cast_input: []
cast_input:
- true
- true
- true
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
exceptions:
- condition: StringTo<int>(args[1]) < 0 || StringTo<int>(args[1]) > 31
message: '"Bit number out of range: " + args[1]'
function: setBit
input:
- args[0]
- args[1]
- '"0"'
input_types:
- uint32_t
- int
- bool
output:
- '"["'
- args[0]
- '", "'
- args[1]
- '"]"'
require_det_id: true
store_result_in_t: false
- arg_types:
- std::string
- std::string
- uint32_t
- int
- special::validate
argc: 3
cast_input: []
cast_input:
- true
- true
- true
check_det_id: false
convert_det_id: true
function: ''
input: []
input_types: []
output: []
require_det_id: false
exceptions:
- condition: StringTo<int>(args[1]) < 0 || StringTo<int>(args[1]) > 31
message: '"Bit number out of range: " + args[1]'
- condition: args[2] != "--validate"
message: '"Could not scan third argument. Did you mean --validate?"'
function: setBit
input:
- args[0]
- args[1]
- '"1"'
input_types:
- uint32_t
- int
- bool
output:
- '"["'
- args[0]
- '", "'
- args[1]
- '"]"'
require_det_id: true
store_result_in_t: false
command_name: setbit
function_alias: setbit
help: ''
help: "[reg address in hex] [bit index]\n\tSets bit in address.\n\tUse --validate\
\ to force validation."
infer_action: true
is_description: true
template: true
settings:
actions:
GET:

View File

@@ -3,7 +3,6 @@
#pragma once
#include "sls/Pattern.h"
#include "sls/Result.h"
#include "sls/bit_utils.h"
#include "sls/network_utils.h"
#include "sls/sls_detector_defs.h"
#include <chrono>
@@ -1613,16 +1612,16 @@ class Detector {
/** [CTB] */
void setNumberOfAnalogSamples(int value, Positions pos = {});
/** [CTB] in MHz, [XCTB] in kHz */
/** [CTB] */
Result<int> getADCClock(Positions pos = {}) const;
/** [CTB] in MHz, [XCTB] in kHz */
/** [CTB] */
void setADCClock(int value_in_MHz, Positions pos = {});
/** [CTB] in MHz, [XCTB] in kHz */
/** [CTB] */
Result<int> getRUNClock(Positions pos = {}) const;
/** [CTB] in MHz, [XCTB] in kHz */
/** [CTB] */
void setRUNClock(int value_in_MHz, Positions pos = {});
/** [CTB] in MHZ */
@@ -1692,10 +1691,10 @@ class Detector {
*/
void setReadoutMode(defs::readoutMode value, Positions pos = {});
/** [CTB] in MHz, [XCTB] in kHz */
/** [CTB] */
Result<int> getDBITClock(Positions pos = {}) const;
/** [CTB] in MHz, [XCTB] in kHz */
/** [CTB] */
void setDBITClock(int value_in_MHz, Positions pos = {});
/**
@@ -1838,61 +1837,6 @@ class Detector {
/** [CTB][Xilinx CTB] */
std::string getSlowADCName(const defs::dacIndex i) const;
/** [CTB][Xilinx CTB] */
int getRegisterDefinitionsCount() const;
/** [CTB][Xilinx CTB] */
void setRegisterDefinition(const std::string &name, RegisterAddress addr);
/** [CTB][Xilinx CTB] */
bool hasRegisterDefinition(const std::string &name) const;
/** [CTB][Xilinx CTB] */
bool hasRegisterDefinition(RegisterAddress addr) const;
/** [CTB][Xilinx CTB] */
RegisterAddress getRegisterDefinitionAddress(const std::string &name) const;
/** [CTB][Xilinx CTB] */
std::string getRegisterDefinitionName(RegisterAddress addr) const;
/** [CTB][Xilinx CTB] */
void clearRegisterDefinitions();
/** [CTB][Xilinx CTB] */
void
setRegisterDefinitions(const std::map<std::string, RegisterAddress> &list);
/** [CTB][Xilinx CTB] */
std::map<std::string, RegisterAddress> getRegisterDefinitions() const;
/** [CTB][Xilinx CTB] */
int getBitDefinitionsCount() const;
/** [CTB][Xilinx CTB] */
void setBitDefinition(const std::string &name, BitAddress addr);
/** [CTB][Xilinx CTB] */
bool hasBitDefinition(const std::string &name) const;
/** [CTB][Xilinx CTB] */
bool hasBitDefinition(BitAddress addr) const;
/** [CTB][Xilinx CTB] returns bit position and address */
BitAddress getBitDefinitionAddress(const std::string &name) const;
/** [CTB][Xilinx CTB] */
std::string getBitDefinitionName(BitAddress addr) const;
/** [CTB][Xilinx CTB] */
void clearBitDefinitions();
/** [CTB][Xilinx CTB] */
void setBitDefinitions(const std::map<std::string, BitAddress> &list);
/** [CTB][Xilinx CTB] */
std::map<std::string, BitAddress> getBitDefinitions() const;
///@}
/** @name Xilinx CTB Specific */
@@ -1999,7 +1943,7 @@ class Detector {
* selected bits */
void setPatternBitMask(uint64_t mask, Positions pos = {});
/** [CTB][Mythen3][Xilinx CTB] */
/** [Mythen3] */
void startPattern(Positions pos = {});
///@}
@@ -2101,71 +2045,26 @@ class Detector {
/** Advanced user Function! \n
* Goes to stop server. Hence, can be called while calling blocking
* acquire(). \n [Eiger] Address is +0x100 for only left, +0x200 for only
* right.*/
Result<RegisterValue> readRegister(RegisterAddress addr,
Positions pos = {}) const;
* right. */
Result<uint32_t> readRegister(uint32_t addr, Positions pos = {}) const;
/** Advanced user Function! \n
* Goes to stop server. Hence, can be called while calling blocking
* acquire(). \n [Eiger] Address is +0x100 for only left, +0x200 for only
* right.*/
void writeRegister(RegisterAddress addr, RegisterValue val,
bool validate = false, Positions pos = {});
* right. */
void writeRegister(uint32_t addr, uint32_t val, bool validate = false,
Positions pos = {});
/** Advanced user Function! */
void setBit(BitAddress addr, bool validate = false, Positions pos = {});
/** Advanced user Function!*/
void clearBit(BitAddress addr, bool validate = false, Positions pos = {});
/** Advanced user Function! */
Result<int> getBit(BitAddress addr, Positions pos = {}) const;
/** [CTB][Xilinx CTB] Advanced user Function! */
Result<RegisterValue> readRegister(const std::string &reg_name,
Positions pos = {}) const;
/** [CTB][Xilinx CTB] Advanced user Function! */
void writeRegister(const std::string &reg_name, RegisterValue val,
bool validate = false, Positions pos = {});
/** [CTB][Xilinx CTB] Advanced user Function! */
void setBit(const std::string &bit_name, bool validate = false,
/** Advanced user Function! */
void setBit(uint32_t addr, int bitnr, bool validate = false,
Positions pos = {});
/** [CTB][Xilinx CTB] Advanced user Function! */
void clearBit(const std::string &bit_name, bool validate = false,
/** Advanced user Function! */
void clearBit(uint32_t addr, int bitnr, bool validate = false,
Positions pos = {});
/** [CTB][Xilinx CTB] Advanced user Function! */
Result<int> getBit(const std::string &bit_name, Positions pos = {}) const;
/** Deprecated Advanced user Function! */
[[deprecated("Use the overload taking RegisterAddress instead of "
"uint32_t")]] Result<uint32_t>
readRegister(uint32_t addr, Positions pos = {}) const;
/** Deprecated Advanced user Function! */
[[deprecated("Use the overload taking RegisterAddress and RegisterValue "
"instead of uint32_t")]] void
writeRegister(uint32_t addr, uint32_t val, bool validate = false,
Positions pos = {});
/** Deprecated Advanced user Function! */
[[deprecated("Use the overload taking BitAddress instead of uint32_t and "
"int")]] void
setBit(uint32_t addr, int bitnr, bool validate = false, Positions pos = {});
/** Deprecated Advanced user Function! */
[[deprecated("Use the overload taking BitAddress instead of uint32_t and "
"int")]] void
clearBit(uint32_t addr, int bitnr, bool validate = false,
Positions pos = {});
/** Deprecated Advanced user Function! */
[[deprecated("Use the overload taking BitAddress instead of uint32_t and "
"int")]] Result<int>
getBit(uint32_t addr, int bitnr, Positions pos = {}) const;
/** Advanced user Function! */
Result<int> getBit(uint32_t addr, int bitnr, Positions pos = {});
/** [Jungfrau][Moench][Mythen3][Gotthard2][CTB] Advanced user
* Function! */

View File

@@ -73,8 +73,7 @@ std::string Caller::adcclk(int action) {
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N([n_clk in MHz]
[Ctb] ADC clock frequency in MHz.
[xilinx Ctb] ADC clock frequency in kHz. )V0G0N"
[Ctb] ADC clock frequency in MHz. )V0G0N"
<< std::endl;
return os.str();
}
@@ -1453,6 +1452,100 @@ std::string Caller::chipversion(int action) {
return os.str();
}
std::string Caller::clearbit(int action) {
std::ostringstream os;
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N([reg address in hex] [bit index]
Clears bit in address.
Use --validate to force validation. )V0G0N"
<< std::endl;
return os.str();
}
// check if action and arguments are valid
if (action == slsDetectorDefs::PUT_ACTION) {
if (1 && args.size() != 2 && args.size() != 3) {
throw RuntimeError("Wrong number of arguments for action PUT");
}
if (args.size() == 2) {
try {
StringTo<uint32_t>(args[0]);
} catch (...) {
throw RuntimeError("Could not convert argument 0 to uint32_t");
}
try {
StringTo<int>(args[1]);
} catch (...) {
throw RuntimeError("Could not convert argument 1 to int");
}
try {
StringTo<bool>("0");
} catch (...) {
throw RuntimeError("Could not convert argument 2 to bool");
}
}
if (args.size() == 3) {
try {
StringTo<uint32_t>(args[0]);
} catch (...) {
throw RuntimeError("Could not convert argument 0 to uint32_t");
}
try {
StringTo<int>(args[1]);
} catch (...) {
throw RuntimeError("Could not convert argument 1 to int");
}
try {
StringTo<bool>("1");
} catch (...) {
throw RuntimeError("Could not convert argument 2 to bool");
}
}
}
else {
throw RuntimeError(
"INTERNAL ERROR: Invalid action: supported actions are ['PUT']");
}
// generate code for each action
if (action == slsDetectorDefs::PUT_ACTION) {
if (args.size() == 2) {
if (StringTo<int>(args[1]) < 0 || StringTo<int>(args[1]) > 31) {
throw RuntimeError("Bit number out of range: " + args[1]);
}
auto arg0 = StringTo<uint32_t>(args[0]);
auto arg1 = StringTo<int>(args[1]);
auto arg2 = StringTo<bool>("0");
det->clearBit(arg0, arg1, arg2, std::vector<int>{det_id});
os << "[" << args[0] << ", " << args[1] << "]" << '\n';
}
if (args.size() == 3) {
if (StringTo<int>(args[1]) < 0 || StringTo<int>(args[1]) > 31) {
throw RuntimeError("Bit number out of range: " + args[1]);
}
if (args[2] != "--validate") {
throw RuntimeError(
"Could not scan third argument. Did you mean --validate?");
}
auto arg0 = StringTo<uint32_t>(args[0]);
auto arg1 = StringTo<int>(args[1]);
auto arg2 = StringTo<bool>("1");
det->clearBit(arg0, arg1, arg2, std::vector<int>{det_id});
os << "[" << args[0] << ", " << args[1] << "]" << '\n';
}
}
return os.str();
}
std::string Caller::clearbusy(int action) {
std::ostringstream os;
@@ -2712,8 +2805,7 @@ std::string Caller::dbitclk(int action) {
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N([n_clk in MHz]
[Ctb] Clock for latching the digital bits in MHz.
[xilinx Ctb] Clock for latching the digital bits in kHz. )V0G0N"
[Ctb] Clock for latching the digital bits in MHz. )V0G0N"
<< std::endl;
return os.str();
}
@@ -5861,6 +5953,60 @@ std::string Caller::gates(int action) {
return os.str();
}
std::string Caller::getbit(int action) {
std::ostringstream os;
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N([reg address in hex] [bit index]
Gets bit in address. )V0G0N"
<< std::endl;
return os.str();
}
// check if action and arguments are valid
if (action == slsDetectorDefs::GET_ACTION) {
if (1 && args.size() != 2) {
throw RuntimeError("Wrong number of arguments for action GET");
}
if (args.size() == 2) {
try {
StringTo<uint32_t>(args[0]);
} catch (...) {
throw RuntimeError("Could not convert argument 0 to uint32_t");
}
try {
StringTo<int>(args[1]);
} catch (...) {
throw RuntimeError("Could not convert argument 1 to int");
}
}
}
else {
throw RuntimeError(
"INTERNAL ERROR: Invalid action: supported actions are ['GET']");
}
// generate code for each action
if (action == slsDetectorDefs::GET_ACTION) {
if (args.size() == 2) {
if (StringTo<int>(args[1]) < 0 || StringTo<int>(args[1]) > 31) {
throw RuntimeError("Bit number out of range: " + args[1]);
}
auto arg0 = StringTo<uint32_t>(args[0]);
auto arg1 = StringTo<int>(args[1]);
auto t = det->getBit(arg0, arg1, std::vector<int>{det_id});
os << OutString(t) << '\n';
}
}
return os.str();
}
std::string Caller::hardwareversion(int action) {
std::ostringstream os;
@@ -8306,7 +8452,7 @@ std::string Caller::patternstart(int action) {
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N(
[Mythen3][Ctb][Xilinx Ctb] Starts Pattern )V0G0N"
[Mythen3] Starts Pattern )V0G0N"
<< std::endl;
return os.str();
}
@@ -9948,6 +10094,119 @@ std::string Caller::rebootcontroller(int action) {
return os.str();
}
std::string Caller::reg(int action) {
std::ostringstream os;
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N([address] [32 bit value][(optional)--validate]
[Mythen3][Gotthard2] Reads/writes to a 32 bit register in hex. Advanced Function!
Goes to stop server. Hence, can be called while calling blocking acquire().
Use --validate to force validation when writing to it.
[Eiger] +0x100 for only left, +0x200 for only right. )V0G0N"
<< std::endl;
return os.str();
}
// check if action and arguments are valid
if (action == slsDetectorDefs::GET_ACTION) {
if (1 && args.size() != 1) {
throw RuntimeError("Wrong number of arguments for action GET");
}
if (args.size() == 1) {
try {
StringTo<uint32_t>(args[0]);
} catch (...) {
throw RuntimeError("Could not convert argument 0 to uint32_t");
}
}
}
else if (action == slsDetectorDefs::PUT_ACTION) {
if (1 && args.size() != 2 && args.size() != 3) {
throw RuntimeError("Wrong number of arguments for action PUT");
}
if (args.size() == 2) {
try {
StringTo<uint32_t>(args[0]);
} catch (...) {
throw RuntimeError("Could not convert argument 0 to uint32_t");
}
try {
StringTo<uint32_t>(args[1]);
} catch (...) {
throw RuntimeError("Could not convert argument 1 to uint32_t");
}
try {
StringTo<bool>("0");
} catch (...) {
throw RuntimeError("Could not convert argument 2 to bool");
}
}
if (args.size() == 3) {
try {
StringTo<uint32_t>(args[0]);
} catch (...) {
throw RuntimeError("Could not convert argument 0 to uint32_t");
}
try {
StringTo<uint32_t>(args[1]);
} catch (...) {
throw RuntimeError("Could not convert argument 1 to uint32_t");
}
try {
StringTo<bool>("1");
} catch (...) {
throw RuntimeError("Could not convert argument 2 to bool");
}
}
}
else {
throw RuntimeError("INTERNAL ERROR: Invalid action: supported actions "
"are ['GET', 'PUT']");
}
// generate code for each action
if (action == slsDetectorDefs::GET_ACTION) {
if (args.size() == 1) {
auto arg0 = StringTo<uint32_t>(args[0]);
auto t = det->readRegister(arg0, std::vector<int>{det_id});
os << OutStringHex(t) << '\n';
}
}
if (action == slsDetectorDefs::PUT_ACTION) {
if (args.size() == 2) {
auto arg0 = StringTo<uint32_t>(args[0]);
auto arg1 = StringTo<uint32_t>(args[1]);
auto arg2 = StringTo<bool>("0");
det->writeRegister(arg0, arg1, arg2, std::vector<int>{det_id});
os << "[" << args[0] << ", " << args[1] << "]" << '\n';
}
if (args.size() == 3) {
if (args[2] != "--validate") {
throw RuntimeError(
"Could not scan third argument. Did you mean --validate?");
}
auto arg0 = StringTo<uint32_t>(args[0]);
auto arg1 = StringTo<uint32_t>(args[1]);
auto arg2 = StringTo<bool>("1");
det->writeRegister(arg0, arg1, arg2, std::vector<int>{det_id});
os << "[" << args[0] << ", " << args[1] << "]" << '\n';
}
}
return os.str();
}
std::string Caller::resetdacs(int action) {
std::ostringstream os;
@@ -10170,8 +10429,7 @@ std::string Caller::runclk(int action) {
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N([n_clk in MHz]
[Ctb] Run clock in MHz.
[xilinx Ctb] Run clock in kHz. )V0G0N"
[Ctb] Run clock in MHz. )V0G0N"
<< std::endl;
return os.str();
}
@@ -12123,6 +12381,100 @@ std::string Caller::serialnumber(int action) {
return os.str();
}
std::string Caller::setbit(int action) {
std::ostringstream os;
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N([reg address in hex] [bit index]
Sets bit in address.
Use --validate to force validation. )V0G0N"
<< std::endl;
return os.str();
}
// check if action and arguments are valid
if (action == slsDetectorDefs::PUT_ACTION) {
if (1 && args.size() != 2 && args.size() != 3) {
throw RuntimeError("Wrong number of arguments for action PUT");
}
if (args.size() == 2) {
try {
StringTo<uint32_t>(args[0]);
} catch (...) {
throw RuntimeError("Could not convert argument 0 to uint32_t");
}
try {
StringTo<int>(args[1]);
} catch (...) {
throw RuntimeError("Could not convert argument 1 to int");
}
try {
StringTo<bool>("0");
} catch (...) {
throw RuntimeError("Could not convert argument 2 to bool");
}
}
if (args.size() == 3) {
try {
StringTo<uint32_t>(args[0]);
} catch (...) {
throw RuntimeError("Could not convert argument 0 to uint32_t");
}
try {
StringTo<int>(args[1]);
} catch (...) {
throw RuntimeError("Could not convert argument 1 to int");
}
try {
StringTo<bool>("1");
} catch (...) {
throw RuntimeError("Could not convert argument 2 to bool");
}
}
}
else {
throw RuntimeError(
"INTERNAL ERROR: Invalid action: supported actions are ['PUT']");
}
// generate code for each action
if (action == slsDetectorDefs::PUT_ACTION) {
if (args.size() == 2) {
if (StringTo<int>(args[1]) < 0 || StringTo<int>(args[1]) > 31) {
throw RuntimeError("Bit number out of range: " + args[1]);
}
auto arg0 = StringTo<uint32_t>(args[0]);
auto arg1 = StringTo<int>(args[1]);
auto arg2 = StringTo<bool>("0");
det->setBit(arg0, arg1, arg2, std::vector<int>{det_id});
os << "[" << args[0] << ", " << args[1] << "]" << '\n';
}
if (args.size() == 3) {
if (StringTo<int>(args[1]) < 0 || StringTo<int>(args[1]) > 31) {
throw RuntimeError("Bit number out of range: " + args[1]);
}
if (args[2] != "--validate") {
throw RuntimeError(
"Could not scan third argument. Did you mean --validate?");
}
auto arg0 = StringTo<uint32_t>(args[0]);
auto arg1 = StringTo<int>(args[1]);
auto arg2 = StringTo<bool>("1");
det->setBit(arg0, arg1, arg2, std::vector<int>{det_id});
os << "[" << args[0] << ", " << args[1] << "]" << '\n';
}
}
return os.str();
}
std::string Caller::settings(int action) {
std::ostringstream os;

View File

@@ -3,7 +3,7 @@
#include "CmdParser.h"
#include "HelpDacs.h"
#include "sls/Detector.h"
#include "sls/bit_utils.h"
#include <iostream>
#include <string>
#include <vector>
@@ -107,10 +107,6 @@ class Caller {
std::string dbitpipeline(int action);
std::string defaultdac(int action);
std::string defaultpattern(int action);
std::string define_bit(int action);
std::string define_reg(int action);
std::string definelist_bit(int action);
std::string definelist_reg(int action);
std::string delay(int action);
std::string delayl(int action);
std::string detectorserverversion(int action);
@@ -402,11 +398,6 @@ class Caller {
static void EmptyDataCallBack(detectorData *data, uint64_t frameIndex,
uint32_t subFrameIndex, void *this_pointer);
std::string bitoperations(int action);
RegisterAddress parseAddress(const std::string &saddr) const;
bool parseValidate();
BitAddress parseBitAddress() const;
FunctionMap functions{
{"list", &Caller::list},
@@ -460,10 +451,6 @@ class Caller {
{"dbitpipeline", &Caller::dbitpipeline},
{"defaultdac", &Caller::defaultdac},
{"defaultpattern", &Caller::defaultpattern},
{"define_bit", &Caller::define_bit},
{"define_reg", &Caller::define_reg},
{"definelist_bit", &Caller::definelist_bit},
{"definelist_reg", &Caller::definelist_reg},
{"delay", &Caller::delay},
{"delayl", &Caller::delayl},
{"detectorserverversion", &Caller::detectorserverversion},

View File

@@ -1437,398 +1437,4 @@ std::string Caller::sleep(int action) {
return os.str();
}
std::string Caller::define_reg(int action) {
std::ostringstream os;
if (action == defs::HELP_ACTION) {
os << "[Ctb][Xilinx Ctb]"
"\n\t[reg name] [reg address]"
"\n\n\tSets a user defined register in shared memory. The name "
"can be upto 32 characters long."
"\n\teg."
"\n\tsls_detector_put define_reg test_reg 0x200"
"\n\n\tOne can retrieve the address using the name and vice "
"versa."
"\n\teg."
"\n\tsls_detector_get define_reg test_reg"
"\n\tsls_detector_get define_reg 0x200"
"\n\n\tOne can then use this user-defined name in other commands "
"instead of hard coding the address such as for reg, setbit, "
"clearbit and getbit commands."
"\n\teg."
"\n\tsls_detector_put reg test_reg 0x1"
"\n\tsls_detector_put setbit test_reg 2"
"\n\tsls_detector_put clearbit test_reg 2"
"\n\tsls_detector_get getbit test_reg 2"
<< '\n';
return os.str();
}
auto det_type = det->getDetectorType().squash();
if (det_type != defs::XILINX_CHIPTESTBOARD &&
det_type != defs::CHIPTESTBOARD) {
throw RuntimeError(
"define_reg command only supported for ctb and xilinx_ctb");
}
if (det_id != -1) {
throw RuntimeError("Cannot use define at module level. Use the default "
"multi-module level");
}
if (action == defs::GET_ACTION) {
if (args.size() != 1) {
WrongNumberOfParameters(1);
}
// get name from address
if (is_hex_or_dec_uint(args[0])) {
auto addr = RegisterAddress(args[0]);
auto t = det->getRegisterDefinitionName(addr);
os << t << '\n';
}
// get address from name
else {
auto t = det->getRegisterDefinitionAddress(args[0]);
os << t.str() << '\n';
}
} else if (action == defs::PUT_ACTION) {
if (args.size() != 2) {
WrongNumberOfParameters(2);
}
auto name = args[0];
auto addr = RegisterAddress(args[1]);
det->setRegisterDefinition(name, addr);
os << "addr " << name << ' ' << addr.str() << '\n';
} else {
throw RuntimeError("Unknown action");
}
return os.str();
}
std::string Caller::define_bit(int action) {
std::ostringstream os;
if (action == defs::HELP_ACTION) {
os << "[Ctb][Xilinx Ctb]"
"\n\t[bit name] [regiser name/address] [bit position]"
"\n\n\tSets a user defined bit name in shared memory "
"representing the register address and the bit position. The "
"address can be named prior using define_reg command. The name "
"can be upto 32 characters long."
"\n\teg."
"\n\tsls_detector_put define_bit test_bit test_reg 2"
"\n\tsls_detector_put define_bit test_bit 0x200 2"
"\n\n\tOne can retrieve the bit address using the name and vice "
"versa using both register name or address and bit position."
"\n\teg."
"\n\tsls_detector_get define_bit test_bit"
"\n\tsls_detector_get define_bit test_reg 2"
"\n\tsls_detector_get define_bit 0x200 2"
"\n\n\tOne can then use this user-defined name in other commands "
"such as for setbit, clearbit and getbit commands. When using "
"bit names, please dont use register name or address as bit name "
"is already tied to a specific register."
"\n\teg."
"\n\tsls_detector_put setbit test_bit"
"\n\tsls_detector_put clearbit test_bit"
"\n\tsls_detector_get getbit test_bit"
<< '\n';
return os.str();
}
auto det_type = det->getDetectorType().squash();
if (det_type != defs::XILINX_CHIPTESTBOARD &&
det_type != defs::CHIPTESTBOARD) {
throw RuntimeError(
"define_bit command only supported for ctb and xilinx_ctb");
}
if (det_id != -1) {
throw RuntimeError("Cannot use define at module level. Use the default "
"multi-module level");
}
if (action == defs::GET_ACTION) {
// get position from name
if (args.size() == 1) {
auto t = det->getBitDefinitionAddress(args[0]);
bool found_addr = det->hasRegisterDefinition(t.address());
if (found_addr) {
os << '[' << det->getRegisterDefinitionName(t.address()) << ", "
<< std::to_string(t.bitPosition()) << "]\n";
} else {
os << t.str() << '\n';
}
}
// get name from position and address
else if (args.size() == 2) {
auto pos =
BitAddress(parseAddress(args[0]), StringTo<int>(args[1]));
try {
auto t = det->getBitDefinitionName(pos);
os << t << '\n';
} catch (const RuntimeError &e) {
std::string err_str = e.what();
if (err_str.find("No bit definition found") !=
std::string::npos &&
!is_hex_or_dec_uint(args[0])) {
err_str += " and addr = " + args[0];
throw RuntimeError(err_str);
}
throw;
}
} else {
WrongNumberOfParameters(1);
}
} else if (action == defs::PUT_ACTION) {
if (args.size() != 3) {
WrongNumberOfParameters(3);
}
if (!is_int(args[2])) {
throw RuntimeError("Bit position must be an integer value.");
}
auto name = args[0];
auto bit = BitAddress(parseAddress(args[1]), StringTo<int>(args[2]));
det->setBitDefinition(name, bit);
os << ToString(args) << '\n';
} else {
throw RuntimeError("Unknown action");
}
return os.str();
}
std::string Caller::definelist_reg(int action) {
std::ostringstream os;
if (action == defs::HELP_ACTION) {
os << "List of user-defined register definitions in shared memory."
<< '\n';
} else if (action == defs::PUT_ACTION) {
throw RuntimeError("cannot put");
} else if (action == defs::GET_ACTION) {
auto det_type = det->getDetectorType().squash();
if (det_type != defs::XILINX_CHIPTESTBOARD &&
det_type != defs::CHIPTESTBOARD) {
throw RuntimeError(
"definelist_reg command only supported for ctb and xilinx_ctb");
}
if (!args.empty()) {
WrongNumberOfParameters(0);
}
auto t = det->getRegisterDefinitions();
os << '\n' << ToString(t) << '\n';
} else {
throw RuntimeError("Unknown action");
}
return os.str();
}
std::string Caller::definelist_bit(int action) {
std::ostringstream os;
if (action == defs::HELP_ACTION) {
os << "List of user-defined bit definitions in shared memory." << '\n';
} else if (action == defs::PUT_ACTION) {
throw RuntimeError("cannot put");
} else if (action == defs::GET_ACTION) {
auto det_type = det->getDetectorType().squash();
if (det_type != defs::XILINX_CHIPTESTBOARD &&
det_type != defs::CHIPTESTBOARD) {
throw RuntimeError(
"definelist_bit command only supported for ctb and xilinx_ctb");
}
if (!args.empty()) {
WrongNumberOfParameters(0);
}
auto t = det->getBitDefinitions();
os << "\n[";
for (const auto &[key, val] : t) {
os << key << ": ";
bool found_addr = det->hasRegisterDefinition(val.address());
if (found_addr) {
os << '[' << det->getRegisterDefinitionName(val.address())
<< ", " << std::to_string(val.bitPosition()) << "]";
} else {
os << val.str();
}
if (&key != &t.rbegin()->first) {
os << ", ";
}
os << '\n';
}
os << "]\n";
} else {
throw RuntimeError("Unknown action");
}
return os.str();
}
std::string Caller::reg(int action) {
std::ostringstream os;
if (action == defs::HELP_ACTION) {
os << "[address] [32 bit value][(optional)--validate]"
"\n\tReads/writes to a 32 bit register in hex."
"\n\tAdvanced Function!\n\tGoes to stop server. Hence, can be "
"called while calling blocking acquire()."
"\n\t\t Use --validate to enforce validation when writing to "
"register."
"\n\t[Eiger] +0x100 for only left, +0x200 for only right."
"\n\t[Ctb][Xilinx_Ctb] Address can also be a user-defined name "
"that was set previously using the define command."
"\n\t\teg."
"\n\t\tsls_detector_put reg 0x200 0xFFF --validate"
"\n\t\tsls_detector_get reg test_reg"
"\n\t\tsls_detector_put reg test_reg 0xFF"
<< '\n';
} else {
if (action == defs::PUT_ACTION) {
if (args.size() < 2 || args.size() > 3) {
WrongNumberOfParameters(2);
}
auto validate = parseValidate();
auto addr = parseAddress(args[0]);
auto val = RegisterValue(StringTo<uint32_t>(args[1]));
det->writeRegister(addr, val, validate, std::vector<int>{det_id});
os << addr.str() << " " << val.str() << '\n';
} else if (action == defs::GET_ACTION) {
if (args.size() != 1) {
WrongNumberOfParameters(1);
}
auto addr = parseAddress(args[0]);
auto t = det->readRegister(addr, std::vector<int>{det_id});
os << OutString(t) << '\n';
} else {
throw RuntimeError("Unknown action");
}
}
return os.str();
}
std::string Caller::getbit(int action) { return bitoperations(action); }
std::string Caller::setbit(int action) { return bitoperations(action); }
std::string Caller::clearbit(int action) { return bitoperations(action); }
std::string Caller::bitoperations(int action) {
std::ostringstream os;
if (action == defs::HELP_ACTION) {
if (cmd == "getbit") {
os << "[reg address in hex] [bit index]\n\tGets bit in address."
<< '\n';
} else if (cmd == "setbit") {
os << "[reg address in hex] [bit index]\n\tSets bit in "
"address.\n\tUse --validate to force validation."
<< '\n';
} else if (cmd == "clearbit") {
os << "[reg address in hex] [bit index]\n\tClears bit in "
"address.\n\tUse --validate to force validation."
<< '\n';
} else {
throw RuntimeError("Unknown command");
}
os << "\n\t\t[Ctb][Xilinx_Ctb] Address or bit position can also be a "
"user-defined name that was set previously using the define "
"command. When using bit names, avoid register name/ address as "
"the bit name is tied to a specific register already."
"\n\n\teg."
"\n\tsls_detector_get getbit 0x200 2"
"\n\tsls_detector_get getbit test_reg 2"
"\n\tsls_detector_get getbit test_bit"
"\n\tsls_detector_put setbit 0x200 2"
"\n\tsls_detector_put setbit test_reg 2"
"\n\tsls_detector_put setbit test_bit"
"\n\tsls_detector_put clearbit test_bit";
os << '\n';
} else {
if (action != defs::GET_ACTION && action != defs::PUT_ACTION) {
throw RuntimeError("Unknown action");
}
auto validate = parseValidate();
auto BitAddress = parseBitAddress();
if (action == defs::GET_ACTION) {
if (cmd == "setbit" || cmd == "clearbit")
throw RuntimeError("Cannot get");
auto t = det->getBit(BitAddress, std::vector<int>{det_id});
os << OutString(t) << '\n';
} else {
if (cmd == "getbit")
throw RuntimeError("Cannot put");
if (cmd == "setbit")
det->setBit(BitAddress, validate, std::vector<int>{det_id});
else if (cmd == "clearbit")
det->clearBit(BitAddress, validate, std::vector<int>{det_id});
else
throw RuntimeError("Unknown command");
os << ToString(args) << "\n";
}
}
return os.str();
}
RegisterAddress Caller::parseAddress(const std::string &saddr) const {
if (is_hex_or_dec_uint(saddr)) {
return RegisterAddress(saddr);
}
auto det_type = det->getDetectorType().squash();
if (det_type != defs::XILINX_CHIPTESTBOARD &&
det_type != defs::CHIPTESTBOARD) {
throw RuntimeError(
"Could not parse address " + saddr +
". User defined register definitions only supported for ctb and "
"xilinx_ctb. Use an actual hard coded address for this detector.");
}
return det->getRegisterDefinitionAddress(saddr);
}
bool Caller::parseValidate() {
auto it = std::find(args.begin(), args.end(), "--validate");
bool validate = (it != args.end());
// throw for any -- options other than --validate
if (!validate) {
auto invalid_it =
std::find_if(args.begin(), args.end(), [](const auto &s) {
// only looks for the first characters
return s.rfind("--", 0) == 0 && s != "--validate";
});
if (invalid_it != args.end()) {
throw RuntimeError("Unknown option '" + *invalid_it +
"'. Did you mean '--validate'?");
}
}
// --validate should be the last argument
else {
if (it != args.end() - 1) {
throw RuntimeError("'--validate' should be the last argument.");
}
args.pop_back();
}
return validate;
}
BitAddress Caller::parseBitAddress() const {
int argsSize = args.size();
std::string addr_or_bitname = args[0];
// bit name
if (argsSize == 1) {
auto det_type = det->getDetectorType().squash();
if (det_type != defs::XILINX_CHIPTESTBOARD &&
det_type != defs::CHIPTESTBOARD) {
throw RuntimeError("Could not parse bit name " + addr_or_bitname +
". User defined bit definitions only supported "
"for ctb and xilinx_ctb. Use an actual hard "
"coded bit position for this detector.");
}
return det->getBitDefinitionAddress(addr_or_bitname);
}
// address and bit position
else if (argsSize == 2) {
std::string bit_pos = args[1];
return BitAddress(parseAddress(addr_or_bitname),
StringTo<int>(bit_pos));
} else {
throw RuntimeError("Command " + cmd +
" expected (1-4) parameter/s but got " +
std::to_string(args.size()) + "\n");
}
}
} // namespace sls

View File

@@ -27,10 +27,6 @@ void CmdParser::Parse(std::string s) {
// taking s by value we can modify it.
Reset();
// If the string is empty there is nothing to parse
if (s.empty())
return;
// Are we looking at -h --help? avoid removing h from command starting
// with h when combined with detector id (ex, 1-hostname)
bool h = replace_first(&s, "--help", " ");

View File

@@ -238,125 +238,4 @@ std::vector<std::string> CtbConfig::getSlowADCNames() const {
const char *CtbConfig::shm_tag() { return shm_tag_; }
int CtbConfig::getRegisterNamesCount() const { return num_regs; }
void CtbConfig::setRegisterName(const std::string &name, RegisterAddress addr) {
addEntry<RegisterDefinition, RegisterAddress>(
name, addr, registers, num_regs, max_regs, "register");
}
bool CtbConfig::hasRegisterName(const std::string &name) const {
return lookupEntryByName<RegisterDefinition, RegisterAddress>(
name, registers, num_regs)
.has_value();
}
bool CtbConfig::hasRegisterAddress(RegisterAddress addr) const {
return lookupEntryByValue<RegisterDefinition, RegisterAddress>(
addr, registers, num_regs)
.has_value();
}
RegisterAddress CtbConfig::getRegisterAddress(const std::string &name) const {
auto val = lookupEntryByName<RegisterDefinition, RegisterAddress>(
name, registers, num_regs);
if (!val.has_value()) {
throw RuntimeError("No register definition found for name: " + name);
}
return val.value();
}
std::string CtbConfig::getRegisterName(RegisterAddress addr) const {
auto val = lookupEntryByValue<RegisterDefinition, RegisterAddress>(
addr, registers, num_regs);
if (!val.has_value()) {
throw RuntimeError("No register definition found for address: " +
addr.str());
}
return val.value();
}
void CtbConfig::clearRegisterNames() {
memset(registers, 0, sizeof(registers));
num_regs = 0;
}
void CtbConfig::setRegisterNames(
const std::map<std::string, RegisterAddress> &list) {
if (list.size() >= max_regs) {
throw RuntimeError("Register names need to be of size less than " +
std::to_string(max_regs));
}
clearRegisterNames();
for (const auto &[name, value] : list) {
setRegisterName(name, value);
}
}
std::map<std::string, RegisterAddress> CtbConfig::getRegisterNames() const {
std::map<std::string, RegisterAddress> names;
for (size_t i = 0; i != num_regs; ++i)
names[registers[i].name()] = registers[i].value();
return names;
}
int CtbConfig::getBitNamesCount() const { return num_bits; }
void CtbConfig::setBitName(const std::string &name, BitAddress bitPos) {
addEntry<BitDefinition, BitAddress>(name, bitPos, bits, num_bits, max_bits,
"bit");
}
bool CtbConfig::hasBitName(const std::string &name) const {
return lookupEntryByName<BitDefinition, BitAddress>(name, bits, num_bits)
.has_value();
}
bool CtbConfig::hasBitAddress(BitAddress bitPos) const {
return lookupEntryByValue<BitDefinition, BitAddress>(bitPos, bits, num_bits)
.has_value();
}
BitAddress CtbConfig::getBitAddress(const std::string &name) const {
auto val =
lookupEntryByName<BitDefinition, BitAddress>(name, bits, num_bits);
if (!val.has_value()) {
throw RuntimeError("No bit definition found for name: " + name);
}
return val.value();
}
std::string CtbConfig::getBitName(BitAddress bitPos) const {
auto val =
lookupEntryByValue<BitDefinition, BitAddress>(bitPos, bits, num_bits);
if (!val.has_value()) {
throw RuntimeError("No bit definition found for bit position: " +
bitPos.str());
}
return val.value();
}
void CtbConfig::clearBitNames() {
memset(bits, 0, sizeof(bits));
num_bits = 0;
}
void CtbConfig::setBitNames(const std::map<std::string, BitAddress> &list) {
if (list.size() >= max_bits) {
throw RuntimeError("Bit names need to be of size less than " +
std::to_string(max_bits));
}
clearBitNames();
for (const auto &[name, value] : list) {
setBitName(name, value);
}
}
std::map<std::string, BitAddress> CtbConfig::getBitNames() const {
std::map<std::string, BitAddress> names;
for (size_t i = 0; i != num_bits; ++i)
names[bits[i].name()] = bits[i].value();
return names;
}
} // namespace sls

View File

@@ -1,61 +1,10 @@
#pragma once
#include "sls/bit_utils.h"
#include "sls/sls_detector_defs.h"
#include "sls/string_utils.h"
#include <map>
#include <optional>
#include <string>
#include <variant>
#include <vector>
namespace sls {
#define CTB_SHMAPIVERSION 0x251031
#define CTB_SHMVERSION 0x251031
#define CTB_NAME_LENGTH 32
class RegisterDefinition {
private:
char name_[CTB_NAME_LENGTH]{};
RegisterAddress addr_;
public:
RegisterDefinition() noexcept = default;
RegisterDefinition(const std::string &name, RegisterAddress address)
: addr_(address) {
if (name.empty()) {
throw sls::RuntimeError("Register name cannot be empty.");
}
strcpy_checked(name_, name);
}
std::string name() const noexcept { return name_; }
RegisterAddress value() const noexcept { return addr_; }
void setValue(RegisterAddress address) noexcept { addr_ = address; }
};
class BitDefinition {
private:
char name_[CTB_NAME_LENGTH]{};
BitAddress bitPos_;
public:
BitDefinition() noexcept = default;
BitDefinition(const std::string &name, BitAddress bitPos)
: bitPos_(bitPos) {
if (name.empty()) {
throw sls::RuntimeError("Bit name cannot be empty.");
}
strcpy_checked(name_, name);
}
std::string name() const noexcept { return name_; }
BitAddress value() const noexcept { return bitPos_; }
void setValue(BitAddress bitPos) noexcept { bitPos_ = bitPos; }
};
#define CTB_SHMAPIVERSION 0x250820
#define CTB_SHMVERSION 0x250820
class CtbConfig {
public:
@@ -64,26 +13,19 @@ class CtbConfig {
bool isValid{true}; // false if freed to block access from python or c++ api
/** end of fixed pattern */
private:
static constexpr const char *shm_tag_ = "ctbdacs";
static constexpr size_t name_length = CTB_NAME_LENGTH;
static constexpr size_t name_length = 20;
static constexpr size_t num_dacs = 18;
static constexpr size_t num_adcs = 32;
static constexpr size_t num_signals = 64;
static constexpr size_t num_powers = 5;
static constexpr size_t num_slowADCs = 8;
static constexpr const char *shm_tag_ = "ctbdacs";
char dacnames[name_length * num_dacs]{};
char adcnames[name_length * num_adcs]{};
char signalnames[name_length * num_signals]{};
char powernames[name_length * num_powers]{};
char slowADCnames[name_length * num_slowADCs]{};
static constexpr size_t max_regs = 64;
static constexpr size_t max_bits = 64;
size_t num_regs{0};
size_t num_bits{0};
RegisterDefinition registers[max_regs];
BitDefinition bits[max_bits];
void check_dac_index(size_t i) const;
void check_adc_index(size_t i) const;
void check_signal_index(size_t i) const;
@@ -91,99 +33,12 @@ class CtbConfig {
void check_slow_adc_index(size_t i) const;
void check_size(const std::string &name) const;
template <typename T>
std::optional<T *> findEntryByName(const std::string &name, T *array,
size_t count) {
auto it = std::find_if(array, array + count,
[&name](T &e) { return (e.name() == name); });
if (it != array + count)
return it;
return std::nullopt;
}
template <typename T>
std::optional<const T *> findEntryByName(const std::string &name,
const T *array,
size_t count) const {
auto it = std::find_if(array, array + count, [&name](const T &e) {
return (e.name() == name);
});
if (it != array + count)
return it;
return std::nullopt;
}
template <typename T, typename Tval>
std::optional<T *> findEntryByValue(Tval value, T *array, size_t count) {
auto it = std::find_if(array, array + count,
[&value](T &e) { return e.value() == value; });
if (it != array + count)
return it;
return std::nullopt;
}
template <typename T, typename Tval>
std::optional<const T *> findEntryByValue(Tval value, const T *array,
size_t count) const {
auto it = std::find_if(array, array + count, [&value](const T &e) {
return e.value() == value;
});
if (it != array + count)
return it;
return std::nullopt;
}
template <typename T, typename Tval>
std::optional<const Tval> lookupEntryByName(const std::string &name,
const T *array,
size_t count) const {
auto entry = findEntryByName<T>(name, array, count);
return (entry ? std::optional<Tval>((*entry)->value()) : std::nullopt);
}
template <typename T, typename Tval>
std::optional<std::string> lookupEntryByValue(Tval value, const T *array,
size_t count) const {
auto entry = findEntryByValue<T>(value, array, count);
return (entry ? std::optional<std::string>((*entry)->name())
: std::nullopt);
}
template <typename T, typename Tval>
void addEntry(const std::string &name, Tval value, T *array, size_t &count,
size_t max_count, const std::string &type_name) {
check_size(name);
// exists: overwrite value
if (auto entry = findEntryByName<T>(name, array, count)) {
(*entry)->setValue(value);
return;
}
// check size
if (count >= max_count) {
throw RuntimeError("Maximum number of " + type_name +
" reached. Clear shared memory and try again.");
}
// check value exists
if (auto entry = findEntryByValue<T>(value, array, count)) {
throw RuntimeError(value.str() + " already assigned to " +
type_name + " '" + (*entry)->name() +
"'. Cannot assign to '" + name + "'");
}
// add new entry
array[count] = T(name, value);
++(count);
}
public:
CtbConfig();
CtbConfig(const CtbConfig &) = default;
CtbConfig(CtbConfig &&) = default;
CtbConfig &operator=(const CtbConfig &) = default;
~CtbConfig() = default;
void setDacNames(const std::vector<std::string> &names);
void setDacName(size_t index, const std::string &name);
@@ -210,26 +65,6 @@ class CtbConfig {
std::string getSlowADCName(size_t index) const;
std::vector<std::string> getSlowADCNames() const;
static const char *shm_tag();
int getRegisterNamesCount() const;
void setRegisterName(const std::string &name, RegisterAddress addr);
bool hasRegisterName(const std::string &name) const;
bool hasRegisterAddress(RegisterAddress addr) const;
RegisterAddress getRegisterAddress(const std::string &name) const;
std::string getRegisterName(RegisterAddress addr) const;
void clearRegisterNames();
void setRegisterNames(const std::map<std::string, RegisterAddress> &list);
std::map<std::string, RegisterAddress> getRegisterNames() const;
int getBitNamesCount() const;
void setBitName(const std::string &name, BitAddress bitPos);
bool hasBitName(const std::string &name) const;
bool hasBitAddress(BitAddress bitPos) const;
BitAddress getBitAddress(const std::string &name) const;
std::string getBitName(BitAddress bitPos) const;
void clearBitNames();
void setBitNames(const std::map<std::string, BitAddress> &list);
std::map<std::string, BitAddress> getBitNames() const;
};
} // namespace sls

View File

@@ -2377,21 +2377,26 @@ void Detector::setLEDEnable(bool enable, Positions pos) {
}
void Detector::setDacNames(const std::vector<std::string> names) {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named dacs only for CTB");
pimpl->setCtbDacNames(names);
}
std::vector<std::string> Detector::getDacNames() const {
if (pimpl->isChipTestBoard())
std::vector<std::string> names;
auto type = getDetectorType().squash();
if (type == defs::CHIPTESTBOARD || type == defs::XILINX_CHIPTESTBOARD)
return pimpl->getCtbDacNames();
std::vector<std::string> names;
for (const auto &index : getDacList())
names.push_back(ToString(index));
return names;
}
defs::dacIndex Detector::getDacIndex(const std::string &name) const {
if (pimpl->isChipTestBoard()) {
auto type = getDetectorType().squash();
if (type == defs::CHIPTESTBOARD || type == defs::XILINX_CHIPTESTBOARD) {
auto names = getDacNames();
auto it = std::find(names.begin(), names.end(), name);
if (it == names.end())
@@ -2402,24 +2407,37 @@ defs::dacIndex Detector::getDacIndex(const std::string &name) const {
}
void Detector::setDacName(const defs::dacIndex i, const std::string &name) {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named dacs only for CTB");
pimpl->setCtbDacName(i, name);
}
std::string Detector::getDacName(const defs::dacIndex i) const {
if (pimpl->isChipTestBoard())
auto dettype = getDetectorType().squash();
if (dettype == defs::CHIPTESTBOARD || dettype == defs::XILINX_CHIPTESTBOARD)
return pimpl->getCtbDacName(i);
return ToString(i);
}
void Detector::setAdcNames(const std::vector<std::string> names) {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named adcs only for CTB");
pimpl->setCtbAdcNames(names);
}
std::vector<std::string> Detector::getAdcNames() const {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named adcs only for CTB");
return pimpl->getCtbAdcNames();
}
int Detector::getAdcIndex(const std::string &name) const {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named adcs only for CTB");
auto names = getAdcNames();
auto it = std::find(names.begin(), names.end(), name);
if (it == names.end())
@@ -2428,22 +2446,37 @@ int Detector::getAdcIndex(const std::string &name) const {
}
void Detector::setAdcName(const int index, const std::string &name) {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named adcs only for CTB");
pimpl->setCtbAdcName(index, name);
}
std::string Detector::getAdcName(const int i) const {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named adcs only for CTB");
return pimpl->getCtbAdcName(i);
}
void Detector::setSignalNames(const std::vector<std::string> names) {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named signals only for CTB");
pimpl->setCtbSignalNames(names);
}
std::vector<std::string> Detector::getSignalNames() const {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named signals only for CTB");
return pimpl->getCtbSignalNames();
}
int Detector::getSignalIndex(const std::string &name) const {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named signals only for CTB");
auto names = getSignalNames();
auto it = std::find(names.begin(), names.end(), name);
if (it == names.end())
@@ -2452,22 +2485,38 @@ int Detector::getSignalIndex(const std::string &name) const {
}
void Detector::setSignalName(const int index, const std::string &name) {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named signals only for CTB");
pimpl->setCtbSignalName(index, name);
}
std::string Detector::getSignalName(const int i) const {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named signals only for CTB");
return pimpl->getCtbSignalName(i);
}
void Detector::setPowerNames(const std::vector<std::string> names) {
auto dettype = getDetectorType().squash();
if (getDetectorType().squash() != defs::CHIPTESTBOARD &&
dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named powers only for CTB");
pimpl->setCtbPowerNames(names);
}
std::vector<std::string> Detector::getPowerNames() const {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named powers only for CTB");
return pimpl->getCtbPowerNames();
}
defs::dacIndex Detector::getPowerIndex(const std::string &name) const {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named powers only for CTB");
auto names = getPowerNames();
auto it = std::find(names.begin(), names.end(), name);
if (it == names.end())
@@ -2477,22 +2526,37 @@ defs::dacIndex Detector::getPowerIndex(const std::string &name) const {
void Detector::setPowerName(const defs::dacIndex index,
const std::string &name) {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named powers only for CTB");
pimpl->setCtbPowerName(index, name);
}
std::string Detector::getPowerName(const defs::dacIndex i) const {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named powers only for CTB");
return pimpl->getCtbPowerName(i);
}
void Detector::setSlowADCNames(const std::vector<std::string> names) {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named SlowADCs only for CTB");
pimpl->setCtbSlowADCNames(names);
}
std::vector<std::string> Detector::getSlowADCNames() const {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named SlowADCs only for CTB");
return pimpl->getCtbSlowADCNames();
}
defs::dacIndex Detector::getSlowADCIndex(const std::string &name) const {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named SlowADCs only for CTB");
auto names = getSlowADCNames();
auto it = std::find(names.begin(), names.end(), name);
if (it == names.end())
@@ -2502,86 +2566,19 @@ defs::dacIndex Detector::getSlowADCIndex(const std::string &name) const {
void Detector::setSlowADCName(const defs::dacIndex index,
const std::string &name) {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named SlowADCs only for CTB");
pimpl->setCtbSlowADCName(index, name);
}
std::string Detector::getSlowADCName(const defs::dacIndex i) const {
auto dettype = getDetectorType().squash();
if (dettype != defs::CHIPTESTBOARD && dettype != defs::XILINX_CHIPTESTBOARD)
throw RuntimeError("Named SlowADCs only for CTB");
return pimpl->getCtbSlowADCName(i);
}
int Detector::getRegisterDefinitionsCount() const {
return pimpl->getRegisterDefinitionsCount();
}
void Detector::setRegisterDefinition(const std::string &name,
RegisterAddress addr) {
pimpl->setRegisterDefinition(name, addr);
}
bool Detector::hasRegisterDefinition(const std::string &name) const {
return pimpl->hasRegisterDefinition(name);
}
bool Detector::hasRegisterDefinition(RegisterAddress addr) const {
return pimpl->hasRegisterDefinition(addr);
}
RegisterAddress
Detector::getRegisterDefinitionAddress(const std::string &name) const {
return pimpl->getRegisterDefinitionAddress(name);
}
std::string Detector::getRegisterDefinitionName(RegisterAddress addr) const {
return pimpl->getRegisterDefinitionName(addr);
}
void Detector::clearRegisterDefinitions() { pimpl->clearRegisterDefinitions(); }
void Detector::setRegisterDefinitions(
const std::map<std::string, RegisterAddress> &list) {
pimpl->setRegisterDefinitions(list);
}
std::map<std::string, RegisterAddress>
Detector::getRegisterDefinitions() const {
return pimpl->getRegisterDefinitions();
}
int Detector::getBitDefinitionsCount() const {
return pimpl->getBitDefinitionsCount();
}
void Detector::setBitDefinition(const std::string &name, BitAddress addr) {
pimpl->setBitDefinition(name, addr);
}
bool Detector::hasBitDefinition(const std::string &name) const {
return pimpl->hasBitDefinition(name);
}
bool Detector::hasBitDefinition(BitAddress addr) const {
return pimpl->hasBitDefinition(addr);
}
BitAddress Detector::getBitDefinitionAddress(const std::string &name) const {
return pimpl->getBitDefinitionAddress(name);
}
std::string Detector::getBitDefinitionName(BitAddress addr) const {
return pimpl->getBitDefinitionName(addr);
}
void Detector::clearBitDefinitions() { pimpl->clearBitDefinitions(); }
void Detector::setBitDefinitions(
const std::map<std::string, BitAddress> &list) {
pimpl->setBitDefinitions(list);
}
std::map<std::string, BitAddress> Detector::getBitDefinitions() const {
return pimpl->getBitDefinitions();
}
// Xilinx Ctb Specific
void Detector::configureTransceiver(Positions pos) {
@@ -2785,78 +2782,26 @@ void Detector::setUpdateMode(const bool updatemode, Positions pos) {
}
}
Result<RegisterValue> Detector::readRegister(RegisterAddress addr,
Positions pos) const {
return pimpl->readRegister(addr, pos);
}
void Detector::writeRegister(RegisterAddress addr, RegisterValue val,
bool validate, Positions pos) {
pimpl->writeRegister(addr, val, validate, pos);
}
void Detector::setBit(BitAddress addr, bool validate, Positions pos) {
pimpl->setBit(addr, validate, pos);
}
void Detector::clearBit(BitAddress addr, bool validate, Positions pos) {
pimpl->clearBit(addr, validate, pos);
}
Result<int> Detector::getBit(BitAddress addr, Positions pos) const {
return pimpl->getBit(addr, pos);
}
Result<RegisterValue> Detector::readRegister(const std::string &reg_name,
Positions pos) const {
return pimpl->readRegister(reg_name, pos);
}
void Detector::writeRegister(const std::string &reg_name, RegisterValue val,
bool validate, Positions pos) {
pimpl->writeRegister(reg_name, val, validate, pos);
}
void Detector::setBit(const std::string &bit_name, bool validate,
Positions pos) {
pimpl->setBit(bit_name, validate, pos);
}
void Detector::clearBit(const std::string &bit_name, bool validate,
Positions pos) {
pimpl->clearBit(bit_name, validate, pos);
}
Result<int> Detector::getBit(const std::string &bit_name, Positions pos) const {
return pimpl->getBit(bit_name, pos);
}
Result<uint32_t> Detector::readRegister(uint32_t addr, Positions pos) const {
auto t = pimpl->readRegister(RegisterAddress(addr), pos);
Result<uint32_t> res;
for (const auto &val : t) {
res.push_back(val);
}
return res;
return pimpl->Parallel(&Module::readRegister, pos, addr);
}
void Detector::writeRegister(uint32_t addr, uint32_t val, bool validate,
Positions pos) {
pimpl->writeRegister(RegisterAddress(addr), RegisterValue(val), validate,
pos);
pimpl->Parallel(&Module::writeRegister, pos, addr, val, validate);
}
void Detector::setBit(uint32_t addr, int bitnr, bool validate, Positions pos) {
pimpl->setBit(BitAddress(RegisterAddress(addr), bitnr), validate, pos);
pimpl->Parallel(&Module::setBit, pos, addr, bitnr, validate);
}
void Detector::clearBit(uint32_t addr, int bitnr, bool validate,
Positions pos) {
pimpl->clearBit(BitAddress(RegisterAddress(addr), bitnr), validate, pos);
pimpl->Parallel(&Module::clearBit, pos, addr, bitnr, validate);
}
Result<int> Detector::getBit(uint32_t addr, int bitnr, Positions pos) const {
return pimpl->getBit(BitAddress(RegisterAddress(addr), bitnr), pos);
Result<int> Detector::getBit(uint32_t addr, int bitnr, Positions pos) {
return pimpl->Parallel(&Module::getBit, pos, addr, bitnr);
}
void Detector::executeFirmwareTest(Positions pos) {

View File

@@ -1935,314 +1935,86 @@ void DetectorImpl::setBadChannels(const std::vector<int> list, Positions pos) {
}
std::vector<std::string> DetectorImpl::getCtbDacNames() const {
if (!isChipTestBoard())
throw RuntimeError("Named DACs only for CTB");
return ctb_shm()->getDacNames();
}
void DetectorImpl::setCtbDacNames(const std::vector<std::string> &names) {
if (!isChipTestBoard())
throw RuntimeError("Named DACs only for CTB");
ctb_shm()->setDacNames(names);
}
std::string DetectorImpl::getCtbDacName(defs::dacIndex i) const {
if (!isChipTestBoard())
throw RuntimeError("Named DACs only for CTB");
return ctb_shm()->getDacName(static_cast<int>(i));
}
void DetectorImpl::setCtbDacName(const defs::dacIndex index,
const std::string &name) {
if (!isChipTestBoard())
throw RuntimeError("Named DACs only for CTB");
ctb_shm()->setDacName(index, name);
}
std::vector<std::string> DetectorImpl::getCtbAdcNames() const {
if (!isChipTestBoard())
throw RuntimeError("Named ADCs only for CTB");
return ctb_shm()->getAdcNames();
}
void DetectorImpl::setCtbAdcNames(const std::vector<std::string> &names) {
if (!isChipTestBoard())
throw RuntimeError("Named ADCs only for CTB");
ctb_shm()->setAdcNames(names);
}
std::string DetectorImpl::getCtbAdcName(const int i) const {
if (!isChipTestBoard())
throw RuntimeError("Named ADCs only for CTB");
return ctb_shm()->getAdcName(i);
}
void DetectorImpl::setCtbAdcName(const int index, const std::string &name) {
if (!isChipTestBoard())
throw RuntimeError("Named ADCs only for CTB");
ctb_shm()->setAdcName(index, name);
}
std::vector<std::string> DetectorImpl::getCtbSignalNames() const {
if (!isChipTestBoard())
throw RuntimeError("Named signals only for CTB");
return ctb_shm()->getSignalNames();
}
void DetectorImpl::setCtbSignalNames(const std::vector<std::string> &names) {
if (!isChipTestBoard())
throw RuntimeError("Named signals only for CTB");
ctb_shm()->setSignalNames(names);
}
std::string DetectorImpl::getCtbSignalName(const int i) const {
if (!isChipTestBoard())
throw RuntimeError("Named signals only for CTB");
return ctb_shm()->getSignalName(i);
}
void DetectorImpl::setCtbSignalName(const int index, const std::string &name) {
if (!isChipTestBoard())
throw RuntimeError("Named signals only for CTB");
ctb_shm()->setSignalName(index, name);
}
std::vector<std::string> DetectorImpl::getCtbPowerNames() const {
if (!isChipTestBoard())
throw RuntimeError("Named Powers only for CTB");
return ctb_shm()->getPowerNames();
}
void DetectorImpl::setCtbPowerNames(const std::vector<std::string> &names) {
if (!isChipTestBoard())
throw RuntimeError("Named Powers only for CTB");
ctb_shm()->setPowerNames(names);
}
std::string DetectorImpl::getCtbPowerName(const defs::dacIndex i) const {
if (!isChipTestBoard())
throw RuntimeError("Named Powers only for CTB");
return ctb_shm()->getPowerName(static_cast<int>(i - defs::V_POWER_A));
}
void DetectorImpl::setCtbPowerName(const defs::dacIndex index,
const std::string &name) {
if (!isChipTestBoard())
throw RuntimeError("Named Powers only for CTB");
ctb_shm()->setPowerName(static_cast<int>(index - defs::V_POWER_A), name);
}
std::vector<std::string> DetectorImpl::getCtbSlowADCNames() const {
if (!isChipTestBoard())
throw RuntimeError("Named Slow ADCs only for CTB");
return ctb_shm()->getSlowADCNames();
}
void DetectorImpl::setCtbSlowADCNames(const std::vector<std::string> &names) {
if (!isChipTestBoard())
throw RuntimeError("Named Slow ADCs only for CTB");
ctb_shm()->setSlowADCNames(names);
}
std::string DetectorImpl::getCtbSlowADCName(const defs::dacIndex i) const {
if (!isChipTestBoard())
throw RuntimeError("Named Slow ADCs only for CTB");
return ctb_shm()->getSlowADCName(static_cast<int>(i - defs::SLOW_ADC0));
}
void DetectorImpl::setCtbSlowADCName(const defs::dacIndex index,
const std::string &name) {
if (!isChipTestBoard())
throw RuntimeError("Named Slow ADCs only for CTB");
ctb_shm()->setSlowADCName(static_cast<int>(index - defs::SLOW_ADC0), name);
}
int DetectorImpl::getRegisterDefinitionsCount() const {
if (!isChipTestBoard())
throw RuntimeError("Register Definitions only for CTB");
return ctb_shm()->getRegisterNamesCount();
}
void DetectorImpl::setRegisterDefinition(const std::string &name,
RegisterAddress addr) {
if (!isChipTestBoard())
throw RuntimeError("Register Definitions only for CTB");
ctb_shm()->setRegisterName(name, addr);
}
bool DetectorImpl::hasRegisterDefinition(const std::string &name) const {
if (!isChipTestBoard())
throw RuntimeError("Register Definitions only for CTB");
return ctb_shm()->hasRegisterName(name);
}
bool DetectorImpl::hasRegisterDefinition(RegisterAddress addr) const {
if (!isChipTestBoard())
throw RuntimeError("Register Definitions only for CTB");
return ctb_shm()->hasRegisterAddress(addr);
}
RegisterAddress
DetectorImpl::getRegisterDefinitionAddress(const std::string &name) const {
if (!isChipTestBoard())
throw RuntimeError("Register Definitions only for CTB");
return ctb_shm()->getRegisterAddress(name);
}
std::string
DetectorImpl::getRegisterDefinitionName(RegisterAddress addr) const {
if (!isChipTestBoard())
throw RuntimeError("Register Definitions only for CTB");
return ctb_shm()->getRegisterName(addr);
}
void DetectorImpl::clearRegisterDefinitions() {
if (!isChipTestBoard())
throw RuntimeError("Register Definitions only for CTB");
ctb_shm()->clearRegisterNames();
}
void DetectorImpl::setRegisterDefinitions(
const std::map<std::string, RegisterAddress> &list) {
if (!isChipTestBoard())
throw RuntimeError("Register Definitions only for CTB");
ctb_shm()->setRegisterNames(list);
}
std::map<std::string, RegisterAddress>
DetectorImpl::getRegisterDefinitions() const {
if (!isChipTestBoard())
throw RuntimeError("Register Definitions only for CTB");
return ctb_shm()->getRegisterNames();
}
int DetectorImpl::getBitDefinitionsCount() const {
if (!isChipTestBoard())
throw RuntimeError("Bit Definitions only for CTB");
return ctb_shm()->getBitNamesCount();
}
void DetectorImpl::setBitDefinition(const std::string &name,
BitAddress bitPos) {
if (!isChipTestBoard())
throw RuntimeError("Bit Definitions only for CTB");
ctb_shm()->setBitName(name, bitPos);
}
bool DetectorImpl::hasBitDefinition(const std::string &name) const {
if (!isChipTestBoard())
throw RuntimeError("Bit Definitions only for CTB");
return ctb_shm()->hasBitName(name);
}
bool DetectorImpl::hasBitDefinition(BitAddress bitPos) const {
if (!isChipTestBoard())
throw RuntimeError("Bit Definitions only for CTB");
return ctb_shm()->hasBitAddress(bitPos);
}
BitAddress
DetectorImpl::getBitDefinitionAddress(const std::string &name) const {
if (!isChipTestBoard())
throw RuntimeError("Bit Definitions only for CTB");
return ctb_shm()->getBitAddress(name);
}
std::string DetectorImpl::getBitDefinitionName(BitAddress bitPos) const {
if (!isChipTestBoard())
throw RuntimeError("Bit Definitions only for CTB");
return ctb_shm()->getBitName(bitPos);
}
void DetectorImpl::clearBitDefinitions() {
if (!isChipTestBoard())
throw RuntimeError("Bit Definitions only for CTB");
ctb_shm()->clearBitNames();
}
void DetectorImpl::setBitDefinitions(
const std::map<std::string, BitAddress> &list) {
if (!isChipTestBoard())
throw RuntimeError("Bit Definitions only for CTB");
ctb_shm()->setBitNames(list);
}
std::map<std::string, BitAddress> DetectorImpl::getBitDefinitions() const {
if (!isChipTestBoard())
throw RuntimeError("Bit Definitions only for CTB");
return ctb_shm()->getBitNames();
}
Result<RegisterValue> DetectorImpl::readRegister(const std::string &reg_name,
Positions pos) const {
if (!isChipTestBoard()) {
throw RuntimeError("Register Definitions only for CTB. Use hard coded "
"values instead.");
}
auto addr = getRegisterDefinitionAddress(reg_name);
return readRegister(addr, pos);
}
void DetectorImpl::writeRegister(const std::string &reg_name, RegisterValue val,
bool validate, Positions pos) {
if (!isChipTestBoard()) {
throw RuntimeError("Register Definitions only for CTB. Use hard coded "
"values instead.");
}
auto addr = getRegisterDefinitionAddress(reg_name);
writeRegister(addr, val, validate, pos);
}
void DetectorImpl::setBit(const std::string &bit_name, bool validate,
Positions pos) {
if (!isChipTestBoard()) {
throw RuntimeError(
"Bit Definitions only for CTB. Use hard coded values instead.");
}
auto addr = getBitDefinitionAddress(bit_name);
setBit(addr, validate, pos);
}
void DetectorImpl::clearBit(const std::string &bit_name, bool validate,
Positions pos) {
if (!isChipTestBoard()) {
throw RuntimeError(
"Bit Definitions only for CTB. Use hard coded values instead.");
}
auto addr = getBitDefinitionAddress(bit_name);
clearBit(addr, validate, pos);
}
Result<int> DetectorImpl::getBit(const std::string &bit_name,
Positions pos) const {
if (!isChipTestBoard()) {
throw RuntimeError(
"Bit Definitions only for CTB. Use hard coded values instead.");
}
auto addr = getBitDefinitionAddress(bit_name);
return getBit(addr, pos);
}
Result<RegisterValue> DetectorImpl::readRegister(RegisterAddress addr,
Positions pos) const {
return Parallel(&Module::readRegister, pos, addr);
}
void DetectorImpl::writeRegister(RegisterAddress addr, RegisterValue val,
bool validate, Positions pos) {
Parallel(&Module::writeRegister, pos, addr, val, validate);
}
void DetectorImpl::setBit(BitAddress addr, bool validate, Positions pos) {
Parallel(&Module::setBit, pos, addr, validate);
}
void DetectorImpl::clearBit(BitAddress addr, bool validate, Positions pos) {
Parallel(&Module::clearBit, pos, addr, validate);
}
Result<int> DetectorImpl::getBit(BitAddress addr, Positions pos) const {
return Parallel(&Module::getBit, pos, addr);
}
} // namespace sls

View File

@@ -183,11 +183,6 @@ class DetectorImpl : public virtual slsDetectorDefs {
bool isAllPositions(Positions pos) const;
inline bool isChipTestBoard() const {
return (shm()->detType == defs::CHIPTESTBOARD ||
shm()->detType == defs::XILINX_CHIPTESTBOARD);
}
/** set acquiring flag in shared memory */
void setAcquiringFlag(bool flag);
@@ -333,42 +328,6 @@ class DetectorImpl : public virtual slsDetectorDefs {
void setCtbSlowADCNames(const std::vector<std::string> &names);
void setCtbSlowADCName(const defs::dacIndex index, const std::string &name);
int getRegisterDefinitionsCount() const;
void setRegisterDefinition(const std::string &name, RegisterAddress addr);
bool hasRegisterDefinition(const std::string &name) const;
bool hasRegisterDefinition(RegisterAddress addr) const;
RegisterAddress getRegisterDefinitionAddress(const std::string &name) const;
std::string getRegisterDefinitionName(RegisterAddress addr) const;
void clearRegisterDefinitions();
void
setRegisterDefinitions(const std::map<std::string, RegisterAddress> &list);
std::map<std::string, RegisterAddress> getRegisterDefinitions() const;
int getBitDefinitionsCount() const;
void setBitDefinition(const std::string &name, BitAddress bitPos);
bool hasBitDefinition(const std::string &name) const;
bool hasBitDefinition(BitAddress bitPos) const;
BitAddress getBitDefinitionAddress(const std::string &name) const;
std::string getBitDefinitionName(BitAddress bitPos) const;
void clearBitDefinitions();
void setBitDefinitions(const std::map<std::string, BitAddress> &list);
std::map<std::string, BitAddress> getBitDefinitions() const;
Result<RegisterValue> readRegister(const std::string &reg_name,
Positions pos) const;
void writeRegister(const std::string &reg_name, RegisterValue val,
bool validate, Positions pos);
void setBit(const std::string &bit_name, bool validate, Positions pos);
void clearBit(const std::string &bit_name, bool validate, Positions pos);
Result<int> getBit(const std::string &bit_name, Positions pos) const;
Result<RegisterValue> readRegister(RegisterAddress addr,
Positions pos = {}) const;
void writeRegister(RegisterAddress addr, RegisterValue val,
bool validate = false, Positions pos = {});
void setBit(BitAddress addr, bool validate = false, Positions pos = {});
void clearBit(BitAddress addr, bool validate = false, Positions pos = {});
Result<int> getBit(BitAddress addr, Positions pos = {}) const;
private:
/**
* Creates/open shared memory, initializes detector structure and members

View File

@@ -1202,7 +1202,7 @@ void Module::setDestinationUDPIP(const IpAddr ip) {
}
sendToDetector(F_SET_DEST_UDP_IP, ip, nullptr);
if (shm()->useReceiverFlag) {
MacAddr retval;
MacAddr retval(0LU);
sendToReceiver(F_SET_RECEIVER_UDP_IP, ip, retval);
LOG(logINFO) << "Setting destination udp mac of Module " << moduleIndex
<< " to " << retval;
@@ -1225,7 +1225,7 @@ void Module::setDestinationUDPIP2(const IpAddr ip) {
}
sendToDetector(F_SET_DEST_UDP_IP2, ip, nullptr);
if (shm()->useReceiverFlag) {
MacAddr retval;
MacAddr retval(0LU);
sendToReceiver(F_SET_RECEIVER_UDP_IP2, ip, retval);
LOG(logINFO) << "Setting destination udp mac2 of Module " << moduleIndex
<< " to " << retval;
@@ -2568,16 +2568,17 @@ std::vector<int> Module::getReceiverDbitList() const {
void Module::setReceiverDbitList(std::vector<int> list) {
LOG(logDEBUG1) << "Setting Receiver Dbit List";
if (list.size() > 64) {
throw RuntimeError("Dbit list size cannot be greater than 64\n");
}
for (auto &it : list) {
if (it < 0 || it > 63) {
throw RuntimeError("Dbit list value must be between 0 and 63\n");
}
}
auto r = stableRemoveDuplicates(list);
if (r) {
LOG(logWARNING) << "Removed duplicated from receiver dbit list";
}
std::sort(begin(list), end(list));
auto last = std::unique(begin(list), end(list));
list.erase(last, list.end());
StaticVector<int, MAX_RX_DBIT> arg = list;
sendToReceiver(F_SET_RECEIVER_DBIT_LIST, arg, nullptr);
@@ -2915,33 +2916,29 @@ void Module::setUpdateMode(const bool updatemode) {
<< "): Update Mode set to " << updatemode << "!";
}
RegisterValue Module::readRegister(RegisterAddress addr) const {
return sendToDetectorStop<RegisterValue>(F_READ_REGISTER, addr);
uint32_t Module::readRegister(uint32_t addr) const {
return sendToDetectorStop<uint32_t>(F_READ_REGISTER, addr);
}
void Module::writeRegister(RegisterAddress addr, RegisterValue val,
bool validate) {
void Module::writeRegister(uint32_t addr, uint32_t val, bool validate) {
uint32_t args[]{addr, val, static_cast<uint32_t>(validate)};
return sendToDetectorStop(F_WRITE_REGISTER, args, nullptr);
}
void Module::setBit(BitAddress bitAddr, bool validate) {
uint32_t args[] = {bitAddr.address(),
static_cast<uint32_t>(bitAddr.bitPosition()),
void Module::setBit(uint32_t addr, int n, bool validate) {
uint32_t args[] = {addr, static_cast<uint32_t>(n),
static_cast<uint32_t>(validate)};
sendToDetectorStop(F_SET_BIT, args, nullptr);
}
void Module::clearBit(BitAddress bitAddr, bool validate) {
uint32_t args[] = {bitAddr.address(),
static_cast<uint32_t>(bitAddr.bitPosition()),
void Module::clearBit(uint32_t addr, int n, bool validate) {
uint32_t args[] = {addr, static_cast<uint32_t>(n),
static_cast<uint32_t>(validate)};
sendToDetectorStop(F_CLEAR_BIT, args, nullptr);
}
int Module::getBit(BitAddress bitAddr) const {
uint32_t args[2] = {bitAddr.address(),
static_cast<uint32_t>(bitAddr.bitPosition())};
int Module::getBit(uint32_t addr, int n) {
uint32_t args[2] = {addr, static_cast<uint32_t>(n)};
return sendToDetectorStop<int>(F_GET_BIT, args);
}

View File

@@ -5,7 +5,6 @@
#include "sls/ClientSocket.h"
#include "sls/Pattern.h"
#include "sls/StaticVector.h"
#include "sls/bit_utils.h"
#include "sls/logger.h"
#include "sls/network_utils.h"
#include "sls/sls_detector_defs.h"
@@ -580,11 +579,11 @@ class Module : public virtual slsDetectorDefs {
void rebootController();
bool getUpdateMode() const;
void setUpdateMode(const bool updatemode);
RegisterValue readRegister(RegisterAddress addr) const;
void writeRegister(RegisterAddress addr, RegisterValue val, bool validate);
void setBit(BitAddress bitAddr, bool validate);
void clearBit(BitAddress bitAddr, bool validate);
int getBit(BitAddress bitAddr) const;
uint32_t readRegister(uint32_t addr) const;
void writeRegister(uint32_t addr, uint32_t val, bool validate);
void setBit(uint32_t addr, int n, bool validate);
void clearBit(uint32_t addr, int n, bool validate);
int getBit(uint32_t addr, int n);
void executeFirmwareTest();
void executeBusTest();
void writeAdcRegister(uint32_t addr, uint32_t val);

View File

@@ -25,26 +25,15 @@
#include <sys/stat.h> // fstat
#include <unistd.h>
// ********************** Defines for shared memory. **********************
// WARNING! before chaning these search the codebase for their usage!
#define SHM_IS_VALID_CHECK_VERSION 0x250820
// Max shared memory name length in macOS is 31 characters
#ifdef __APPLE__
#define SHM_DETECTOR_PREFIX "/sls_"
#define SHM_MODULE_PREFIX "_mod_"
#else
#define SHM_DETECTOR_PREFIX "/slsDetectorPackage_detector_"
#define SHM_MODULE_PREFIX "_module_"
#endif
#define SHM_ENV_NAME "SLSDETNAME"
// ************************************************************************
namespace sls {
class CtbConfig;
struct CtbConfig;
// struct sharedDetector;
#define SHM_IS_VALID_CHECK_VERSION 0x250820
#define SHM_DETECTOR_PREFIX "/slsDetectorPackage_detector_"
#define SHM_MODULE_PREFIX "_module_"
#define SHM_ENV_NAME "SLSDETNAME"
template <typename T, typename U> constexpr bool is_type() {
return std::is_same_v<std::decay_t<U>, T>;
@@ -278,12 +267,6 @@ template <typename T> class SharedMemory {
throw SharedMemoryError(msg);
}
#ifdef __APPLE__
// On macOS, fstat returns the allocated size and not the requested
// size. This means we can't check for size since we always get for
// example 16384 bytes.
return;
#endif
auto actual_size = static_cast<size_t>(sb.st_size);
auto expected_size = sizeof(T);
if (actual_size != expected_size) {

View File

@@ -400,10 +400,6 @@ int InferAction::chipversion() {
int InferAction::clearbit() {
if (args.size() == 1) {
return slsDetectorDefs::PUT_ACTION;
}
if (args.size() == 2) {
return slsDetectorDefs::PUT_ACTION;
}
@@ -792,66 +788,6 @@ int InferAction::defaultpattern() {
}
}
int InferAction::define_bit() {
if (args.size() == 1) {
return slsDetectorDefs::GET_ACTION;
}
if (args.size() == 2) {
return slsDetectorDefs::GET_ACTION;
}
if (args.size() == 3) {
return slsDetectorDefs::PUT_ACTION;
}
else {
throw RuntimeError("Could not infer action: Wrong number of arguments");
}
}
int InferAction::define_reg() {
if (args.size() == 1) {
return slsDetectorDefs::GET_ACTION;
}
if (args.size() == 2) {
return slsDetectorDefs::PUT_ACTION;
}
else {
throw RuntimeError("Could not infer action: Wrong number of arguments");
}
}
int InferAction::definelist_bit() {
if (args.size() == 0) {
return slsDetectorDefs::GET_ACTION;
}
else {
throw RuntimeError("Could not infer action: Wrong number of arguments");
}
}
int InferAction::definelist_reg() {
if (args.size() == 0) {
return slsDetectorDefs::GET_ACTION;
}
else {
throw RuntimeError("Could not infer action: Wrong number of arguments");
}
}
int InferAction::delay() {
if (args.size() == 0) {
@@ -1562,10 +1498,6 @@ int InferAction::gates() {
int InferAction::getbit() {
if (args.size() == 1) {
return slsDetectorDefs::GET_ACTION;
}
if (args.size() == 2) {
return slsDetectorDefs::GET_ACTION;
}
@@ -3123,10 +3055,6 @@ int InferAction::serialnumber() {
int InferAction::setbit() {
if (args.size() == 1) {
return slsDetectorDefs::PUT_ACTION;
}
if (args.size() == 2) {
return slsDetectorDefs::PUT_ACTION;
}

View File

@@ -62,10 +62,6 @@ class InferAction {
int dbitpipeline();
int defaultdac();
int defaultpattern();
int define_bit();
int define_reg();
int definelist_bit();
int definelist_reg();
int delay();
int delayl();
int detectorserverversion();
@@ -398,10 +394,6 @@ class InferAction {
{"dbitpipeline", &InferAction::dbitpipeline},
{"defaultdac", &InferAction::defaultdac},
{"defaultpattern", &InferAction::defaultpattern},
{"define_bit", &InferAction::define_bit},
{"define_reg", &InferAction::define_reg},
{"definelist_bit", &InferAction::definelist_bit},
{"definelist_reg", &InferAction::definelist_reg},
{"delay", &InferAction::delay},
{"delayl", &InferAction::delayl},
{"detectorserverversion", &InferAction::detectorserverversion},

View File

@@ -8,7 +8,6 @@ target_sources(tests PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}/Caller/test-Caller.cpp
${CMAKE_CURRENT_SOURCE_DIR}/Caller/test-Caller-rx.cpp
${CMAKE_CURRENT_SOURCE_DIR}/Caller/test-Caller-rx-running.cpp
${CMAKE_CURRENT_SOURCE_DIR}/Caller/test-Caller-pattern.cpp
${CMAKE_CURRENT_SOURCE_DIR}/Caller/test-Caller-eiger.cpp
${CMAKE_CURRENT_SOURCE_DIR}/Caller/test-Caller-jungfrau.cpp

View File

@@ -1025,43 +1025,91 @@ TEST_CASE("dbitclk", "[.cmdcall]") {
}
}
TEST_CASE("v_abcd", "[.cmdcall]") {
TEST_CASE("v_a", "[.cmdcall]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
std::vector<std::string> cmds{"v_a", "v_b", "v_c", "v_d"};
std::vector<defs::dacIndex> indices{defs::V_POWER_A, defs::V_POWER_B,
defs::V_POWER_C, defs::V_POWER_D};
if (det.isVirtualDetectorServer().tsquash("Inconsistent virtual servers")) {
cmds.push_back("v_io");
indices.push_back(defs::V_POWER_IO);
}
for (size_t i = 0; i < cmds.size(); ++i) {
if (det_type == defs::CHIPTESTBOARD ||
det_type == defs::XILINX_CHIPTESTBOARD) {
auto prev_val = det.getPower(indices[i]);
{
std::ostringstream oss;
caller.call(cmds[i], {"0"}, -1, PUT, oss);
REQUIRE(oss.str() == cmds[i] + " 0\n");
}
{
std::ostringstream oss1, oss2;
caller.call(cmds[i], {"1200"}, -1, PUT, oss1);
REQUIRE(oss1.str() == cmds[i] + " 1200\n");
caller.call(cmds[i], {}, -1, GET, oss2);
REQUIRE(oss2.str() == cmds[i] + " 1200\n");
}
for (int i = 0; i != det.size(); ++i) {
det.setPower(indices[i], prev_val[i], {i});
}
} else {
REQUIRE_THROWS(caller.call(cmds[i], {}, -1, GET));
if (det_type == defs::CHIPTESTBOARD ||
det_type == defs::XILINX_CHIPTESTBOARD) {
auto prev_val = det.getPower(defs::V_POWER_A);
{
std::ostringstream oss1, oss2;
caller.call("v_a", {"1200"}, -1, PUT, oss1);
REQUIRE(oss1.str() == "v_a 1200\n");
caller.call("v_a", {}, -1, GET, oss2);
REQUIRE(oss2.str() == "v_a 1200\n");
}
for (int i = 0; i != det.size(); ++i) {
det.setPower(defs::V_POWER_A, prev_val[i], {i});
}
} else {
REQUIRE_THROWS(caller.call("v_a", {}, -1, GET));
}
}
TEST_CASE("v_b", "[.cmdcall]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::CHIPTESTBOARD ||
det_type == defs::XILINX_CHIPTESTBOARD) {
auto prev_val = det.getPower(defs::V_POWER_B);
{
std::ostringstream oss1, oss2;
caller.call("v_b", {"1200"}, -1, PUT, oss1);
REQUIRE(oss1.str() == "v_b 1200\n");
caller.call("v_b", {}, -1, GET, oss2);
REQUIRE(oss2.str() == "v_b 1200\n");
}
for (int i = 0; i != det.size(); ++i) {
det.setPower(defs::V_POWER_B, prev_val[i], {i});
}
} else {
REQUIRE_THROWS(caller.call("v_b", {}, -1, GET));
}
}
TEST_CASE("v_c", "[.cmdcall]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::CHIPTESTBOARD ||
det_type == defs::XILINX_CHIPTESTBOARD) {
auto prev_val = det.getPower(defs::V_POWER_C);
{
std::ostringstream oss1, oss2;
caller.call("v_c", {"1200"}, -1, PUT, oss1);
REQUIRE(oss1.str() == "v_c 1200\n");
caller.call("v_c", {}, -1, GET, oss2);
REQUIRE(oss2.str() == "v_c 1200\n");
}
for (int i = 0; i != det.size(); ++i) {
det.setPower(defs::V_POWER_C, prev_val[i], {i});
}
} else {
REQUIRE_THROWS(caller.call("v_c", {}, -1, GET));
}
}
TEST_CASE("v_d", "[.cmdcall]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::CHIPTESTBOARD ||
det_type == defs::XILINX_CHIPTESTBOARD) {
auto prev_val = det.getPower(defs::V_POWER_D);
{
std::ostringstream oss1, oss2;
caller.call("v_d", {"1200"}, -1, PUT, oss1);
REQUIRE(oss1.str() == "v_d 1200\n");
caller.call("v_d", {}, -1, GET, oss2);
REQUIRE(oss2.str() == "v_d 1200\n");
}
for (int i = 0; i != det.size(); ++i) {
det.setPower(defs::V_POWER_D, prev_val[i], {i});
}
} else {
REQUIRE_THROWS(caller.call("v_d", {}, -1, GET));
}
}
@@ -1330,366 +1378,4 @@ TEST_CASE("led", "[.cmdcall]") {
}
}
TEST_CASE("define_reg", "[.cmdcall]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::CHIPTESTBOARD ||
det_type == defs::XILINX_CHIPTESTBOARD) {
auto prev_reg_defines = det.getRegisterDefinitions();
auto prev_bit_defines = det.getBitDefinitions();
det.clearRegisterDefinitions();
det.clearBitDefinitions();
{
// invalid puts
// missing arg
REQUIRE_THROWS(caller.call("define_reg", {}, -1, GET));
// missing arg
REQUIRE_THROWS(caller.call("define_reg", {"TEST_REG"}, -1, PUT));
// invalid module id
REQUIRE_THROWS(
caller.call("define_reg", {"TEST_REG", "0x201"}, 0, PUT));
// valid put
REQUIRE_NOTHROW(
caller.call("define_reg", {"TEST_REG", "0x200"}, -1, PUT));
// modify reg
REQUIRE_NOTHROW(
caller.call("define_reg", {"TEST_REG", "0x201"}, -1, PUT));
REQUIRE_NOTHROW(
caller.call("define_reg", {"TEST_REG2", "0x202"}, -1, PUT));
// invalid puts
// existing reg addr
REQUIRE_THROWS(
caller.call("define_reg", {"TEST_REG3", "0x201"}, -1, PUT));
// valid gets
{
// get by name
std::ostringstream oss;
REQUIRE_NOTHROW(
caller.call("define_reg", {"TEST_REG"}, -1, GET, oss));
REQUIRE(oss.str() == "define_reg 0x201\n");
}
{
// get by addr
std::ostringstream oss;
REQUIRE_NOTHROW(
caller.call("define_reg", {"0x201"}, -1, GET, oss));
REQUIRE(oss.str() == "define_reg TEST_REG\n");
}
// invalid gets
// doesnt exist
REQUIRE_THROWS(caller.call("define_reg", {"TEST_REG3"}, -1, GET));
REQUIRE_THROWS(caller.call("define_reg", {"0x203"}, -1, GET));
// ensure correct exception message
try {
caller.call("define_reg", {"0x203"}, -1, GET);
} catch (const std::exception &e) {
REQUIRE(std::string(e.what()) ==
"No register definition found for address: 0x203");
}
}
det.clearRegisterDefinitions();
det.clearBitDefinitions();
det.setRegisterDefinitions(prev_reg_defines);
det.setBitDefinitions(prev_bit_defines);
} else {
REQUIRE_THROWS(
caller.call("define_reg", {"TEST_REG", "0x200"}, -1, PUT));
REQUIRE_THROWS(caller.call("define_reg", {"TEST_REG"}, -1, GET));
}
}
TEST_CASE("define_bit", "[.cmdcall]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::CHIPTESTBOARD ||
det_type == defs::XILINX_CHIPTESTBOARD) {
auto prev_reg_defines = det.getRegisterDefinitions();
auto prev_bit_defines = det.getBitDefinitions();
det.clearRegisterDefinitions();
det.clearBitDefinitions();
det.setRegisterDefinition("TEST_REG", RegisterAddress(0x201));
det.setRegisterDefinition("TEST_REG2", RegisterAddress(0x202));
{
// invalid puts
// skipped register
REQUIRE_THROWS(
caller.call("define_bit", {"TEST_BIT", "1"}, -1, PUT));
// named register doesnt exist
REQUIRE_THROWS(caller.call(
"define_bit", {"TEST_BIT", "RANDOM_REG", "1"}, -1, PUT));
// invalid bit position
REQUIRE_THROWS(
caller.call("define", {"TEST_BIT", "TEST_REG", "32"}, -1, PUT));
// valid puts
REQUIRE_NOTHROW(caller.call(
"define_bit", {"TEST_BIT", "TEST_REG2", "1"}, -1, PUT));
// modify reg
REQUIRE_NOTHROW(caller.call(
"define_bit", {"TEST_BIT", "TEST_REG", "1"}, -1, PUT));
// modify position
REQUIRE_NOTHROW(caller.call(
"define_bit", {"TEST_BIT", "TEST_REG", "2"}, -1, PUT));
// another bit to same reg
REQUIRE_NOTHROW(caller.call(
"define_bit", {"TEST_BIT2", "TEST_REG", "4"}, -1, PUT));
// bit to a different reg
REQUIRE_NOTHROW(caller.call(
"define_bit", {"TEST_BIT3", "TEST_REG2", "3"}, -1, PUT));
// valid gets
{
// get by name
std::ostringstream oss;
REQUIRE_NOTHROW(
caller.call("define_bit", {"TEST_BIT"}, -1, GET, oss));
REQUIRE(oss.str() == "define_bit [TEST_REG, 2]\n");
}
{
// get by addr+pos name
std::ostringstream oss;
REQUIRE_NOTHROW(
caller.call("define_bit", {"TEST_REG", "2"}, -1, GET, oss));
REQUIRE(oss.str() == "define_bit TEST_BIT\n");
}
{
// get by addr val + pos
std::ostringstream oss;
REQUIRE_NOTHROW(
caller.call("define_bit", {"0x201", "2"}, -1, GET, oss));
REQUIRE(oss.str() == "define_bit TEST_BIT\n");
}
// invalid gets
// bit doesnt exist
REQUIRE_THROWS(
caller.call("define_bit", {"TEST_REG", "3"}, -1, GET));
// addr doesnt exist
REQUIRE_THROWS(
caller.call("define_bit", {"TEST_REG3", "2"}, -1, GET));
// ensure correct exception message
try {
caller.call("define_bit", {"TEST_REG", "3"}, -1, GET);
} catch (const std::exception &e) {
REQUIRE(std::string(e.what()) ==
"No bit definition found for bit position: [0x201, 3] "
"and addr = TEST_REG");
}
}
det.clearRegisterDefinitions();
det.clearBitDefinitions();
det.setRegisterDefinitions(prev_reg_defines);
det.setBitDefinitions(prev_bit_defines);
} else {
REQUIRE_THROWS(
caller.call("define_bit", {"TEST_BIT", "0x200", "2"}, -1, PUT));
REQUIRE_THROWS(caller.call("define_bit", {"0x200", "2"}, -1, GET));
}
}
TEST_CASE("using define for reg, setbit, getbit and clearbit", "[.cmdcall]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::CHIPTESTBOARD ||
det_type == defs::XILINX_CHIPTESTBOARD) {
if (det.isVirtualDetectorServer().tsquash(
"inconsistent virtual values")) {
auto prev_reg_defines = det.getRegisterDefinitions();
auto prev_bit_defines = det.getBitDefinitions();
det.clearRegisterDefinitions();
det.clearBitDefinitions();
det.setRegisterDefinition("TEST_REG", RegisterAddress(0x201));
det.setRegisterDefinition("TEST_REG2", RegisterAddress(0x202));
det.setBitDefinition("TEST_BIT",
BitAddress(RegisterAddress(0x201), 2));
det.setBitDefinition("TEST_BIT2",
BitAddress(RegisterAddress(0x201), 4));
det.setBitDefinition("TEST_BIT3",
BitAddress(RegisterAddress(0x202), 3));
auto prev_val_addr = det.readRegister(RegisterAddress(0x201));
auto prev_val_addr2 = det.readRegister(RegisterAddress(0x202));
// invalid puts
// doesnt exist addr
REQUIRE_THROWS(
caller.call("reg", {"RANDOM_REG", "0xf00"}, -1, PUT));
REQUIRE_THROWS(
caller.call("clearbit", {"RANDOM_REG", "TEST_BIT"}, -1, PUT));
REQUIRE_THROWS(
caller.call("setbit", {"RANDOM_REG", "TEST_BIT"}, -1, PUT));
REQUIRE_THROWS(
caller.call("getbit", {"RANDOM_REG", "TEST_BIT"}, -1, GET));
// using bit name for reg (only hardcoded values allowed)
REQUIRE_THROWS(
caller.call("reg", {"TEST_REG", "TEST_BIT"}, -1, PUT));
// using bit name and reg (only bit names or both reg and bit
// hardcoded allowed)
REQUIRE_THROWS(
caller.call("clearbit", {"TEST_REG", "TEST_BIT"}, -1, PUT));
REQUIRE_THROWS(
caller.call("setbit", {"TEST_REG", "TEST_BIT"}, -1, PUT));
REQUIRE_THROWS(
caller.call("getbit", {"TEST_REG", "TEST_BIT"}, -1, GET));
// valid puts and gets
{
// reg hard coded value of 0
std::ostringstream oss;
REQUIRE_NOTHROW(
caller.call("reg", {"TEST_REG", "0x0"}, -1, PUT));
REQUIRE_NOTHROW(caller.call("reg", {"TEST_REG"}, -1, GET, oss));
REQUIRE(oss.str() == "reg 0x0\n");
}
{
// reg hard coded value
std::ostringstream oss;
REQUIRE_NOTHROW(
caller.call("reg", {"TEST_REG", "0x10"}, -1, PUT));
REQUIRE_NOTHROW(caller.call("reg", {"TEST_REG"}, -1, GET, oss));
REQUIRE(oss.str() == "reg 0x10\n");
}
{
// set bit
std::ostringstream oss;
REQUIRE_NOTHROW(caller.call("setbit", {"TEST_BIT"}, -1, PUT));
REQUIRE_NOTHROW(
caller.call("setbit", {"TEST_REG", "2"}, -1, PUT));
REQUIRE_NOTHROW(caller.call("reg", {"TEST_REG"}, -1, GET, oss));
REQUIRE(oss.str() == "reg 0x14\n");
}
{
// get bit
std::ostringstream oss, oss2;
REQUIRE_NOTHROW(
caller.call("getbit", {"TEST_REG", "2"}, -1, GET, oss));
REQUIRE(oss.str() == "getbit 1\n");
REQUIRE_NOTHROW(
caller.call("getbit", {"TEST_BIT"}, -1, GET, oss2));
REQUIRE(oss2.str() == "getbit 1\n");
}
{
// clear bit
std::ostringstream oss;
REQUIRE_NOTHROW(caller.call("clearbit", {"TEST_BIT"}, -1, PUT));
REQUIRE_NOTHROW(
caller.call("clearbit", {"TEST_REG", "2"}, -1, PUT));
REQUIRE_NOTHROW(caller.call("reg", {"TEST_REG"}, -1, GET, oss));
REQUIRE(oss.str() == "reg 0x10\n");
}
for (int i = 0; i != det.size(); ++i) {
det.writeRegister(RegisterAddress(0x201),
RegisterValue(prev_val_addr[i]), false, {i});
det.writeRegister(RegisterAddress(0x202),
RegisterValue(prev_val_addr2[i]), false, {i});
}
det.clearRegisterDefinitions();
det.clearBitDefinitions();
det.setRegisterDefinitions(prev_reg_defines);
det.setBitDefinitions(prev_bit_defines);
}
} else {
REQUIRE_THROWS(caller.call("reg", {"TEST_REG", "0x200"}, -1, PUT));
REQUIRE_THROWS(caller.call("reg", {"TEST_REG"}, -1, GET));
}
}
TEST_CASE("definelist_reg", "[.cmdcall]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::CHIPTESTBOARD ||
det_type == defs::XILINX_CHIPTESTBOARD) {
auto prev_reg_defines = det.getRegisterDefinitions();
det.clearRegisterDefinitions();
det.clearBitDefinitions();
det.setRegisterDefinition("TEST_REG", RegisterAddress(0x201));
det.setRegisterDefinition("TEST_REG2", RegisterAddress(0x202));
// invalid
// cannot put
REQUIRE_THROWS(
caller.call("definelist_reg", {"TEST_REG", "0x201"}, -1, PUT));
// too many args
REQUIRE_THROWS(caller.call("definelist_reg", {"TEST_MACRO"}, -1, GET));
// valid
REQUIRE_NOTHROW(caller.call("definelist_reg", {}, -1, GET));
det.clearRegisterDefinitions();
det.clearBitDefinitions();
det.setRegisterDefinitions(prev_reg_defines);
} else {
REQUIRE_THROWS(caller.call("definelist_reg", {}, -1, GET));
}
}
TEST_CASE("definelist_bit", "[.cmdcall]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::CHIPTESTBOARD ||
det_type == defs::XILINX_CHIPTESTBOARD) {
auto prev_reg_defines = det.getRegisterDefinitions();
auto prev_bit_defines = det.getBitDefinitions();
det.clearRegisterDefinitions();
det.clearBitDefinitions();
det.setRegisterDefinition("TEST_REG", RegisterAddress(0x201));
det.setRegisterDefinition("TEST_REG2", RegisterAddress(0x202));
det.setBitDefinition("TEST_BIT", BitAddress(RegisterAddress(0x201), 2));
det.setBitDefinition("TEST_BIT2",
BitAddress(RegisterAddress(0x201), 4));
det.setBitDefinition("TEST_BIT3",
BitAddress(RegisterAddress(0x202), 3));
// invalid
// cannot put
REQUIRE_THROWS(
caller.call("definelist_bit", {"TEST_BIT", "0x201", "2"}, -1, PUT));
// too many args
REQUIRE_THROWS(caller.call("definelist_bit", {"TEST_BIT"}, -1, GET));
// valid
REQUIRE_NOTHROW(caller.call("definelist_bit", {}, -1, GET));
det.clearRegisterDefinitions();
det.clearBitDefinitions();
det.setRegisterDefinitions(prev_reg_defines);
det.setBitDefinitions(prev_bit_defines);
} else {
REQUIRE_THROWS(caller.call("definelist_bit", {}, -1, GET));
}
}
} // namespace sls

View File

@@ -436,8 +436,7 @@ TEST_CASE("patternstart", "[.cmdcall]") {
Caller caller(&det);
REQUIRE_THROWS(caller.call("patternstart", {}, -1, GET));
auto det_type = det.getDetectorType().squash();
if (det_type == defs::MYTHEN3 || det_type == defs::CHIPTESTBOARD ||
det_type == defs::XILINX_CHIPTESTBOARD) {
if (det_type == defs::MYTHEN3) {
REQUIRE_NOTHROW(caller.call("patternstart", {}, -1, PUT));
} else {
REQUIRE_THROWS(caller.call("patternstart", {}, -1, PUT));

View File

@@ -1,239 +0,0 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2025 Contributors to the SLS Detector Package
#include "Caller.h"
#include "catch.hpp"
#include "sls/Detector.h"
#include "tests/globals.h"
#include <sstream>
namespace sls {
using test::PUT;
TEST_CASE("Ctb and xilinx - cant put if receiver is not idle",
"[.cmdcall][.rx]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::CHIPTESTBOARD ||
det_type == defs::XILINX_CHIPTESTBOARD) {
auto prev_romode = det.getReadoutMode();
auto prev_asamples = det.getNumberOfAnalogSamples();
auto prev_dsamples = det.getNumberOfDigitalSamples();
auto prev_tsamples = det.getNumberOfTransceiverSamples();
auto prev_adcenable10g = det.getTenGigaADCEnableMask();
auto prev_trasnsceiverenable = det.getTransceiverEnableMask();
auto prev_rxdbitlist = det.getRxDbitList();
auto prev_rxdbitoffset = det.getRxDbitOffset();
auto prev_rxdbitreorder = det.getRxDbitReorder();
// start receiver
REQUIRE_NOTHROW(caller.call("rx_start", {}, -1, PUT));
REQUIRE_THROWS(caller.call("romode", {"digital"}, -1, PUT));
REQUIRE_THROWS(caller.call("asamples", {"5"}, -1, PUT));
REQUIRE_THROWS(caller.call("dsamples", {"100"}, -1, PUT));
REQUIRE_THROWS(caller.call("tsamples", {"2"}, -1, PUT));
REQUIRE_THROWS(caller.call("adcenable10g", {"0xFF00FFFF"}, -1, PUT));
REQUIRE_THROWS(caller.call("transceiverenable", {"0x3"}, -1, PUT));
REQUIRE_THROWS(caller.call("rx_dbitlist", {"{1,2,10}"}, -1, PUT));
REQUIRE_THROWS(caller.call("rx_dbitoffset", {"5"}, -1, PUT));
REQUIRE_THROWS(caller.call("rx_dbitreorder", {"0"}, -1, PUT));
// stop receiver
REQUIRE_NOTHROW(caller.call("rx_stop", {}, -1, PUT));
for (int i = 0; i != det.size(); ++i) {
det.setReadoutMode(prev_romode[i], {i});
det.setNumberOfAnalogSamples(prev_asamples[i], {i});
det.setNumberOfDigitalSamples(prev_dsamples[i], {i});
det.setNumberOfTransceiverSamples(prev_tsamples[i], {i});
det.setTenGigaADCEnableMask(prev_adcenable10g[i], {i});
det.setTransceiverEnableMask(prev_trasnsceiverenable[i], {i});
det.setRxDbitList(prev_rxdbitlist[i], {i});
det.setRxDbitOffset(prev_rxdbitoffset[i], {i});
det.setRxDbitReorder(prev_rxdbitreorder[i], {i});
}
}
}
TEST_CASE("adcenable - cant put if receiver is not idle", "[.cmdcall][.rx]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::CHIPTESTBOARD) {
auto prev_adcenable = det.getADCEnableMask();
// start receiver
REQUIRE_NOTHROW(caller.call("rx_start", {}, -1, PUT));
REQUIRE_THROWS(caller.call("adcenable", {"0xFFFFFF00"}, -1, PUT));
// stop receiver
REQUIRE_NOTHROW(caller.call("rx_stop", {}, -1, PUT));
for (int i = 0; i != det.size(); ++i) {
det.setADCEnableMask(prev_adcenable[i], {i});
}
}
}
TEST_CASE("bursts - cant put if receiver is not idle", "[.cmdcall][.rx]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::GOTTHARD2) {
auto prev_burst =
det.getNumberOfBursts().tsquash("#bursts should be same to test");
// start receiver
REQUIRE_NOTHROW(caller.call("rx_start", {}, -1, PUT));
REQUIRE_THROWS(caller.call("bursts", {"20"}, -1, PUT));
// stop receiver
REQUIRE_NOTHROW(caller.call("rx_stop", {}, -1, PUT));
det.setNumberOfBursts(prev_burst);
}
}
TEST_CASE("counters - cant put if receiver is not idle", "[.cmdcall][.rx]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::MYTHEN3) {
auto prev_counters = det.getCounterMask();
// start receiver
REQUIRE_NOTHROW(caller.call("rx_start", {}, -1, PUT));
REQUIRE_THROWS(caller.call("counters", {"0 1 2"}, -1, PUT));
// stop receiver
REQUIRE_NOTHROW(caller.call("rx_stop", {}, -1, PUT));
for (int i = 0; i != det.size(); ++i) {
det.setCounterMask(prev_counters[i], {i});
}
}
}
TEST_CASE("numinterfaces - cant put if receiver is not idle",
"[.cmdcall][.rx]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::JUNGFRAU || det_type == defs::MOENCH) {
auto prev_numinterfaces = det.getNumberofUDPInterfaces();
// start receiver
REQUIRE_NOTHROW(caller.call("rx_start", {}, -1, PUT));
REQUIRE_THROWS(caller.call("numinterafaces", {"2"}, -1, PUT));
// stop receiver
REQUIRE_NOTHROW(caller.call("rx_stop", {}, -1, PUT));
for (int i = 0; i != det.size(); ++i) {
det.setNumberofUDPInterfaces(prev_numinterfaces[i], {i});
}
}
}
TEST_CASE("dr - cant put if receiver is not idle", "[.cmdcall][.rx]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::EIGER || det_type == defs::MYTHEN3) {
auto prev_dr =
det.getDynamicRange().tsquash("dr should be same to test");
// start receiver
REQUIRE_NOTHROW(caller.call("rx_start", {}, -1, PUT));
REQUIRE_THROWS(caller.call("dr", {"16"}, -1, PUT));
// stop receiver
REQUIRE_NOTHROW(caller.call("rx_stop", {}, -1, PUT));
det.setDynamicRange(prev_dr);
}
}
TEST_CASE("tengiga - cant put if receiver is not idle", "[.cmdcall][.rx]") {
Detector det;
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::EIGER || det_type == defs::MYTHEN3 ||
det_type == defs::CHIPTESTBOARD) {
auto prev_tengiga = det.getTenGiga();
// start receiver
REQUIRE_NOTHROW(caller.call("rx_start", {}, -1, PUT));
REQUIRE_THROWS(caller.call("tengiga", {"1"}, -1, PUT));
// stop receiver
REQUIRE_NOTHROW(caller.call("rx_stop", {}, -1, PUT));
for (int i = 0; i != det.size(); ++i) {
det.setTenGiga(prev_tengiga[i], {i});
}
}
}
TEST_CASE("general - cant put if receiver is not idle", "[.cmdcall][.rx]") {
Detector det;
Caller caller(&det);
{
auto prev_frames =
det.getNumberOfFrames().tsquash("#frames should be same to test");
auto prev_triggers =
det.getNumberOfTriggers().tsquash("#triggers must be same to test");
auto prev_findex = det.getAcquisitionIndex();
auto prev_fwrite = det.getFileWrite();
auto prev_fifodepth = det.getRxFifoDepth();
auto rx_hostname = det.getRxHostname();
// start receiver
REQUIRE_NOTHROW(caller.call("rx_start", {}, -1, PUT));
REQUIRE_THROWS(caller.call("frames", {"10"}, -1, PUT));
REQUIRE_THROWS(caller.call("triggers", {"5"}, -1, PUT));
REQUIRE_THROWS(caller.call("findex", {"2"}, -1, PUT));
REQUIRE_THROWS(caller.call("fwrite", {"0"}, -1, PUT));
REQUIRE_THROWS(caller.call("rx_fifodepth", {"1000"}, -1, PUT));
REQUIRE_THROWS(caller.call("rx_hostname", {rx_hostname[0]}, 0, PUT));
// stop receiver
REQUIRE_NOTHROW(caller.call("rx_stop", {}, -1, PUT));
det.setNumberOfFrames(prev_frames);
det.setNumberOfTriggers(prev_triggers);
for (int i = 0; i != det.size(); ++i) {
det.setAcquisitionIndex(prev_findex[i], {i});
det.setFileWrite(prev_fwrite[i], {i});
det.setRxFifoDepth(prev_fifodepth[i], {i});
det.setRxHostname(rx_hostname[i], {i});
}
}
}
} // namespace sls

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