* if blocking and handling sync, only master gets blocking acq, slaves get non blocking as they are first and so dont get status or error caught when slaves dont get trigger (due to not connected etc) and acq returns with slaves still in waiting status. so check status of all in blocking acq
* for all dets with sync, ensure atleast one master when starting acq
* docs updated about sync
* fix virtual test when it fails
* catching errors in tests and removing sigchild ignore so servers (process in background) executing commands will not fail (pclose no child processes, if sigchld is ignored) fixed
* uncommented python loading config
* somehow killal slsReciever in second detector test fails even though no receiver running
* fixing script for virtual simlator test:fixed issue with check if process running, fixed moench tests
* fix acquisition finished status to have different status for different modules, but does not have to be error. for eg. jf sync fw (2.4.1 gives idle for master and stopped for slaves when stopping acquiistion)
* jf: if bit 14 in reg 0x5d (electron mode collection bit) is changed, configure chip if v1.1 and powered on. so touch writeregister (setbit/clearbit also calls write register in the end). replace when electroncollectionmode command introduced
* rewrite of status reg bits, waiting state includes both wati for trigger and start frame, blocking trigger only waits if its not in waiting for trigger and run busy enabled, error state connected in firmware
* jf sync mode master could return idle when stopped and so not all modules return the same value and must check for 'stopped or idle', Also must throw if any of the module gives an error
* added contains_only to sls::Result (#827)
* added variadic template for checking if a result contains only specified values
* fix for gcc4.8
* renamed to Result::contains_only
* stop on only the positions
---------
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
* getVoltageList, getVoltage /set, getMeasuredVoltage, getVoltageNames /set, getVoltageIndex moved to 'Power' as its misleading
* added cstdint and names slowadc, added division to mV
* changed uV to mV in command line slow adc help. removed all python slowadcs (as it was already implemented as slowadc
---------
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
* updated python bindings for port update from int to uint16_t
* user friendly error message for exception when python arg does not match uint16_t for ports
* merge fix from 7.0.2: new jungfrau fw versions, incremented binary, hdf5 and json versions
* moench: changed dac names and default values to old moench values
* moench: remove interface clk polarity at start up
* moench: default speed is half speed, default values for adc offset and adc phase for different speeds (only half speed confirmed), adc vref voltage to 2.0 like G1
* moench: connected adc pipeline to client
* moench: receiver- default frames per file is 100k and discard partial frames as default
* moench binary in
* using tostring in gui for dacs
* moved frame discard policy as a parameter to be configured with a default depending on detector
* moench: 300 degrees for adc phase in full speed
* silence warnings
* making constructors explicit to avoid unintended conversions
* changed struct to class since we already have public:
---------
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* using fetchcontent to get zmq
* local copy of libzmq
* added guard for policy setting
* removed the need to export by using build interface
* moved pybind11 to FetchContent
* removed zmq hint from cmk script
* Fixed comments
---------
authored-by: froejdh_e <erik.frojdh@psi.ch>
* using fetchcontent to get zmq
* local copy of libzmq
* added guard for policy setting
* removed the need to export by using build interface
* removed zmq hint from cmk script
---------
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
Co-authored-by: froejdh_e <erik.frojdh@psi.ch>
* transceiverenable, tsamples, romode for tranceiver and digital_transceiver
* 202 spec instr only for transceiver mode
* removed check for empty in trans readout and clean memory before reading from fifo
* ctb read fifo strobe for all after reading all channels, adding 1us after selecting channel, changing fw date
* updated 10gb transceiver enable
----
* added transceiver (tsamples, romode(transceiver, digital_transceiver), transceiverenable (mask)
* clean memory before reading from fifo (for analog and digital as well)
* read fifo then read strobe (also corresp fw) fixes number of reads (also for analg and digital)-> increases all pipelines by 1
* fixed bug in rearranging digital data in receiver
* fixed bug in streaming size of data after rearranging
* fixed bug in setbit, clearbit,and getbit
* status checks fifo before returning idle (transmitting if data in fifo if transceiver more enabled)
* soem matterhorn specifics that will need to be put into pattern in a month or two. this is temporary.
* NOTE: breaking api. rxParameters struct has transceiverenabel and tsamples given from det to receiver
