ecc692ad9a
start pattern without binaries
2020-05-15 17:06:08 +02:00
00c1211c56
unformatting regdefs
2020-05-15 16:14:57 +02:00
671cf45fd7
format slsdetectorservers
2020-05-05 15:23:11 +02:00
8cbf3c62a9
merge from developer
2020-01-22 17:30:13 +01:00
981b13494c
mythen3: virtual server, connected timing mode, row and col in header, included pattern bit and mask
2020-01-21 18:16:27 +01:00
e8bdf5a505
gotthard2: updated register map; powerchip checking detector type; internal and external period, frames, exptime; set/get delay, get actualtime, measurement, framesfromstart enabled; which detector comment updated in cmdproxy, detector and slsdetector
2020-01-16 15:33:35 +01:00
Dhanya Thattil
de53747ddd
Counters ( #71 )
...
* mythen3: adding counters mask, firmware still takes only number of counters for now
* mythen3: checking if module attached before powering on chip
* bug fix: loop inital declaration not allowed in c
* fix scope eiger test
* mythen3: renamed setCounters to setCounterMask and getCounterMask in API
* mythen3 replacing counting bits with popcount
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2020-01-14 17:40:46 +01:00
086cbacd84
mythen3: connected busy signal insttead of timer
2019-12-10 11:03:27 +01:00
c4675da0c3
m3: reset fixed
2019-11-22 16:40:43 +01:00
d07873ee39
mythen3 and gotthard2: wait request not needed, reset to be implemented
2019-11-22 11:29:24 +01:00
781e8fc67f
mythen3: workaround for busy signal
2019-11-20 11:57:14 +01:00
2123fb47a5
mythen3: config reg enable all counters, dr
2019-11-11 10:41:42 +01:00
1797d39216
updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings
2019-11-06 18:58:22 +01:00
Marie Andrae
7de9401bc7
powerchip for mythen3
2019-11-06 11:50:09 +01:00
f9fff97f8a
mythen3 register mix up
2019-10-31 14:48:53 +01:00
Dhanya Thattil
995f0924e5
Commandline ( #66 )
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* WIP
* WIP
* removed status to string from defs
* WIP
* WIP
* WIP removed unused functions in multi
* WIP
* print hex in a terrible way
* WIP, loadconfig error
* WIP, type to string
* WIP
* fix to conversion
* WIP, hostname doesnt work
* WIP
* WIP
* WIP
* WIP, threshold
* WIP, threshold
* WIP
* WIP, triggers
* WIP, cycles to triggers
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* rx_udsocksize fx, WIP
* WIP
* WIP
* WIP
* file index (64 bit), WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* merge
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* New python mod
2019-10-21 10:29:06 +02:00
Marie Andrä
9b4fc02b0e
start/stop statemachine for my3 ( #68 )
...
* start/stop statemachine for my3
* runStatus, readFrame, runBusy (use CONTROL_REG) for mythen3
* registers for Pavel
* change dac names Mythen3
2019-10-09 13:52:07 +02:00
Marie Andrä
5f94b5c246
Dac ( #67 )
...
* dac WIP
* dacs WIP
* DACs are working with names
* namechanges of vrfsh->vshaper, vrfshnpol->vshaperneg
* pattern for MY3, configure MAC for MY3
2019-10-07 12:13:25 +02:00
Marie Andrä
6e6fcec698
MY3.0:read and write Registers, frames, cycles, delay ( #64 )
...
* MY3.0:read and write Registers, frames, cycles, delay
* write pattern seems to work
* done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos)
* clk check for aquistition time
* clk check for aquistition time
* Update slsDetectorServer_defs.h
* Update slsDetectorFunctionList.c
2019-09-30 14:36:33 +02:00
Marie Andrä
4b987abf41
Niosmarie ( #63 )
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* HV for Mythen3 server
* HV for mythen3 server
* corrected upstreams
* missing endif
2019-09-03 09:36:02 +02:00
Marie Andrä
f981825172
virtual UDP for mythen3 ( #55 )
2019-08-26 10:53:17 +02:00
4b7ab98135
initial functions for mythen3
2019-08-22 15:55:27 +02:00
72362b0334
first version of mythen3
2019-08-22 12:34:06 +02:00
