mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-26 08:10:02 +02:00
995f0924e5
* WIP * WIP * removed status to string from defs * WIP * WIP * WIP removed unused functions in multi * WIP * print hex in a terrible way * WIP, loadconfig error * WIP, type to string * WIP * fix to conversion * WIP, hostname doesnt work * WIP * WIP * WIP * WIP, threshold * WIP, threshold * WIP * WIP, triggers * WIP, cycles to triggers * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * rx_udsocksize fx, WIP * WIP * WIP * WIP * file index (64 bit), WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * merge * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * New python mod
192 lines
8.5 KiB
C
192 lines
8.5 KiB
C
// stuff from Carlos
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#pragma once
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/* Definitions for FPGA*/
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#define REG_OFFSET (4)
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#define BASE_CONTROL (0x0)
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#define BASE_PATTERN_CONTROL (0x200)
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#define BASE_PATTERN_RAM (0x10000)
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#define BASE_UDP_RAM (0x1000) // fix it
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/* Basic detector FPGA registers --------------------------------------------------*/
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/* Module Control Board Serial Number Register */
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#define MCB_SERIAL_NO_REG (0x000 * REG_OFFSET + BASE_CONTROL)
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/* FPGA Version register */
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#define FPGA_VERSION_REG (0x001 * REG_OFFSET + BASE_CONTROL)
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#define FPGA_COMPILATION_DATE_OFST (0)
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#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
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#define DETECTOR_TYPE_OFST (24)
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#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
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/* API Version Register */
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#define API_VERSION_REG (0x002 * REG_OFFSET + BASE_CONTROL)
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#define API_VERSION_OFST (0)
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#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
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#define API_VERSION_DETECTOR_TYPE_OFST (24) //Not used in software
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#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
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/* Fix pattern register */
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#define FIX_PATT_REG (0x003 * REG_OFFSET + BASE_CONTROL)
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#define FIX_PATT_VAL (0xACDC2019)
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/* Status register */
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#define STATUS_REG (0x004 * REG_OFFSET + BASE_CONTROL)
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#ifdef VIRTUAL // until firmware is ready ----------------------------------
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#define RUN_BUSY_OFST (0)
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#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
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#endif
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/* Look at me register, read only */
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#define LOOK_AT_ME_REG (0x005 * REG_OFFSET + BASE_CONTROL) //Not used in firmware or software, good to play with
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/* Control RW register */ // assumed for MY3
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#define CONTROL_REG (0x021 * REG_OFFSET + BASE_CONTROL)
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#define CONTROL_STRT_ACQSTN_OFST (0)
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#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
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#define CONTROL_STP_ACQSTN_OFST (1)
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#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
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#define CONTROL_RN_BSY_OFST (2) // assumed for MY3
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#define CONTROL_RN_BSY_MSK (0x00000001 << CONTROL_RN_BSY_OFST)
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#define CONTROL_STRT_EXPSR_OFST (6)
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#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
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#define CONTROL_CRE_RST_OFST (10)
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#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
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#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
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#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
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// #define CONTROL_MMRY_RST_OFST (12)
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// #define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
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#define CONTROL_CLR_ACQSTN_FIFO_OFST (14)
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#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
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#define DTA_OFFSET_REG (0x104 * REG_OFFSET + BASE_CONTROL)
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/* Pattern Control FPGA registers --------------------------------------------------*/
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/* Pattern status Register*/
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#define PAT_STATUS_REG (0x000 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Delay left 64bit Register */
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#define GET_DELAY_LSB_REG (0x0002 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define GET_DELAY_MSB_REG (0x0003 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Triggers left 64bit Register */
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#define GET_CYCLES_LSB_REG (0x0004 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define GET_CYCLES_MSB_REG (0x0005 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Frames left 64bit Register */
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#define GET_FRAMES_LSB_REG (0x0006 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define GET_FRAMES_MSB_REG (0x0007 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Period left 64bit Register */
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#define GET_PERIOD_LSB_REG (0x0008 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define GET_PERIOD_MSB_REG (0x0009 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Delay 64bit Write-register */
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#define SET_DELAY_LSB_REG (0x0102 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define SET_DELAY_MSB_REG (0x0103 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Cylces 64bit Write-register */
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#define SET_CYCLES_LSB_REG (0x0104 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define SET_CYCLES_MSB_REG (0x0105 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Frames 64bit Write-register */
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#define SET_FRAMES_LSB_REG (0x0106 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define SET_FRAMES_MSB_REG (0x0107 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Period 64bit Write-register */
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#define SET_PERIOD_LSB_REG (0x0108 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define SET_PERIOD_MSB_REG (0x0109 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Pattern Control FPGA registers --------------------------------------------------*/
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// /* Pattern IO Control 64 bit RW Register
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// * Each bit configured as output(1)/ input(0) */
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// #define PATTERN_IO_CNTRL_LSB_REG (0x88 + BASE_CONTROL)
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// #define PATTERN_IO_CNTRL_MSB_REG (0x8C + BASE_CONTROL)
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/* Pattern Limit RW Register */
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#define PATTERN_LIMIT_REG (0x1000 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_LIMIT_STRT_OFST (0)
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#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
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#define PATTERN_LIMIT_STP_OFST (16)
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#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
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/* Pattern Wait Timer 0 64bit RW Register */
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#define PATTERN_WAIT_TIMER_0_LSB_REG (0x1100 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_TIMER_0_MSB_REG (0x1101 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Pattern Wait 0 RW Register*/
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#define PATTERN_WAIT_0_ADDR_REG (0x1102 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_0_ADDR_OFST (0)
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#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
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/* Pattern Loop 0 Iteration RW Register */
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#define PATTERN_LOOP_0_ITERATION_REG (0x1103 * REG_OFFSET + BASE_PATTERN_CONTROL) // patnloop
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/* Pattern Loop 0 Address RW Register */
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#define PATTERN_LOOP_0_ADDR_REG (0x1104 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
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#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
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/* Pattern Wait Timer 1 64bit RW Register */
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#define PATTERN_WAIT_TIMER_1_LSB_REG (0x1105 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_TIMER_1_MSB_REG (0x1106 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Pattern Wait 1 RW Register*/
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#define PATTERN_WAIT_1_ADDR_REG (0x1107 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_1_ADDR_OFST (0)
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#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
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/* Pattern Loop 1 Iteration RW Register */
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#define PATTERN_LOOP_1_ITERATION_REG (0x1108 * REG_OFFSET + BASE_PATTERN_CONTROL) // patnloop
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/* Pattern Loop 1 Address RW Register */
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#define PATTERN_LOOP_1_ADDR_REG (0x1109 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
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#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
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/* Pattern Wait Timer 2 64bit RW Register */
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#define PATTERN_WAIT_TIMER_2_LSB_REG (0x110A * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_TIMER_2_MSB_REG (0x110B * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Pattern Wait 2 RW Register*/
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#define PATTERN_WAIT_2_ADDR_REG (0x110C * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_2_ADDR_OFST (0)
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#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
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/* Pattern Loop 2 Iteration RW Register */
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#define PATTERN_LOOP_2_ITERATION_REG (0x110D * REG_OFFSET + BASE_PATTERN_CONTROL) // patnloop
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/* Pattern Loop 0 Address RW Register */
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#define PATTERN_LOOP_2_ADDR_REG (0x110E * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
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#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
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/* Register of first word */
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#define PATTERN_STEP0_LSB_REG (0x0 * REG_OFFSET + BASE_PATTERN_RAM)
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#define PATTERN_STEP0_MSB_REG (0x1 * REG_OFFSET + BASE_PATTERN_RAM)
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