mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-26 08:10:02 +02:00
6e6fcec698
* MY3.0:read and write Registers, frames, cycles, delay * write pattern seems to work * done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos) * clk check for aquistition time * clk check for aquistition time * Update slsDetectorServer_defs.h * Update slsDetectorFunctionList.c
161 lines
6.4 KiB
C
161 lines
6.4 KiB
C
// stuff from Carlos
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#pragma once
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/* Definitions for FPGA*/
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#define BASE_CONTROL (0x0)
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#define BASE_PATTERN_CONTROL (0x200 )
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#define BASE_PATTERN_RAM (0x10000 )
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/* Basic detector FPGA registers --------------------------------------------------*/
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/* FPGA Version register */
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#define FPGA_VERSION_REG (0x04 + BASE_CONTROL)
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#define FPGA_COMPILATION_DATE_OFST (0)
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#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
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#define DETECTOR_TYPE_OFST (24)
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#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
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/* Module Control Board Serial Number Register */
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#define MCB_SERIAL_NO_REG (0x00 + BASE_CONTROL)
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/* API Version Register */
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#define API_VERSION_REG (0x08 + BASE_CONTROL)
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/* Fix pattern register */
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#define FIX_PATT_REG (0x0C + BASE_CONTROL)
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#define FIX_PATT_VAL (0xACDC2019)
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/* Status register */
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#define STATUS_REG (0x10 + BASE_CONTROL)
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#ifdef VIRTUAL // until firmware is ready ----------------------------------
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#define RUN_BUSY_OFST (0)
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#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
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#endif
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/* Look at me register */
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#define LOOK_AT_ME_REG (0x14 + BASE_CONTROL) //Not used in firmware or software, good to play with
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/* Pattern Control FPGA registers --------------------------------------------------*/
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/* Pattern status Register*/
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#define PAT_STATUS_REG (0x00 + BASE_PATTERN_CONTROL)
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/* Delay left 64bit Register */
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#define GET_DELAY_LSB_REG (0x08 + BASE_PATTERN_CONTROL)
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#define GET_DELAY_MSB_REG (0x0C + BASE_PATTERN_CONTROL)
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/* Cycles left 64bit Register */
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#define GET_CYCLES_LSB_REG (0x10 + BASE_PATTERN_CONTROL)
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#define GET_CYCLES_MSB_REG (0x14 + BASE_PATTERN_CONTROL)
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/* Frames left 64bit Register */
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#define GET_FRAMES_LSB_REG (0x18 + BASE_PATTERN_CONTROL)
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#define GET_FRAMES_MSB_REG (0x1C + BASE_PATTERN_CONTROL)
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/* Period left 64bit Register */
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#define GET_PERIOD_LSB_REG (0x20 + BASE_PATTERN_CONTROL)
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#define GET_PERIOD_MSB_REG (0x24 + BASE_PATTERN_CONTROL)
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/* Delay 64bit Write-register */
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#define SET_DELAY_LSB_REG (0x88 + BASE_PATTERN_CONTROL)
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#define SET_DELAY_MSB_REG (0x8C + BASE_PATTERN_CONTROL)
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/* Cylces 64bit Write-register */
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#define SET_CYCLES_LSB_REG (0x90 + BASE_PATTERN_CONTROL)
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#define SET_CYCLES_MSB_REG (0x94 + BASE_PATTERN_CONTROL)
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/* Frames 64bit Write-register */
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#define SET_FRAMES_LSB_REG (0x98 + BASE_PATTERN_CONTROL)
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#define SET_FRAMES_MSB_REG (0x9C + BASE_PATTERN_CONTROL)
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/* Period 64bit Write-register */
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#define SET_PERIOD_LSB_REG (0xA0 + BASE_PATTERN_CONTROL)
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#define SET_PERIOD_MSB_REG (0xA4 + BASE_PATTERN_CONTROL)
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/* Pattern Control FPGA registers --------------------------------------------------*/
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// /* Pattern IO Control 64 bit RW Register
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// * Each bit configured as output(1)/ input(0) */
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// #define PATTERN_IO_CNTRL_LSB_REG (0x88 + BASE_CONTROL)
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// #define PATTERN_IO_CNTRL_MSB_REG (0x8C + BASE_CONTROL)
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/* Pattern Limit RW Register */
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#define PATTERN_LIMIT_REG (0x100 + BASE_PATTERN_CONTROL)
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#define PATTERN_LIMIT_STRT_OFST (0)
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#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
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#define PATTERN_LIMIT_STP_OFST (16)
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#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
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/* Pattern Wait 0 RW Register*/
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#define PATTERN_WAIT_0_ADDR_REG (0x188 + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_0_ADDR_OFST (0)
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#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
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/* Pattern Wait 1 RW Register*/
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#define PATTERN_WAIT_1_ADDR_REG (0x19C + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_1_ADDR_OFST (0)
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#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
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/* Pattern Wait 2 RW Register*/
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#define PATTERN_WAIT_2_ADDR_REG (0x1B0 + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_2_ADDR_OFST (0)
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#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
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/* Pattern Wait Timer 0 64bit RW Register */
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#define PATTERN_WAIT_TIMER_0_LSB_REG (0x180 + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_TIMER_0_MSB_REG (0x184 + BASE_PATTERN_CONTROL)
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/* Pattern Wait Timer 1 64bit RW Register */
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#define PATTERN_WAIT_TIMER_1_LSB_REG (0x194 + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_TIMER_1_MSB_REG (0x198 + BASE_PATTERN_CONTROL)
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/* Pattern Wait Timer 2 64bit RW Register */
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#define PATTERN_WAIT_TIMER_2_LSB_REG (0x1A8 + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_TIMER_2_MSB_REG (0x1AC + BASE_PATTERN_CONTROL)
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/* Pattern Loop 0 Address RW Register */
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#define PATTERN_LOOP_0_ADDR_REG (0x190 + BASE_PATTERN_CONTROL)
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#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
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#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
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/* Pattern Loop 1 Address RW Register */
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#define PATTERN_LOOP_1_ADDR_REG (0x1A4 + BASE_PATTERN_CONTROL)
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#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
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#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
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/* Pattern Loop 0 Address RW Register */
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#define PATTERN_LOOP_2_ADDR_REG (0x1B8 + BASE_PATTERN_CONTROL)
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#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
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#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
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/* Pattern Loop 0 Iteration RW Register */
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#define PATTERN_LOOP_0_ITERATION_REG (0x18C + BASE_PATTERN_CONTROL) // patnloop
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/* Pattern Loop 1 Iteration RW Register */
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#define PATTERN_LOOP_1_ITERATION_REG (0x1A0 + BASE_PATTERN_CONTROL) // patnloop
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/* Pattern Loop 2 Iteration RW Register */
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#define PATTERN_LOOP_2_ITERATION_REG (0x1B4 + BASE_PATTERN_CONTROL) // patnloop
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/* Register of first word */
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#define PATTERN_STEP0_LSB_REG (0x0 + BASE_PATTERN_RAM)
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#define PATTERN_STEP0_MSB_REG (0x4 + BASE_PATTERN_RAM)
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