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c4675da0c3
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m3: reset fixed
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2019-11-22 16:40:43 +01:00 |
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d07873ee39
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mythen3 and gotthard2: wait request not needed, reset to be implemented
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2019-11-22 11:29:24 +01:00 |
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781e8fc67f
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mythen3: workaround for busy signal
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2019-11-20 11:57:14 +01:00 |
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2123fb47a5
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mythen3: config reg enable all counters, dr
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2019-11-11 10:41:42 +01:00 |
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1797d39216
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updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings
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2019-11-06 18:58:22 +01:00 |
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Marie Andrae
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7de9401bc7
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powerchip for mythen3
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2019-11-06 11:50:09 +01:00 |
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f9fff97f8a
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mythen3 register mix up
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2019-10-31 14:48:53 +01:00 |
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Dhanya Thattil
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995f0924e5
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Commandline (#66)
* WIP
* WIP
* removed status to string from defs
* WIP
* WIP
* WIP removed unused functions in multi
* WIP
* print hex in a terrible way
* WIP, loadconfig error
* WIP, type to string
* WIP
* fix to conversion
* WIP, hostname doesnt work
* WIP
* WIP
* WIP
* WIP, threshold
* WIP, threshold
* WIP
* WIP, triggers
* WIP, cycles to triggers
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* rx_udsocksize fx, WIP
* WIP
* WIP
* WIP
* file index (64 bit), WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* merge
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* New python mod
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2019-10-21 10:29:06 +02:00 |
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Marie Andrä
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9b4fc02b0e
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start/stop statemachine for my3 (#68)
* start/stop statemachine for my3
* runStatus, readFrame, runBusy (use CONTROL_REG) for mythen3
* registers for Pavel
* change dac names Mythen3
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2019-10-09 13:52:07 +02:00 |
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Marie Andrä
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5f94b5c246
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Dac (#67)
* dac WIP
* dacs WIP
* DACs are working with names
* namechanges of vrfsh->vshaper, vrfshnpol->vshaperneg
* pattern for MY3, configure MAC for MY3
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2019-10-07 12:13:25 +02:00 |
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Marie Andrä
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6e6fcec698
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MY3.0:read and write Registers, frames, cycles, delay (#64)
* MY3.0:read and write Registers, frames, cycles, delay
* write pattern seems to work
* done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos)
* clk check for aquistition time
* clk check for aquistition time
* Update slsDetectorServer_defs.h
* Update slsDetectorFunctionList.c
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2019-09-30 14:36:33 +02:00 |
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Marie Andrä
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4b987abf41
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Niosmarie (#63)
* HV for Mythen3 server
* HV for mythen3 server
* corrected upstreams
* missing endif
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2019-09-03 09:36:02 +02:00 |
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Marie Andrä
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f981825172
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virtual UDP for mythen3 (#55)
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2019-08-26 10:53:17 +02:00 |
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4b7ab98135
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initial functions for mythen3
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2019-08-22 15:55:27 +02:00 |
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72362b0334
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first version of mythen3
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2019-08-22 12:34:06 +02:00 |
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