- do not validate write reg, setbit and clearbit by default anymore
- --validate will force validation on the bitmask or entire reg
- remove return value for write reg (across server to client, but thankfully not in the Detector class)
- extend validation into writereg, setbit and clearbit for Eiger (always special)
- need to check python (TODO)
- missed the rx_zmqip implementations in detector.h and python bindings
* put back code to obtain adc and dac device indexafter loading device tree and then create folder iio_device_links and create symbolic links there according to device indices found. ln -sf operation not permitted, so folder has to be deleted and created everytime. Also refactored definitions to have all the xilinx name or detector specific stuff out of programbyArm.c
* uncommented waittransceiverreset at startup (should work now) and return of powering off chip at startup (error for transceiver alignment reset)
* updated registerdefs from firmware
* minor prints and updating names from registerdefs
* waittransceiverreset has been fixed in firmware and removing warnign for that, transceiver alignment check for powering off chip is not done in fw (giving a warning and returning ok for now)
* fixing ipchecksum (not done), removed startperiphery, allowing readout command to be allowed for xilinx when acquiring
* m3: fixed stop server not starting up with setup variables
* all servers except eiger fixed for virtual stop server to start up with setupDetector function called
* virtual tests work
* eiger: versions print neednt be in stop server
* jungfrau: stop server (not virtual) also needs to read config file
* ensuring master is setup for virtual and real servers
* voltage regulators only looks at dac and not at ctrl_reg
* xilinx: change dac max to 2048, setting dac ist not inverse conversion from dac to voltage anymore, but setting power is inverse, also there is max and min to power, a different min for vio and this is checked at funcs interface, not printign or converting to mv in dac for power regulators (as its conversion max and min are different)
* Use links for dacs/adc and adapt power rglt thresholds
* Remove wait for transceiver reset
* adc and dac device not used anymore and hence removed
* udp restucturing: arm has to be multiple of 16 and no byteswap in udp_gen, option to compile locally in arm architecture, memsize of the second udp memory has to be limited
---------
Co-authored-by: Martin Brückner <martin.brueckner@psi.ch>
* changed common.c readADCFromFile to make it more general and move temperature calculation for Eiger out of this function and inside whereever it is called.
* g2 and m2: gethighvoltage was just a variable set in server, it is now moved to a get inside DAC5671 implementation (but not reading a measured value, instead what is set from a file), high voltage variable used inside DAC5671 for virtual servers
* g2: switching off hv (ifrom non zero to zero value) will wait for 10s; powering on chip reconfigures chip; powering off chip unconfigures chip; powering off chip also includes check if hv = 0, if not throw exception; chip configuration checked before acquring; at start up: hv switched off and chip powered on, so does not wait 10s to switch off hv;
* included test to check powering off chip when hv is on should throw an exception
* g2: check if chip configured before acquiring
* nios: read hv value set from file and virtual still goes into DAC5671 for conversions to and fro dac to V, change common readadc to readparameter to generalize, make sethighvoltage into a get and set to catch errors in get as well, g2: if not at startup, remmeber hv value before setting it and after check if value was being switched off (from a non zero value) and wait 10s if it was (10s wait only for switching off from non zero and not at startup)
* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)
* g2: startup clk div back to 10 as in firmware but setting in software startup to 20
* m3: minor print error if clk divider > max
* period and exptime(patternwaittime level 0)
* added new regsieterdefs and updated api version and fixedpattern reg
* autogenerate commands
* formatting
* minor
* wip resetflow, readout mode, transceiver mask, transceiver enable
* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw
* programming fpga and device tree done
* most configuration done, need to connect configuretransceiver to client
* stuck at resetting transciever timed out
* minor
* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber
* configuretransceiver from client, added help in client
* make formatt and command generation
* tests for xilinx ctb works
* command generation
* dacs added and tested, power not done
* power added
* added temp_fpga
* binaries in
* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed
* start works
* virtual server sends
* receiver works
* tests
* python function and enum generation, commands generatorn and autocomplete, formatting, tests
* tests fail at start(transceiver not aligned)
* tests passed
* all binaries compiled
* eiger binary in
* added --nomodule cehck for xilinx
* implemented testbus, testfpga, set/get #frames, triggers, allowed that and for connection to client, also allowed, getnumchannels, configuremac, getrunstatus, setdetectorposition with dummy values
* connected kernelversion, hardwareversion, versions, framesl, triggersl, dr, timingmode, pattern (except patioctrl) thats there for altera ctb
* replaced set/get64Bit to set/getU64bit in all loadpattern.c for (ctb and m3 also)
* implemented testbus, testfpga, set/get #frames, triggers, allowed that and for connection to client, also allowed, getnumchannels, configuremac, getrunstatus, setdetectorposition with dummy values
* allowing tests for xilinx
* binaries in
* updated registers, arm64
* compiler set to aarch64 for xilinx server
* updated RegisterDefs.h
* merge into generate branch and resolving conflicts and adding the xilinx changes to callerspecial and commands.yaml
* compiles and can print firmware version (using a different csp0 address)
* fixing other servers (gotthard, jungfrau, moench, mythen3) that it returns in case of mapping failure, xilinxctb: added that it checks type, prints proper fw version, checks kernel date, added armprocessor define to use in common places, added specifiers to supress overflow and truncation warnings
* added detector ip and mac adddress to the printout
* fixed tests and recompiled servers
* draft to fix virtual test when it fails
* catching errors in tests and removing sigchild ignore so servers (process in background) executing commands will not fail (pclose no child processes, if sigchld is ignored) fixed
* uncommented python loading config
* somehow killal slsReciever in second detector test fails even though no receiver running
* fixing script for virtual simlator test:fixed issue with check if process running, fixed moench tests
* merge fix from 7.0.2: new jungfrau fw versions, incremented binary, hdf5 and json versions
* moench: changed dac names and default values to old moench values
* moench: remove interface clk polarity at start up
* moench: default speed is half speed, default values for adc offset and adc phase for different speeds (only half speed confirmed), adc vref voltage to 2.0 like G1
* moench: connected adc pipeline to client
* moench: receiver- default frames per file is 100k and discard partial frames as default
* moench binary in
* using tostring in gui for dacs
* moved frame discard policy as a parameter to be configured with a default depending on detector
* moench: 300 degrees for adc phase in full speed
* when dbit list is enabled, the size of data in zmq stream is changed to only the digital bits enabled size. now fixed to also include analog size
* allowing to set 0xffffffffffffffff to pat io control. prevously was used to do a get. fixed also for pat bit mask and pat mask
* moench, removed chip version, filter resistor, filter cells, currentsoures, gain mode, setttings(modes), dbitphase, maxdbitphase, autocompdisable, comparatordisabletime, made acq start and stop a pulse, removed unused registers
* added parallel command
* remove gain plot for moench
* moench: updated adc invert val
* moench: update adcoffset to 0xf and adcphase to 140 degrees
* removed sync clock in moench
* updated min fw version
* removing config file in moench server
* merge fix from #721 PR (sync) 7.0.2.rc -> developer
* row and column for jungfrau mixed up
* multi module jungfrau sync must do slaves first then master for start acquisition and send software trigger, and master first and then slaves for stopacquisition
* non blocking to slaves first and only then blocking/nonblocking to the master for sending software trigger(jungfrau multi mod sync)
* fixed get/set timing jungfrau when sync enabled, getsync during blocking acquire (for trigger or stop) will get stuck as it should ask the stop server
* switching between 1 and 2 interfaces did not set gui/client zmq port properly. Resulted in dummy streaming forever. fixed
* formatting, refactoring: const & for positions, multi mod M3 stop first master first
* adding missing cstdint for gcc 13
* Refactoring handle sync out, handling synchronization also for softwaretrigger for m3, for start/sync/stop for g2/g1
---------
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
* fixed row and col for moench 2 interfaces
* fix moench getTiming and also allow moench to handle sync
---------
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
* copied jungfrau server to moench and adapted
* fixed image size and num packets
* read n rows allows 16
* commneted out configure_asic_timer at server startup. To be removed later the ASIC_CTRL_REG and storage cell options
* moench:removing the decrement (which was in jf) in read n rows to register
* removed lblsamples from gui
