Dhanya Thattil ce7f01bdc4

Dev: m3 clkdiv0 20 (#924) ...

* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)

* g2: startup clk div back to 10 as in firmware but setting in software startup to 20

* m3: minor print error if clk divider > max

2024-07-25 17:18:45 +02:00

..

bin

Dev: m3 clkdiv0 20 (#924)

2024-07-25 17:18:45 +02:00

CMakeLists.txt

Moench rw3 (#745)

2023-05-25 11:00:23 +02:00

detid_moench.txt

Moench rewrite (#597)

2022-12-15 09:16:51 +01:00

Makefile

Moench rw3 (#745)

2023-05-25 11:00:23 +02:00

RegisterDefs.h

Moench dacs defaults (#788)

2023-07-31 14:02:30 +02:00

slsDetectorFunctionList.c

moench default speed set to after init readout configuration (half speed) (#886)

2024-01-11 18:07:34 +01:00

slsDetectorServer_defs.h

moench server: changed default values of adcphase for full speed from 300 to 150 and dac vipre_cds from 800 to 1280 (#922)

2024-07-15 12:31:53 +02:00