maliakal_d
f626db454e
updated gotthard2, mythen3 binaries
2020-04-28 17:07:18 +02:00
maliakal_d
86b39853a3
gotthard2, mythen3: making them clkdivider dependant and not clkfrequency, binaries not loaded yet
2020-04-28 17:04:57 +02:00
maliakal_d
2f33a1a479
updated binaries
2020-04-09 09:35:46 +02:00
maliakal_d
0652ff6b5a
updated binaries
2020-04-09 08:37:27 +02:00
maliakal_d
07cd71f0c7
removed update shared memory from detector, check if eiger firmware >=26: have same top and bottom addresses
2020-04-07 17:19:47 +02:00
maliakal_d
bdf0f9e2b9
fixed start stop tests
2020-04-07 10:39:50 +02:00
maliakal_d
83283b672a
WIP
2020-04-06 19:38:35 +02:00
maliakal_d
456b96446f
WIP
2020-04-06 17:59:06 +02:00
maliakal_d
80e55cd4da
WIP
2020-04-06 17:28:05 +02:00
maliakal_d
47b0e46f15
Merge branch 'developer' into testing
2020-04-06 10:55:41 +02:00
fdb6e3f3d4
Removeshm ( #90 )
...
* eiger: moved rate correction outside, fixed threshold energy bug in client (binaries not updated yet)
* removed dr and deadtiem from shm
* help for rx_status and status to point them to rx_Start, rx_stop, start and stop
* moved progress to receiver
* removed currentsettings from eiger shm
* updated server binaries, and client api
* moench and ctb virtual servers compile fix
* gui: moved acquire to a concurrent qt thread so it doesnt block updateplot
2020-04-06 10:44:44 +02:00
maliakal_d
eeed102bf3
somewhere between fork and pipes, crashes at sendingudppacket at print
2020-04-03 20:18:16 +02:00
maliakal_d
262b4b0b16
more tests
2020-03-31 18:19:32 +02:00
maliakal_d
83010de9f4
updated all binaries, previous ones may not work
2020-03-31 16:58:35 +02:00
maliakal_d
f2dd146e56
updates on servers (mainly virtual): indices, dbit clock not allowed for moench anymore
2020-03-31 16:54:35 +02:00
maliakal_d
6289163ac8
virtual servers checked
2020-03-31 10:40:42 +02:00
maliakal_d
3ba9e5ec22
eiger, jungfrau, ctb, moench, gotthard virtual servers checked
2020-03-30 18:24:42 +02:00
d58eb1dc6e
Gappixels ( #89 )
...
* WIP
* WIP virtual delays, imagetest for saturation
* WIP, vertical and horizontal
* WIP
* gap pixels work, fixed 32 bit data out (10gbe=0) for virtual servers
* quad works (also in virtual), handling gappixels and quad
* jungfrau gapppixels work
* jungfrau: done
* complete image or missing packets given in json header and gui
* eiger virtual 4 bit mode bug fix
* working version of zmq add json header, except printout
* printout bug
* fix for json para
* to map WIP
* map done
* map print , mapwith result left
* json result works, testing added
* updated server binaries
* compiling on rhels7, variable size char array iniitalization
* zmqsocket parsing didnt need Document
* const to map, json para is strings not map
* json add header: mapping cleaner without insert make_pair
2020-03-30 14:54:35 +02:00
0de0d82a1a
replaced old logger
2020-03-11 12:40:12 +01:00
maliakal_d
2cb09a590a
gotthard2, mythen3: firmware type check added, others: minor print
2020-03-10 16:25:07 +01:00
maliakal_d
df2512fb1c
all servers: eiger, jungfrau, gotthard, ctb, moench, mythen3, gotthard2 updated
2020-03-10 15:57:27 +01:00
maliakal_d
e4942a5c8d
virtual servers warnings fixed
2020-03-10 15:53:44 +01:00
maliakal_d
ac1c40d6f9
virtual servers: redundant declarations fixed
2020-03-10 15:50:33 +01:00
maliakal_d
5192dae9c5
removed virtual server warnings
2020-03-10 15:15:09 +01:00
bd6529a64c
warnings for virtual servers
2020-03-10 09:27:23 +01:00
maliakal_d
9ca86c2edb
ctb, gotthard, gotthard2, jungfrau, mythen updated
2020-03-05 10:21:24 +01:00
maliakal_d
90acd51389
server api changes: for mythen3, jungfrau, eiger as well
2020-02-26 17:52:35 +01:00
maliakal_d
02b367ffe8
mythen3 and gotthard2: updated clocks
2020-02-24 16:50:47 +01:00
maliakal_d
89c774dbf7
nios programming: check file size first
2020-01-31 11:24:48 +01:00
5ca3a1b685
gotthard2 and mythen3: programming fpga, reboot; jungfrau, ctb: modified programming ( #74 )
2020-01-30 19:52:35 -08:00
maliakal_d
f881133795
get/set timing, generate data for gotthard2, vref_rstore instead of restore for gotthard2
2020-01-22 18:18:56 +01:00
maliakal_d
8cbf3c62a9
merge from developer
2020-01-22 17:30:13 +01:00
maliakal_d
3ea2520615
PR minor changes
2020-01-22 13:55:10 +01:00
maliakal_d
981b13494c
mythen3: virtual server, connected timing mode, row and col in header, included pattern bit and mask
2020-01-21 18:16:27 +01:00
maliakal_d
6e47f0b7f7
merge resolved
2020-01-20 11:36:35 +01:00
maliakal_d
3c891495db
mythen3: bug fix detector type
2020-01-20 11:32:02 +01:00
maliakal_d
e8bdf5a505
gotthard2: updated register map; powerchip checking detector type; internal and external period, frames, exptime; set/get delay, get actualtime, measurement, framesfromstart enabled; which detector comment updated in cmdproxy, detector and slsdetector
2020-01-16 15:33:35 +01:00
de53747ddd
Counters ( #71 )
...
* mythen3: adding counters mask, firmware still takes only number of counters for now
* mythen3: checking if module attached before powering on chip
* bug fix: loop inital declaration not allowed in c
* fix scope eiger test
* mythen3: renamed setCounters to setCounterMask and getCounterMask in API
* mythen3 replacing counting bits with popcount
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com >
2020-01-14 17:40:46 +01:00
maliakal_d
086cbacd84
mythen3: connected busy signal insttead of timer
2019-12-10 11:03:27 +01:00
maliakal_d
9455a5fba1
ctb: adcenable10g included, 10g readout enables included
2019-11-27 17:28:57 +01:00
maliakal_d
94382c1ece
m3 and g2: while setting clock freq, change phase only if there is a change in phase (removing more printouts, will still only set if needed )
2019-11-25 10:54:30 +01:00
maliakal_d
a95ab1e13e
servers: default compile not update versionign
2019-11-22 17:23:07 +01:00
maliakal_d
c4675da0c3
m3: reset fixed
2019-11-22 16:40:43 +01:00
maliakal_d
ba008db29a
m3 ang g2: reset not yet imple
2019-11-22 11:54:45 +01:00
maliakal_d
d07873ee39
mythen3 and gotthard2: wait request not needed, reset to be implemented
2019-11-22 11:29:24 +01:00
maliakal_d
f8df11886a
ctb: change in phase done in degrees (phase reset due to change in frequency)
2019-11-21 15:08:38 +01:00
maliakal_d
c4ae32b216
mythen3: setting clk frequecy and phase shifts work
2019-11-21 14:36:37 +01:00
maliakal_d
fea94b15d5
mythen3:forgot binary
2019-11-21 13:48:39 +01:00
maliakal_d
955bc74a91
mythen3: change vco freq to 1.25GHz
2019-11-21 13:38:54 +01:00
maliakal_d
781e8fc67f
mythen3: workaround for busy signal
2019-11-20 11:57:14 +01:00
maliakal_d
Dhanya Thattil