maliakal_d
3c723990f1
dacs should work now even in tests
2026-03-24 15:10:14 +01:00
maliakal_d
30c1ee17bc
ctb dacs, yet to do othe rdacs
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2026-03-24 12:32:28 +01:00
maliakal_d
fdebe53ab7
fix dac default names and test for dacs
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2026-03-24 12:08:09 +01:00
maliakal_d
fb3c0539db
added dac test
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2026-03-24 11:44:53 +01:00
maliakal_d
3c2c3b3180
throw approperiate error when no modules added for powers
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2026-03-24 11:20:37 +01:00
maliakal_d
fefbab77de
moved signallist, adclist, slowadc, slowadclist to Ctb
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2026-03-23 17:24:42 +01:00
maliakal_d
2843d2b527
fixed tests to work for powelist in Ctb
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2026-03-23 17:03:15 +01:00
maliakal_d
fda27d05f3
python: moved powerlist to Ctb
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2026-03-23 16:32:31 +01:00
maliakal_d
e557096047
wip
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2026-03-23 12:36:09 +01:00
maliakal_d
a5612f1161
fixes for python api
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2026-03-23 12:09:09 +01:00
maliakal_d
c891b906d4
fixed tests
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2026-03-20 15:52:01 +01:00
maliakal_d
ff0b3e1274
wip
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2026-03-19 17:28:29 +01:00
maliakal_d
01d90b8ba2
fix getdacindex and getdacname for normal detectors to throw if random index that doesnt fit to the detector
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2026-03-19 17:08:25 +01:00
maliakal_d
601c23f1af
pybindings
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2026-03-19 16:39:00 +01:00
maliakal_d
a32498ffb9
wip
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2026-03-19 15:43:14 +01:00
maliakal_d
ba99af8446
wip
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2026-03-18 22:50:17 +01:00
maliakal_d
4d2e3d8c9d
wip
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2026-03-18 18:46:21 +01:00
maliakal_d
171b131655
wip xilinx
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2026-03-18 18:36:57 +01:00
maliakal_d
0a1db69532
wip
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2026-03-18 17:21:01 +01:00
maliakal_d
1a99c21485
wip
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2026-03-18 16:13:10 +01:00
maliakal_d
8afeb92a32
wip
2026-03-18 16:07:21 +01:00
maliakal_d
567dc8af71
wip
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2026-03-18 10:09:33 +01:00
maliakal_d
3feed07d95
wip
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2026-03-17 17:26:57 +01:00
maliakal_d
16f8925ffa
wip
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2026-03-17 16:03:45 +01:00
maliakal_d
8fcff75086
wip python
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2026-03-16 18:00:04 +01:00
maliakal_d
7621d964cd
configtransceiver is removed
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2026-03-13 16:59:28 +01:00
maliakal_d
bf25493de3
power all returns all
2026-03-13 16:51:41 +01:00
maliakal_d
a537de69c3
fixed powerchip for ctb
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2026-03-13 16:18:11 +01:00
maliakal_d
3b3180ef0f
wip. xilinx
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2026-03-13 12:32:47 +01:00
maliakal_d
afb808aef8
wip
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2026-03-13 11:35:21 +01:00
maliakal_d
951304c39c
fixed xilinx. python left
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2026-03-11 16:45:02 +01:00
maliakal_d
297e23d1d2
Merge branch 'developer' into dev/xilinx_power_cmd
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2026-03-11 15:39:58 +01:00
maliakal_d
03df08cb8c
python cmds still left. wip
2026-03-11 15:38:02 +01:00
mazzol_a
c86ca1eaec
per default pyqtgraph should read array as row-major ( #1419 )
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* per default pyqtgraph should read array as row-major
* dont transform for analog images
* never flip rows
2026-03-11 12:28:42 +01:00
maliakal_d
8bed67b8c8
added vchip check
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2026-03-11 11:33:17 +01:00
maliakal_d
7b305a1faf
fixed some tests
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2026-03-09 18:01:19 +01:00
maliakal_d
4875597533
wip: ctb power works, tests left
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2026-03-09 15:54:18 +01:00
maliakal_d
0fe1df7959
wip. client and xilinx todo
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2026-03-06 21:24:00 +01:00
maliakal_d
c2e8d5954d
wip: power in client, tests, and fixed server interfaces and ctb implementation, not tested
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2026-03-06 14:23:34 +01:00
maliakal_d
3846aec46e
Dev/jungfrau 1m root display support ( #1364 )
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* Aldo Mozzanica added support for 2 modules in 1M configuration for root display
* deleted the wrong files
2026-03-05 17:13:38 +01:00
maliakal_d
6982b8cfa4
rm unnecessary hidden test tags ( #1415 )
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* removed hidden tags other than .detectorintegration and .disable_check_data_file
* updated label, minor
2026-03-05 17:11:56 +01:00
maliakal_d
4723eb2ff4
dacs with power dac names should work and do not take in dac units to avoid ambiguity, test with 0 value for power dacs should fail, to do: implement power commands
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2026-03-05 17:09:00 +01:00
maliakal_d
b2cd043358
Merge branch 'developer' into dev/xilinx_power_cmd
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2026-03-05 12:34:49 +01:00
maliakal_d
384b2480ab
Dev/fix no rx roi port ( #1372 )
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* rx_roi fixed when there is no roi for a particular port. Fixed tests for it
* removing todo check if files created because its not enough to count matching pattern file names, but also look at timestamp and create files with timestamp else you read older ones. For now, checking individual rois is enough
* restore md5
---------
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com >
2026-03-05 12:28:57 +01:00
a1b8dccdd9
added support for int() for RegisterAddress and RegisterValue ( #1414 )
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2026-03-05 11:35:21 +01:00
9f72688b9c
Adding offset to RegisterAddress ( #1413 )
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* implemented + and += for RegisterAddres and tests plus test cleanup
2026-03-05 09:32:21 +01:00
mazzol_a
6e090dbba2
Dev/update workflows ( #1406 )
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* only run tests for pull-requests
* build gui and simulators
* trigger upon push to all branches
* renamed workflows
* added python tests
* added colorama and numpy
* added slsdet to pythonpath
* updated workflow name
2026-03-02 14:30:27 +01:00
maliakal_d
60f5db1224
xilinx: slow adcs ( #1405 )
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* xilinx: slow adcs
* minor
* xilinx: max reference voltage back to 2500mV for slow adcs ad7689
2026-02-27 17:17:11 +01:00
maliakal_d
a3e6cc90ea
server versions werent getting updated ( #1407 )
2026-02-27 17:12:27 +01:00
maliakal_d
0c5a9ceafc
binary in
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2026-02-27 16:12:14 +01:00
maliakal_d
mazzol_a
Erik Fröjdh