* added readoutspeed command to m3 (fullspeed - 10, half speed - 20, quarter speed - 40), removed reaodut pll, moved up system pll clock indices, leaving pll index in common altera code, default speed is half speed, allow only system_c0 to be set, the others can be obtained, same for clkphase, maxclkphaseshift, clkfreq. added to readoutspeedlist commands, updated help and updated tests
* updated readoutspeedlist command
* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)
* g2: startup clk div back to 10 as in firmware but setting in software startup to 20
* m3: minor print error if clk divider > max
* period and exptime(patternwaittime level 0)
* added new regsieterdefs and updated api version and fixedpattern reg
* autogenerate commands
* formatting
* minor
* wip resetflow, readout mode, transceiver mask, transceiver enable
* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw
* programming fpga and device tree done
* most configuration done, need to connect configuretransceiver to client
* stuck at resetting transciever timed out
* minor
* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber
* configuretransceiver from client, added help in client
* make formatt and command generation
* tests for xilinx ctb works
* command generation
* dacs added and tested, power not done
* power added
* added temp_fpga
* binaries in
* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed
* start works
* virtual server sends
* receiver works
* tests
* python function and enum generation, commands generatorn and autocomplete, formatting, tests
* tests fail at start(transceiver not aligned)
* tests passed
* all binaries compiled
* eiger binary in
* added --nomodule cehck for xilinx
* badchannels for m3 and modify for g2 (file from single and multi)
* m3: invert polarity of bit 7 and 11 signals from setmodule, allow commas in bad channel file
* badchannel file can take commas, colons and comments (also taking care of spaces at the end of channel numbers)
* tests 'badchannels' and 'Channel file reading' added, removing duplicates in badchannel list, defining macro for num counters in client side
* fix segfault when list from file is empty,
* fix tests assertion for ctbconfig (adding message) for c++11
* fixed badchannels in m3server (clocking in trimming)
* badchannel tests can be run from any folder (finds the file)
* vicin default changed to 800, only setting vthx directly allows to set dac even if counter disabled, else disable counter, setallthresholdenergy if an energy is -1, get module value, fix that reg was repaced by isettings
* vth3 disabled for interpolation enable, interpolation disable sets counter mask to what it was before (updating old mask whn setting counter mask except for setting all counters for interpolation enable) and enabling vth3 if counter was enabled
* refactor and test for previous commit
* pump probe only has vth2 enabled, handles both pump probe mode and interpolation mode as well
* wip
* refactored pump probe and interpolation and added to setmodule
* check dacs and trimbits out of range for setmodule (not just threshold)
* binaries in
* m3: pump probe and interpolation mutually exclusive
* minor
* Setting pattern from memory (#218)
* ToString accepts c-style arrays
* fixed patwait time bug in validation
* Introduced pattern class
* compile for servers too
* Python binding for Pattern
* added scanParameters in Python
* slsReceiver: avoid potential memory leak around Implementation::generalData
* additional constructors for scanPrameters in python
* bugfix: avoid potentital memory leak in receiver if called outside constructor context
* added scanParameters in Python
* additional constructors for scanPrameters in python
* M3defaultpattern (#227)
* default pattern for m3 and moench including Python bindings
* M3settings (#228)
* some changes to compile on RH7 and in the server to load the default chip status register at startup
* Updated mythen3DeectorServer_developer executable with correct initialization at startup
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
* Pattern.h as a public header files (#229)
* fixed buffer overflow but caused by using global instead of local enum
* replacing out of range trimbits with edge values
* replacing dac values that are out of range after interpolation
* updated pybind11 to 2.6.2
* Mythen3 improved synchronization (#231)
Disabling scans for multi module Mythen3, since there is no feedback of the detectors being ready
startDetector first starts the slaves then the master
acquire firs calls startDetector for the slaves then acquire on the master
getMaster to read back from hardware which one is master
* New server for JF to go with the new FW (#232)
* Modified Jungfrau speed settings for HW1.0 - FW fix version 1.1.1, compilation date 210218
* Corrected bug. DBIT clk phase is implemented in both HW version 1.0 and 2.0. Previous version did not update the DBIT phase shift on the configuration of a speed.
* fix for m3 scan with single module
* m3 fw version
* m3 server
* bugfix for bottom when setting quad
* new strategy for finding zmq based on cppzmq
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
Co-authored-by: Dhanya Thattil <33750417+thattil@users.noreply.github.com>
Co-authored-by: Alejandro Homs Puron <ahoms@esrf.fr>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
Co-authored-by: Xiaoqiang Wang <xiaoqiangwang@gmail.com>
Co-authored-by: lopez_c <carlos.lopez-cuenca@psi.ch>
* added temp m3 settings files
* renames settings noise to trim
* get threshold for M3
* some changes to compile on RH7 and in the server to load the default chip status register at startup
* Updated mythen3DeectorServer_developer executable with correct initialization at startup
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
