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https://github.com/slsdetectorgroup/slsDetectorPackage.git
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mythen3: fix of external signals to not allow master output inversion, but can edge detect not configurable, and default dout pulse length
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@ -186,12 +186,16 @@
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/** DOUTIF1 Master Ouput Register */
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#define DOUTIF1_REG (0x01 * REG_OFFSET + BASE_PIPELINE)
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#define DOUTIF1_BYPASS_OFST (0)
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#define DOUTIF1_BYPASS_MSK (0x0000000F << DOUTIF1_BYPASS_OFST)
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#define DOUTIF1_TRIGGER_BYPASS_OFST (0)
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#define DOUTIF1_TRIGGER_BYPASS_MSK (0x00000001 << DOUTIF1_TRIGGER_BYPASS_OFST)
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#define DOUTIF1_BYPASS_GATE_OFST (1)
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#define DOUTIF1_BYPASS_GATE_MSK (0x00000007 << DOUTIF1_BYPASS_GATE_OFST)
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#define DOUTIF1_INVERSION_OFST (4)
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#define DOUTIF1_INVERSION_MSK (0x0000000F << DOUTIF1_INVERSION_OFST)
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#define DOUTIF1_RISING_OFST (8)
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#define DOUTIF1_RISING_MSK (0x0000000F << DOUTIF1_RISING_OFST)
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#define DOUTIF1_RISING_TRIGGER_OFST (8)
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#define DOUTIF1_RISING_TRIGGER_MSK (0x00000001 << DOUTIF1_RISING_TRIGGER_OFST)
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#define DOUTIF1_RISING_GATE_OFST (9)
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#define DOUTIF1_RISING_GATE_MSK (0x00000007 << DOUTIF1_RISING_GATE_OFST)
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#define DOUTIF1_FALLING_OFST (12)
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#define DOUTIF1_FALLING_MSK (0x0000000F << DOUTIF1_FALLING_OFST)
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@ -211,13 +215,13 @@
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#define DOUTIF_RISING_LNGTH_REG (0x03 * REG_OFFSET + BASE_PIPELINE)
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#define DOUTIF_RISING_LNGTH_PORT_1_OFST (0)
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#define DOUTIF_RISING_LNGTH_PORT_1_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_1_OFST)
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#define DOUTIF_RISING_LNGTH_PORT_2_OFST (0)
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#define DOUTIF_RISING_LNGTH_PORT_2_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_2_OFST)
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#define DOUTIF_RISING_LNGTH_PORT_3_OFST (0)
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#define DOUTIF_RISING_LNGTH_PORT_3_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_3_OFST)
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#define DOUTIF_RISING_LNGTH_PORT_4_OFST (0)
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#define DOUTIF_RISING_LNGTH_PORT_4_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_4_OFST)
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#define DOUTIF_RISING_LNGTH_PORT_1_MSK (0x000000FF << DOUTIF_RISING_LNGTH_PORT_1_OFST)
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#define DOUTIF_RISING_LNGTH_PORT_2_OFST (8)
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#define DOUTIF_RISING_LNGTH_PORT_2_MSK (0x000000FF << DOUTIF_RISING_LNGTH_PORT_2_OFST)
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#define DOUTIF_RISING_LNGTH_PORT_3_OFST (16)
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#define DOUTIF_RISING_LNGTH_PORT_3_MSK (0x000000FF << DOUTIF_RISING_LNGTH_PORT_3_OFST)
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#define DOUTIF_RISING_LNGTH_PORT_4_OFST (24)
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#define DOUTIF_RISING_LNGTH_PORT_4_MSK (0x000000FF << DOUTIF_RISING_LNGTH_PORT_4_OFST)
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/* ASIC Exposure Control registers
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@ -1245,14 +1245,28 @@ enum timingMode getTiming() {
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void setInitialExtSignals() {
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LOG(logINFOBLUE, ("Setting Initial External Signals\n"));
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// default, everything is 0
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bus_w(DINF1_REG, 0);
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bus_w(DOUTIF1_REG, 0);
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bus_w(DINF2_REG, 0);
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bus_w(DOUTIF_RISING_LNGTH_REG, 0);
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// bypass everything
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// (except master input can edge detect)
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// (except master triggers can edge detect)
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bus_w(DINF1_REG, DINF1_BYPASS_GATE_MSK);
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bus_w(DOUTIF1_REG, DOUTIF1_BYPASS_MSK);
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bus_w(DOUTIF1_REG, DOUTIF1_BYPASS_GATE_MSK);
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bus_w(DINF2_REG, DINF2_BYPASS_MSK);
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// master input can edge detect, so rising is 1
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// master input/output can edge detect, so rising is 1
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bus_w(DINF1_REG, bus_r(DINF1_REG) | DINF1_RISING_TRIGGER_MSK);
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bus_w(DOUTIF1_REG, bus_r(DOUTIF1_REG) | DOUTIF1_RISING_TRIGGER_MSK);
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// set default value for master output rising pulse length for port1
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bus_w(DOUTIF_RISING_LNGTH_REG,
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bus_r(DOUTIF_RISING_LNGTH_REG) & ~DOUTIF_RISING_LNGTH_PORT_1_MSK);
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bus_w(DOUTIF_RISING_LNGTH_REG, bus_r(DOUTIF_RISING_LNGTH_REG) |
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((DEFAULT_MSTR_OTPT_P1_NUM_PULSES
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<< DOUTIF_RISING_LNGTH_PORT_1_OFST) &
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DOUTIF_RISING_LNGTH_PORT_1_MSK));
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}
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void setExtSignal(int signalIndex, enum externalSignalFlag mode) {
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@ -41,6 +41,7 @@
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#define DEFAULT_SYSTEM_C1 (10) //(125000000) // chip_clk, 125 MHz
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#define DEFAULT_SYSTEM_C2 (10) //(125000000) // sync_clk, 125 MHz
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#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
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#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
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/* Firmware Definitions */
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#define IP_HEADER_SIZE (20)
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@ -517,7 +517,16 @@ int set_external_signal_flag(int file_des) {
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functionNotImplemented();
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#else
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if (Server_VerifyLock() == OK) {
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if (signalIndex < 0 || signalIndex >= MAX_EXT_SIGNALS) {
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#ifdef MYTHEN3D
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// to be implemented in hardware as busy configurable
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if (signalIndex == 4) {
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ret = FAIL;
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sprintf(mess, "Signal index %d not configurable yet\n",
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signalIndex);
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LOG(logERROR, (mess));
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} else
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#endif
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if (signalIndex < 0 || signalIndex >= MAX_EXT_SIGNALS) {
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ret = FAIL;
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sprintf(mess, "Signal index %d can only be between 0 and %d\n",
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signalIndex, MAX_EXT_SIGNALS - 1);
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@ -923,9 +923,11 @@ class Detector {
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/** [Gotthard] signal index is 0
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* Options: TRIGGER_IN_RISING_EDGE, TRIGGER_IN_FALLING_EDGE
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* [Mythen3] signal index 0-3 for master input, 4-7 master output signals
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* Options: TRIGGER_IN_RISING_EDGE, TRIGGER_IN_FALLING_EDGE (for master
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* input trigger only), INVERSION_ON, INVERSION_OFF */
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* [Mythen3] signal index 0 is master input trigger signal, 1-3 for master
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* input gate signals, 4 is busy out signal, 5-7 is master output gate
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* signals.
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* Options: TRIGGER_IN_RISING_EDGE, TRIGGER_IN_FALLING_EDGE (for
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* master input trigger only), INVERSION_ON, INVERSION_OFF */
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void setExternalSignalFlags(int signalIndex, defs::externalSignalFlag value,
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Positions pos = {});
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@ -766,8 +766,9 @@ std::string CmdProxy::ExternalSignal(int action) {
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"[trigger_in_rising_edge|trigger_in_falling_edge]"
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"\n\t[Mythen3] [0-7] "
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"[trigger_in_rising_edge|trigger_in_falling_edge|inversion_on|"
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"inversion_off]\n\t where 0-3 is master input signals and 4-7 is "
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"master output signals"
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"inversion_off]\n\t where 0 is master input trigger signal, 1-3 "
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"is master input gate signals, 4 is busy out signal and 5-7 is "
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"master output gate signals"
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<< '\n';
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} else if (action == defs::GET_ACTION) {
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if (args.size() != 1) {
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