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almost done with ctb update, need to do slow adcs, split to moench and ctb

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This commit is contained in:
maliakal_d
2018-11-30 10:39:26 +01:00
parent c19c787904
commit 8f3f9caf2b
110 changed files with 4526 additions and 14397 deletions
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1
slsDetectorServers/gotthardDetectorServer/RegisterDefs.h
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@ -116,7 +116,6 @@
#define ADC_SYNC_ENET_DELAY_MSK (0x000000FF << ADC_SYNC_ENET_DELAY_OFST)
#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL ((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_DELAY_ROI_VAL ((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
//FIXME: try with just 0x8 and 0x1.. it is anded with 0000 in firmware anyway
/** Time From Start register */
//#define MU_TIME_REG (0x1a << MEM_MAP_SHIFT)

1
slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c
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@ -783,7 +783,6 @@ ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret) {
int i = 0;
for (i = 0; i < n; ++i) {
FILE_LOG(logINFO, ("\t(%d, %d)\n", arg[i].xmin, arg[i].xmax));
}
}
// only one ROI allowed per module

3
slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h
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@ -51,6 +51,9 @@ enum DACINDEX {VREF_DS, VCASCN_PB, VCASCP_PB, VOUT_CM, VCASC_OUT, VIN
#define DEFAULT_PHASE_SHIFT (120)
#define DEFAULT_TX_UDP_PORT (0xE185)
#define MAX_DAC_VOLTAGE_VALUE (2500)
#define MAX_DAC_UNIT_VALUE (4096)
/* LTC2620 DAC DEFINES *///FIXME: if neeeded
#define LTC2620_DAC_CMD_OFST (20)
#define LTC2620_DAC_CMD_MSK (0x0000000F << LTC2620_DAC_CMD_OFST)