detectors/slsDetectorPackage
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almost done with ctb update, need to do slow adcs, split to moench and ctb

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This commit is contained in:
maliakal_d
2018-11-30 10:39:26 +01:00
parent c19c787904
commit 8f3f9caf2b
110 changed files with 4526 additions and 14397 deletions
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2
slsDetectorGui/src/qDetectorMain.cpp
View File

@ -287,7 +287,7 @@ void qDetectorMain::SetUpDetector(const string fName){
case slsDetectorDefs::PROPIX:
case slsDetectorDefs::MOENCH:
case slsDetectorDefs::JUNGFRAU:
case slsDetectorDefs::JUNGFRAUCTB:
case slsDetectorDefs::CHIPTESTBOARD:
actionLoadTrimbits->setText("Load Settings"); actionSaveTrimbits->setText("Save Settings");
break;
default:

8
slsDetectorGui/src/qDrawPlot.cpp
View File

@ -75,7 +75,7 @@ void qDrawPlot::SetupWidgetWindow(){
case slsDetectorDefs::PROPIX:
case slsDetectorDefs::MOENCH:
case slsDetectorDefs::JUNGFRAU:
case slsDetectorDefs::JUNGFRAUCTB:
case slsDetectorDefs::CHIPTESTBOARD:
originally2D = true;
break;
default:
@ -121,7 +121,7 @@ void qDrawPlot::SetupWidgetWindow(){
nPixelsX = myDet->getTotalNumberOfChannelsInclGapPixels(slsDetectorDefs::X);
nPixelsY = myDet->getTotalNumberOfChannelsInclGapPixels(slsDetectorDefs::Y);
if (detType == slsDetectorDefs::JUNGFRAUCTB) {
if (detType == slsDetectorDefs::CHIPTESTBOARD) {
npixelsy_jctb = (myDet->setTimer(slsDetectorDefs::SAMPLES_JCTB, -1) * 2)/25;// for moench 03
nPixelsX = npixelsx_jctb;
nPixelsY = npixelsy_jctb;
@ -585,7 +585,7 @@ void qDrawPlot::SetScanArgument(int scanArg){
minPixelsY = 0;
nPixelsX = myDet->getTotalNumberOfChannelsInclGapPixels(slsDetectorDefs::X);
nPixelsY = myDet->getTotalNumberOfChannelsInclGapPixels(slsDetectorDefs::Y);
if (detType == slsDetectorDefs::JUNGFRAUCTB) {
if (detType == slsDetectorDefs::CHIPTESTBOARD) {
npixelsy_jctb = (myDet->setTimer(slsDetectorDefs::SAMPLES_JCTB, -1) * 2)/25; // for moench 03
nPixelsX = npixelsx_jctb;
nPixelsY = npixelsy_jctb;
@ -2216,7 +2216,7 @@ void qDrawPlot::toDoublePixelData(double* dest, char* source,int size, int datab
break;
case 16:
if (detType == slsDetectorDefs::JUNGFRAU || detType == slsDetectorDefs::JUNGFRAUCTB) {
if (detType == slsDetectorDefs::JUNGFRAU || detType == slsDetectorDefs::CHIPTESTBOARD) {
// show gain plot
if(gaindest!=NULL) {

2
slsDetectorGui/src/qTabActions.cpp
View File

@ -185,7 +185,7 @@ void qTabActions::SetupWidgetWindow(){
(detType == slsDetectorDefs::AGIPD) ||
(detType == slsDetectorDefs::PROPIX) ||
(detType == slsDetectorDefs::JUNGFRAU) ||
(detType == slsDetectorDefs::JUNGFRAUCTB) ||
(detType == slsDetectorDefs::CHIPTESTBOARD) ||
(detType == slsDetectorDefs::MOENCH)) {
lblName[NumPositions]->setEnabled(false);
btnExpand[NumPositions]->setEnabled(false);

2
slsDetectorGui/src/qTabAdvanced.cpp
View File

@ -125,7 +125,7 @@ void qTabAdvanced::SetupWidgetWindow(){
boxRxr->setEnabled(true);
break;
case slsDetectorDefs::JUNGFRAU:
case slsDetectorDefs::JUNGFRAUCTB:
case slsDetectorDefs::CHIPTESTBOARD:
isEnergy = false;
isAngular = false;
lblIP->setEnabled(true);

2
slsDetectorGui/src/qTabDataOutput.cpp
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@ -897,7 +897,7 @@ void qTabDataOutput::SetupFileFormat(){
case slsDetectorDefs::PROPIX:
case slsDetectorDefs::GOTTHARD:
case slsDetectorDefs::JUNGFRAU:
case slsDetectorDefs::JUNGFRAUCTB:
case slsDetectorDefs::CHIPTESTBOARD:
item[(int)slsDetectorDefs::BINARY]->setEnabled(true);
item[(int)slsDetectorDefs::ASCII]->setEnabled(false);
item[(int)slsDetectorDefs::HDF5]->setEnabled(true);

8
slsDetectorGui/src/qTabDebugging.cpp
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@ -74,7 +74,7 @@ void qTabDebugging::SetupWidgetWindow(){
chkModuleFirmware->setEnabled(false);
break;
case slsDetectorDefs::JUNGFRAU:
case slsDetectorDefs::JUNGFRAUCTB:
case slsDetectorDefs::CHIPTESTBOARD:
case slsDetectorDefs::PROPIX:
case slsDetectorDefs::GOTTHARD:
lblDetector->setText("Module:");
@ -344,7 +344,7 @@ void qTabDebugging::GetInfo(){
case slsDetectorDefs::JUNGFRAU:
case slsDetectorDefs::JUNGFRAUCTB:
case slsDetectorDefs::CHIPTESTBOARD:
//display widget
formLayout->addWidget(new QLabel("Module:"),0,0);
formLayout->addItem(new QSpacerItem(15,20,QSizePolicy::Fixed,QSizePolicy::Fixed),0,1);
@ -474,7 +474,7 @@ void qTabDebugging::SetParameters(QTreeWidgetItem *item){
case slsDetectorDefs::JUNGFRAU:
case slsDetectorDefs::JUNGFRAUCTB:
case slsDetectorDefs::CHIPTESTBOARD:
case slsDetectorDefs::PROPIX:
case slsDetectorDefs::MOENCH:
case slsDetectorDefs::GOTTHARD:
@ -524,7 +524,7 @@ void qTabDebugging::TestDetector(){
break;
case slsDetectorDefs::EIGER: Detector = "Half Module"; break;
case slsDetectorDefs::JUNGFRAU:
case slsDetectorDefs::JUNGFRAUCTB:
case slsDetectorDefs::CHIPTESTBOARD:
case slsDetectorDefs::MOENCH:
case slsDetectorDefs::PROPIX:
case slsDetectorDefs::GOTTHARD: Detector = "Module"; break;

8
slsDetectorGui/src/qTabDeveloper.cpp
View File

@ -148,7 +148,7 @@ void qTabDeveloper::SetupWidgetWindow() {
case slsDetectorDefs::JUNGFRAU:
case slsDetectorDefs::JUNGFRAUCTB:
case slsDetectorDefs::CHIPTESTBOARD:
NUM_DAC_WIDGETS = 8;
NUM_ADC_WIDGETS = 1;
dacNames.push_back("v vb comp:");
@ -472,7 +472,7 @@ slsDetectorDefs::dacIndex qTabDeveloper::getSLSIndex(int index){
}
break;
case slsDetectorDefs::JUNGFRAU:
case slsDetectorDefs::JUNGFRAUCTB:
case slsDetectorDefs::CHIPTESTBOARD:
switch(index){
case 0:
@ -527,7 +527,7 @@ void qTabDeveloper::RefreshAdcs(){
if(value == -1)
spinAdcs[i]->setText(QString("Different values"));
else {
if(detType == slsDetectorDefs::EIGER || detType == slsDetectorDefs::JUNGFRAU || detType == slsDetectorDefs::JUNGFRAUCTB)
if(detType == slsDetectorDefs::EIGER || detType == slsDetectorDefs::JUNGFRAU || detType == slsDetectorDefs::CHIPTESTBOARD)
value/=1000.00;
spinAdcs[i]->setText(QString::number(value,'f',2)+0x00b0+QString("C"));
}
@ -536,7 +536,7 @@ void qTabDeveloper::RefreshAdcs(){
else{
double value = (double)det->getADC(getSLSIndex(i+NUM_DAC_WIDGETS));
if(detType == slsDetectorDefs::EIGER || detType == slsDetectorDefs::JUNGFRAU || detType == slsDetectorDefs::JUNGFRAUCTB)
if(detType == slsDetectorDefs::EIGER || detType == slsDetectorDefs::JUNGFRAU || detType == slsDetectorDefs::CHIPTESTBOARD)
value/=1000.00;
spinAdcs[i]->setText(QString::number(value,'f',2)+0x00b0+QString("C"));
}

12
slsDetectorGui/src/qTabMeasurement.cpp
View File

@ -74,7 +74,7 @@ void qTabMeasurement::SetupWidgetWindow(){
comboDelayUnit->setCurrentIndex((int)unit);
}
//gates
if ((detType == slsDetectorDefs::EIGER) || (detType == slsDetectorDefs::JUNGFRAU) || (detType == slsDetectorDefs::JUNGFRAUCTB)) {
if ((detType == slsDetectorDefs::EIGER) || (detType == slsDetectorDefs::JUNGFRAU) || (detType == slsDetectorDefs::CHIPTESTBOARD)) {
lblNumGates->setEnabled(false);
spinNumGates->setEnabled(false);
} else
@ -154,7 +154,7 @@ void qTabMeasurement::SetupTimingMode(){
case slsDetectorDefs::PROPIX:
case slsDetectorDefs::GOTTHARD:
case slsDetectorDefs::JUNGFRAU:
case slsDetectorDefs::JUNGFRAUCTB:
case slsDetectorDefs::CHIPTESTBOARD:
item[(int)Trigger_Exp_Series]->setEnabled(true);
item[(int)Trigger_Readout]->setEnabled(false);
item[(int)Gated]->setEnabled(false);
@ -292,7 +292,7 @@ void qTabMeasurement::Initialization(){
}
//Number of Gates
if ((detType != slsDetectorDefs::EIGER) && (detType != slsDetectorDefs::JUNGFRAU) && (detType != slsDetectorDefs::JUNGFRAUCTB))
if ((detType != slsDetectorDefs::EIGER) && (detType != slsDetectorDefs::JUNGFRAU) && (detType != slsDetectorDefs::CHIPTESTBOARD))
connect(spinNumGates,SIGNAL(valueChanged(int)), this, SLOT(setNumGates(int)));
//Number of Probes
@ -790,7 +790,7 @@ void qTabMeasurement::Refresh(){
disconnect(spinDelay, SIGNAL(valueChanged(double)), this, SLOT(setDelay()));
disconnect(comboDelayUnit, SIGNAL(currentIndexChanged(int)), this, SLOT(setDelay()));
}
if ((detType != slsDetectorDefs::EIGER) && (detType != slsDetectorDefs::JUNGFRAU) && (detType != slsDetectorDefs::JUNGFRAUCTB))
if ((detType != slsDetectorDefs::EIGER) && (detType != slsDetectorDefs::JUNGFRAU) && (detType != slsDetectorDefs::CHIPTESTBOARD))
disconnect(spinNumGates, SIGNAL(valueChanged(int)), this, SLOT(setNumGates(int)));
#ifdef VERBOSE
@ -824,7 +824,7 @@ void qTabMeasurement::Refresh(){
time = qDefs::getCorrectTime(unit,((double)(myDet->setTimer(slsDetectorDefs::DELAY_AFTER_TRIGGER,-1)*(1E-9))));
//gates
if ((detType != slsDetectorDefs::EIGER) && (detType != slsDetectorDefs::JUNGFRAU) && (detType != slsDetectorDefs::JUNGFRAUCTB) )
if ((detType != slsDetectorDefs::EIGER) && (detType != slsDetectorDefs::JUNGFRAU) && (detType != slsDetectorDefs::CHIPTESTBOARD) )
spinNumGates->setValue((int)myDet->setTimer(slsDetectorDefs::GATES_NUMBER,-1));
@ -862,7 +862,7 @@ void qTabMeasurement::Refresh(){
connect(spinDelay, SIGNAL(valueChanged(double)), this, SLOT(setDelay()));
connect(comboDelayUnit, SIGNAL(currentIndexChanged(int)), this, SLOT(setDelay()));
}
if ((detType != slsDetectorDefs::EIGER) && (detType != slsDetectorDefs::JUNGFRAU) && (detType != slsDetectorDefs::JUNGFRAUCTB))
if ((detType != slsDetectorDefs::EIGER) && (detType != slsDetectorDefs::JUNGFRAU) && (detType != slsDetectorDefs::CHIPTESTBOARD))
connect(spinNumGates, SIGNAL(valueChanged(int)), this, SLOT(setNumGates(int)));
//timing mode - will also check if exptime>acq period and also enableprobes()

4
slsDetectorGui/src/qTabPlot.cpp
View File

@ -183,7 +183,7 @@ void qTabPlot::SetupWidgetWindow(){
isOriginallyOneD = false;
break;
case slsDetectorDefs::JUNGFRAU:
case slsDetectorDefs::JUNGFRAUCTB:
case slsDetectorDefs::CHIPTESTBOARD:
isOriginallyOneD = false;
chkGainPlot->setEnabled(true);
break;
@ -1120,7 +1120,7 @@ void qTabPlot::EnableScanBox(){
if((myDet->getDetectorsType() == slsDetectorDefs::GOTTHARD) ||
(myDet->getDetectorsType() == slsDetectorDefs::PROPIX) ||
(myDet->getDetectorsType() == slsDetectorDefs::JUNGFRAU) ||
(myDet->getDetectorsType() == slsDetectorDefs::JUNGFRAUCTB) ||
(myDet->getDetectorsType() == slsDetectorDefs::CHIPTESTBOARD) ||
(myDet->getDetectorsType() == slsDetectorDefs::MOENCH)){
pagePedestal->setEnabled(true);
pagePedestal_2->setEnabled(true);

10
slsDetectorGui/src/qTabSettings.cpp
View File

@ -38,7 +38,7 @@ void qTabSettings::SetupWidgetWindow(){
detType=myDet->getDetectorsType();
// Settings
if (detType != slsDetectorDefs::JUNGFRAUCTB) {
if (detType != slsDetectorDefs::CHIPTESTBOARD) {
SetupDetectorSettings();
} else
comboSettings->setEnabled(false);
@ -210,7 +210,7 @@ void qTabSettings::SetupDetectorSettings(){
void qTabSettings::Initialization(){
// Settings
if (detType != slsDetectorDefs::JUNGFRAUCTB)
if (detType != slsDetectorDefs::CHIPTESTBOARD)
connect(comboSettings, SIGNAL(currentIndexChanged(int)), this, SLOT(setSettings(int)));
// Number of Modules
connect(spinNumModules, SIGNAL(valueChanged(int)), this, SLOT(SetNumberOfModules(int)));
@ -322,7 +322,7 @@ void qTabSettings::Refresh(){
cout << endl << "**Updating Settings Tab" << endl;
#endif
if (detType != slsDetectorDefs::JUNGFRAUCTB)
if (detType != slsDetectorDefs::CHIPTESTBOARD)
disconnect(comboSettings, SIGNAL(currentIndexChanged(int)), this, SLOT(setSettings(int)));
disconnect(spinNumModules, SIGNAL(valueChanged(int)), this, SLOT(SetNumberOfModules(int)));
disconnect(spinThreshold, SIGNAL(valueChanged(int)), this, SLOT(SetEnergy()));
@ -342,7 +342,7 @@ void qTabSettings::Refresh(){
GetDynamicRange();
// Settings
if (detType != slsDetectorDefs::JUNGFRAUCTB) {
if (detType != slsDetectorDefs::CHIPTESTBOARD) {
#ifdef VERBOSE
cout << "Getting settings" << endl;
#endif
@ -369,7 +369,7 @@ void qTabSettings::Refresh(){
}
}
if (detType != slsDetectorDefs::JUNGFRAUCTB)
if (detType != slsDetectorDefs::CHIPTESTBOARD)
connect(comboSettings, SIGNAL(currentIndexChanged(int)), this, SLOT(setSettings(int)));
connect(spinNumModules, SIGNAL(valueChanged(int)), this, SLOT(SetNumberOfModules(int)));
connect(spinThreshold, SIGNAL(valueChanged(int)), this, SLOT(SetEnergy()));

1
slsDetectorServers/ctbDetectorServer/AD7689.h Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/AD7689.h

1
slsDetectorServers/ctbDetectorServer/AD9257.h Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/AD9257.h

1
slsDetectorServers/ctbDetectorServer/I2C.h Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/I2C.h

1
slsDetectorServers/ctbDetectorServer/INA226.h Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/INA226.h

31
slsDetectorServers/ctbDetectorServer/Makefile Executable file
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@ -0,0 +1,31 @@
CROSS = bfin-uclinux-
CC = $(CROSS)gcc
CFLAGS += -Wall -DCHIPTESTBOARDD -DSTOP_SERVER #-DJCTB -DVERBOSEI #-DVERBOSE
LDLIBS += -lm -lstdc++
PROGS = ctbDetectorServer
DESTDIR ?= bin
INSTMODE = 0777
SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c
OBJS = $(SRC_CLNT:.c=.o)
all: clean versioning $(PROGS)
boot: $(OBJS)
versioning:
@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
$(PROGS): $(OBJS)
# echo $(OBJS)
mkdir -p $(DESTDIR)
$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
mv $(PROGS) $(DESTDIR)
rm *.gdb
clean:
rm -rf $(DESTDIR)/$(PROGS) *.o *.gdb

27
slsDetectorServers/ctbDetectorServer/Makefile.virtual Normal file
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@ -0,0 +1,27 @@
CC = gcc
CFLAGS += -Wall -DCHIPTESTBOARDD -DVIRTUAL -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
LDLIBS += -lm -lstdc++ -pthread
PROGS = ctbDetectorServer_virtual
DESTDIR ?= bin
INSTMODE = 0777
SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c
OBJS = $(SRC_CLNT:.c=.o)
all: clean versioning $(PROGS)
boot: $(OBJS)
versioning:
@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
$(PROGS): $(OBJS)
# echo $(OBJS)
mkdir -p $(DESTDIR)
$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
mv $(PROGS) $(DESTDIR)
clean:
rm -rf $(DESTDIR)/$(PROGS) *.o

538
slsDetectorServers/ctbDetectorServer/RegisterDefs.h Normal file
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@ -0,0 +1,538 @@
#pragma once
/* Definitions for FPGA */
#ifdef JCTB
#define MEM_MAP_SHIFT 11
#else
#define MEM_MAP_SHIFT 1
#endif
/* FPGA Version RO register */
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
#define FPGA_VERSION_BRD_RVSN_OFST (0)
#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
#define FPGA_VERSION_DTCTR_TYP_OFST (24)
#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
#define FPGA_VERSION_DTCTR_TYP_JCTB_VAL ((0x2 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
#define FPGA_VERSION_DTCTR_TYP_CTB_VAL ((0x3 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
/* Fix pattern RO register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
#define FIX_PATT_VAL (0xACDC2014)
/* Status RO register */
#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
#define STATUS_RN_BSY_OFST (0)
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
//#define STATUS_FF_TST_BSY_OFST (2)
//#define STATUS_FF_TST_BSY_MSK (0x00000001 << STATUS_FF_TST_BSY_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4)
#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
#define STATUS_DLY_AFTR_OFST (5)
#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
#define STATUS_EXPSNG_OFST (6)
#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
#define STATUS_CNT_ENBL_OFST (7)
#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
#define STATUS_SM_FF_FLL_OFST (11)
#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
#define STATUS_STPPD_OFST (15)
#define STATUS_STPPD_MSK (0x00000001 << STATUS_STPPD_OFST)
#define STATUS_ALL_FF_EMPTY_OFST (16)
#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
#define STATUS_CYCL_RN_BSY_OFST (17)
#define STATUS_CYCL_RN_BSY_MSK (0x00000001 << STATUS_CYCL_RN_BSY_OFST)
#define STATUS_FRM_RN_BSY_OFST (18)
#define STATUS_FRM_RN_BSY_MSK (0x00000001 << STATUS_FRM_RN_BSY_OFST)
#define STATUS_ADC_DESERON_OFST (19)
#define STATUS_ADC_DESERON_MSK (0x00000001 << STATUS_ADC_DESERON_OFST)
#define STATUS_PLL_RCNFG_BSY_OFST (20)
#define STATUS_PLL_RCNFG_BSY_MSK (0x00000001 << STATUS_PLL_RCNFG_BSY_OFST)
#define STATUS_DT_STRMNG_BSY_OFST (21)
#define STATUS_DT_STRMNG_BSY_MSK (0x00000001 << STATUS_DT_STRMNG_BSY_OFST)
#define STATUS_FRM_PCKR_BSY_OFST (22)
#define STATUS_FRM_PCKR_BSY_MSK (0x00000001 << STATUS_FRM_PCKR_BSY_OFST)
#define STATUS_PLL_PHS_DN_OFST (23)
#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
#define STATUS_PT_CNTRL_STTS_OFF_MSK (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x7FFFF)
/* Look at me RO register TODO */
#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT)
/* System Status RO register */
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK (0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK (0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
#define SYSTEM_STATUS_PLL_A_LCK_MSK (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as PLL_PARAM_REG 0x50 */
//#define PLL_PARAM_REG (0x05 << MEM_MAP_SHIFT)
/* FIFO Data RO register TODO */
#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
//0xCACA#define FIFO_DATA_WRD_OFST (16)
//0xCACA#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
/* FIFO Status RO register TODO */
#define FIFO_STATUS_REG (0x07 << MEM_MAP_SHIFT)
/* FIFO Empty RO register TODO */
#define FIFO_EMPTY_REG (0x08 << MEM_MAP_SHIFT)
/* FIFO Full RO register TODO */
#define FIFO_FULL_REG (0x09 << MEM_MAP_SHIFT)
/* MCB Serial Number RO register */
#define MOD_SERIAL_NUMBER_REG (0x0A << MEM_MAP_SHIFT)
#define MOD_SERIAL_NUMBER_OFST (0)
#define MOD_SERIAL_NUMBER_MSK (0x000000FF << MOD_SERIAL_NUMBER_OFST)
#define MOD_SERIAL_NUMBER_VRSN_OFST (16)
#define MOD_SERIAL_NUMBER_VRSN_MSK (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
/* API Version RO register */
#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DTCTR_TYP_OFST (24)
#define API_VERSION_DTCTR_TYP_MSK (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using CONTROL_CRST. TODO */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
/* Delay Left 64 bit RO register. t = DLY x 50 ns. TODO */
#define DELAY_LEFT_LSB_REG (0x12 << MEM_MAP_SHIFT)
#define DELAY_LEFT_MSB_REG (0x13 << MEM_MAP_SHIFT)
/* Cycles Left 64 bit RO register TODO */
#define CYCLES_LEFT_LSB_REG (0x14 << MEM_MAP_SHIFT)
#define CYCLES_LEFT_MSB_REG (0x15 << MEM_MAP_SHIFT)
/* Frames Left 64 bit RO register TODO */
#define FRAMES_LEFT_LSB_REG (0x16 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_MSB_REG (0x17 << MEM_MAP_SHIFT)
/* Period Left 64 bit RO register. t = T x 50 ns. TODO */
#define PERIOD_LEFT_LSB_REG (0x18 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
/* Exposure Time Left 64 bit RO register */
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT) // Not used in FW
/* Gates Left 64 bit RO register */
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT) // Not used in FW
/* Data In 64 bit RO register TODO */
#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
#define DATA_IN_MSB_REG (0x1F << MEM_MAP_SHIFT)
/* Pattern Out 64 bit RO register */
#define PATTERN_OUT_LSB_REG (0x20 << MEM_MAP_SHIFT)
#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
/* Frames From Start 64 bit RO register TODO */
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT) // Not used in FW
/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame start until reset) TODO */
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
/* Power Status RO register */
#define POWER_STATUS_REG (0x29 << MEM_MAP_SHIFT)
#define POWER_STATUS_ALRT_OFST (27)
#define POWER_STATUS_ALRT_MSK (0x0000001F << POWER_STATUS_ALRT_OFST)
/* DAC Value Out RO register */
//#define DAC_VAL_OUT_REG (0x2A << MEM_MAP_SHIFT)
/* ADC Value RO register */
#define ADC_VAL_REG (0x2B << MEM_MAP_SHIFT)
/* FIFO Digital In Status RO register */
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
/* FIFO Digital In 64 bit RO register */
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
#define FIFO_DIN_MSB_REG (0x3D << MEM_MAP_SHIFT)
/* SPI (Serial Peripheral Interface) DAC, HV RW register */
#define SPI_REG (0x40 << MEM_MAP_SHIFT)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
#define SPI_DAC_SRL_CS_OTPT_OFST (2)
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
#define SPI_HV_SRL_DGTL_OTPT_OFST (8)
#define SPI_HV_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_HV_SRL_DGTL_OTPT_OFST)
#define SPI_HV_SRL_CLK_OTPT_OFST (9)
#define SPI_HV_SRL_CLK_OTPT_MSK (0x00000001 << SPI_HV_SRL_CLK_OTPT_OFST)
#define SPI_HV_SRL_CS_OTPT_OFST (10)
#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
#define SPI_IDLE_MSK (SPI_DAC_SRL_DGTL_OTPT_MSK | SPI_DAC_SRL_CLK_OTPT_MSK | SPI_DAC_SRL_CS_OTPT_MSK | SPI_HV_SRL_DGTL_OTPT_MSK | SPI_HV_SRL_CLK_OTPT_MSK | SPI_HV_SRL_CS_OTPT_MSK)
/* ADC SPI (Serial Peripheral Interface) RW register */
#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
#define ADC_SPI_SLOW_SRL_DT_OTPT_OFST (8)
#define ADC_SPI_SLOW_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SLOW_SRL_DT_OTPT_OFST)
#define ADC_SPI_SLOW_SRL_CLK_OTPT_OFST (9)
#define ADC_SPI_SLOW_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SLOW_SRL_CS_OTPT_OFST (10)
#define ADC_SPI_SLOW_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SLOW_SRL_CS_OTPT_OFST)
#define ADC_SPI_IDLE_MSK (ADC_SPI_SRL_CLK_OTPT_MSK | ADC_SPI_SRL_DT_OTPT_MSK | ADC_SPI_SRL_CS_OTPT_MSK | ADC_SPI_SLOW_SRL_DT_OTPT_MSK | ADC_SPI_SLOW_SRL_CLK_OTPT_MSK | ADC_SPI_SLOW_SRL_CS_OTPT_MSK)
/* ADC Offset RW register */
#define ADC_OFFSET_REG (0x42 << MEM_MAP_SHIFT)
#define ADC_OFFSET_ADC_PPLN_OFST (0)
#define ADC_OFFSET_ADC_PPLN_MSK (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
#define ADC_OFFSET_DBT_PPLN_OFST (16)
#define ADC_OFFSET_DBT_PPLN_MSK (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
/* ADC Port Invert RW register */
#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
#define ADC_PORT_INVERT_0_INPT_OFST (0)
#define ADC_PORT_INVERT_0_INPT_MSK (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
#define ADC_PORT_INVERT_1_INPT_OFST (8)
#define ADC_PORT_INVERT_1_INPT_MSK (0x000000FF << ADC_PORT_INVERT_1_INPT_OFST)
#define ADC_PORT_INVERT_2_INPT_OFST (16)
#define ADC_PORT_INVERT_2_INPT_MSK (0x000000FF << ADC_PORT_INVERT_2_INPT_OFST)
#define ADC_PORT_INVERT_3_INPT_OFST (24)
#define ADC_PORT_INVERT_3_INPT_MSK (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
/* Dummy RW register */
#define DUMMY_REG (0x44 << MEM_MAP_SHIFT)
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
#define DUMMY_ALL_FIFO_RD_STRBE_OFST (8)
#define DUMMY_ALL_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_ALL_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
/* Receiver IP Address RW register */
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
/* UDP Port RW register */
#define UDP_PORT_REG (0x46 << MEM_MAP_SHIFT)
#define UDP_PORT_RX_OFST (0)
#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
#define UDP_PORT_TX_OFST (16)
#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
/* Receiver Mac Address 64 bit RW register */
#define RX_MAC_LSB_REG (0x47 << MEM_MAP_SHIFT)
#define RX_MAC_MSB_REG (0x48 << MEM_MAP_SHIFT)
#define RX_MAC_LSB_OFST (0)
#define RX_MAC_LSB_MSK (0xFFFFFFFF << RX_MAC_LSB_OFST)
#define RX_MAC_MSB_OFST (0)
#define RX_MAC_MSB_MSK (0x0000FFFF << RX_MAC_MSB_OFST)
/* Detector/ Transmitter Mac Address 64 bit RW register */
#define TX_MAC_LSB_REG (0x49 << MEM_MAP_SHIFT)
#define TX_MAC_MSB_REG (0x4A << MEM_MAP_SHIFT)
#define TX_MAC_LSB_OFST (0)
#define TX_MAC_LSB_MSK (0xFFFFFFFF << TX_MAC_LSB_OFST)
#define TX_MAC_MSB_OFST (0)
#define TX_MAC_MSB_MSK (0x0000FFFF << TX_MAC_MSB_OFST)
/* Detector/ Transmitter IP Address RW register */
#define TX_IP_REG (0x4B << MEM_MAP_SHIFT)
/* Detector/ Transmitter IP Checksum RW register */
#define TX_IP_CHECKSUM_REG (0x4C << MEM_MAP_SHIFT)
#define TX_IP_CHECKSUM_OFST (0)
#define TX_IP_CHECKSUM_MSK (0x0000FFFF << TX_IP_CHECKSUM_OFST)
/* Configuration RW register */
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
#define CONFIG_LED_DSBL_OFST (0)
#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
#define CONFIG_DSBL_ANLG_OTPT_OFST (8)
#define CONFIG_DSBL_ANLG_OTPT_MSK (0x00000001 << CONFIG_DSBL_ANLG_OTPT_OFST)
#define CONFIG_ENBLE_DGTL_OTPT_OFST (9)
#define CONFIG_ENBLE_DGTL_OTPT_MSK (0x00000001 << CONFIG_ENBLE_DGTL_OTPT_OFST)
#define CONFIG_GB10_SND_UDP_OFST (12)
#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
/* External Signal RW register */
#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_AUTO_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_VAL ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/* Control RW register */
#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
//#define CONTROL_STRT_FF_TST_OFST (2)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
//#define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
//#define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_RDT_OFST (5)
//#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_EXPSR_OFST (7)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STRT_TRN_OFST (8)
//#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_TRN_OFST (9)
//#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
#define CONTROL_MMRY_RST_OFST (12)
#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
//#define CONTROL_PLL_RCNFG_WR_OFST (13)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 << CONTROL_PLL_RCNFG_WR_OFST)
#define CONTROL_SND_10GB_PCKT_OFST (14)
#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
/* Reconfiguratble PLL Paramater RW register */
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
/* Reconfiguratble PLL Control RW regiser */
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
#define PLL_CNTRL_PLL_RST_MSK (0x00000001 << PLL_CNTRL_PLL_RST_OFST)
#define PLL_CNTRL_ADDR_OFST (16)
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
/* Pattern Control RW register */
#define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)
#define PATTERN_CNTRL_WR_OFST (0)
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
#define PATTERN_CNTRL_RD_OFST (1)
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
#define PATTERN_CNTRL_ADDR_OFST (16)
#define PATTERN_CNTRL_ADDR_MSK (0x0000FFFF << PATTERN_CNTRL_ADDR_OFST)
/* Pattern Limit RW regiser */
#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
/* Pattern Loop 0 Address RW regiser */
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_0_ADDR_STP_OFST)
/* Pattern Loop 0 Iteration RW regiser */
#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
/* Pattern Loop 1 Address RW regiser */
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_1_ADDR_STP_OFST)
/* Pattern Loop 1 Iteration RW regiser */
#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
/* Pattern Loop 2 Address RW regiser */
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_2_ADDR_STP_OFST)
/* Pattern Loop 2 Iteration RW regiser */
#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
/* Pattern Wait 0 RW regiser */
#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_0_ADDR_OFST)
//FIXME: is mask 3FF
/* Pattern Wait 1 RW regiser */
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_1_ADDR_OFST)
/* Pattern Wait 2 RW regiser */
#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_2_ADDR_OFST)
/* Samples RW register */
#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
/** Power RW register */
#define POWER_REG (0x5E << MEM_MAP_SHIFT)
#define POWER_ENBL_VLTG_RGLTR_OFST (16)
#define POWER_ENBL_VLTG_RGLTR_MSK (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
#define POWER_HV_SLCT_OFST (31)
#define POWER_HV_SLCT_MSK (0x00000001 << POWER_HV_SLCT_OFST)
/* Number of Words RW register TODO */
#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
/* Delay 64 bit RW register. t = DLY x 50 ns. */
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
/* Cycles 64 bit RW register */
#define CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
#define CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
/* Frames 64 bit RW register */
#define FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
#define FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
#define PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_MSB_REG (0x69 << MEM_MAP_SHIFT) // Not used in FW
/* Gates 64 bit RW register */
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) // Not used in FW
/* Pattern IO Control 64 bit RW regiser
* Each bit configured as output(1)/ input(0) */
#define PATTERN_IO_CNTRL_LSB_REG (0x6C << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_MSB_REG (0x6D << MEM_MAP_SHIFT)
/* Pattern IO Clock Control 64 bit RW regiser
* When bit n enabled (1), clocked output for DIO[n] (T run clock)
* When bit n disabled (0), Dio[n] driven by its pattern output */
#define PATTERN_IO_CLK_CNTRL_LSB_REG (0x6E << MEM_MAP_SHIFT)
#define PATTERN_IO_CLK_CNTRL_MSB_REG (0x6F << MEM_MAP_SHIFT)
/* Pattern In 64 bit RW register */
#define PATTERN_IN_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define PATTERN_IN_MSB_REG (0x71 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 0 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x72 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x73 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 1 64 bit RW register. t = PWT2 x T run clock */
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x74 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x75 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 2 64 bit RW register. t = PWT3 x T run clock */
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
/* ADC Disable RW register TODO */
#define ADC_DISABLE_REG (0x78 << MEM_MAP_SHIFT)
/* DAC Value RW register TODO */
//#define DAC_VALUE_REG (0x79 << MEM_MAP_SHIFT)
/* DAC Number RW register TODO */
//#define DAC_NUMBER_REG (0x7A << MEM_MAP_SHIFT)
/* Digital Bit External Trigger RW register */
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
#define DBIT_EXT_TRG_SRC_OFST (0)
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
#define DBIT_EXT_TRG_OPRTN_MD_OFST (16)
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
/* Pin Delay 0 RW register */
#define PIN_DELAY_0_REG (0x7C << MEM_MAP_SHIFT)
#define PIN_DELAY_0_OTPT_STTNG_OFST (0) //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define PIN_DELAY_0_OTPT_STTNG_MSK (0x0000001F << PIN_DELAY_0_OFST)
#define PIN_DELAY_0_OTPT_TRGGR_OFST (31)
#define PIN_DELAY_0_OTPT_TRGGR_MSK (0x00000001 << PIN_DELAY_0_OFST)
#define PIN_DELAY_0_OTPT_TRGGR_LD_VAL (1)
#define PIN_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
/* Pin Delay 1 RW register
* Each bit configured as enable for dynamic output delay configuration */
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT)
/** I2C Control register */
#define I2C_TRANSFER_COMMAND_FIFO_REG (0x100 << MEM_MAP_SHIFT)
#define I2C_CONTROL_REG (0x102 << MEM_MAP_SHIFT)
#define I2C_RX_DATA_FIFO_LEVEL_REG (0x107 << MEM_MAP_SHIFT)
#define I2C_SCL_LOW_COUNT_REG (0x108 << MEM_MAP_SHIFT)
#define I2C_SCL_HIGH_COUNT_REG (0x109 << MEM_MAP_SHIFT)
#define I2C_SDA_HOLD_REG (0x10A << MEM_MAP_SHIFT)
//fixme: upto 0x10f

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slsDetectorServers/ctbDetectorServer/ansi.h Symbolic link
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../../slsSupportLib/include/ansi.h

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slsDetectorServers/ctbDetectorServer/blackfin.h Symbolic link
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slsDetectorServers/ctbDetectorServer/commonServerFunctions.h Symbolic link
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slsDetectorServers/ctbDetectorServer/communication_funcs.c Symbolic link
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slsDetectorServers/ctbDetectorServer/communication_funcs.h Symbolic link
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../slsDetectorServer/communication_funcs.h

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slsDetectorServers/ctbDetectorServer/gitInfoCtb.h Normal file
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@ -0,0 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "91dd176a0fb314f583ca6e29140053f1eb742896"
#define GITAUTH "Dhanya_Thattil"
#define GITREV 0x4166
#define GITDATE 0x20181108
#define GITBRANCH "refactor"

0
slsDetectorServers/jctbDetectorServer/gitInfoMoenchTmp.h → slsDetectorServers/ctbDetectorServer/gitInfoCtbTmp.h
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1
slsDetectorServers/ctbDetectorServer/logger.h Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/logger.h

1
slsDetectorServers/ctbDetectorServer/programfpga.h Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/programfpga.h

2353
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c Normal file
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1
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.h Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/slsDetectorFunctionList.h

1
slsDetectorServers/ctbDetectorServer/slsDetectorServer.c Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/slsDetectorServer.c

187
slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h Normal file
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@ -0,0 +1,187 @@
#pragma once
#include "sls_detector_defs.h"
#include "RegisterDefs.h"
#define GOODBYE (-200)
#define MIN_REQRD_VRSN_T_RD_API 0x180314
#define REQRD_FRMWR_VRSN 0x180314
#define PROGRAMMING_MODE (0x2)
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
#ifdef JCTB
#define DETNAME = "Jungfrau Chip Test Board";
#else
#define DETNAME = "Chip Test Board";
#endif
/* Struct Definitions */
typedef struct ip_header_struct {
uint16_t ip_len;
uint8_t ip_tos;
uint8_t ip_ihl:4 ,ip_ver:4;
uint16_t ip_offset:13,ip_flag:3;
uint16_t ip_ident;
uint16_t ip_chksum;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint32_t ip_sourceip;
uint32_t ip_destip;
} ip_header;
/* Enums */
enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
enum ADCINDEX {V_PWR_IO, V_PWR_A, V_PWR_B, V_PWR_C, V_PWR_D, I_PWR_IO, I_PWR_A, I_PWR_B, I_PWR_C, I_PWR_D};
enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
D10, D11, D12, D13, D14, D15, D16, D17,
D_PWR_D, D_PWR_CHIP, D_PWR_C, D_PWR_B, D_PWR_A, D_PWR_IO};
/* Hardware Definitions */
#define NCHAN (36)
#define NCHAN_ANALOG (32)
#define NCHAN_DIGITAL (4)
#define NCHIP (1)
#define NDAC (24)
#define NPWR (6)
#define NDAC_ONLY (NDAC - NPWR)
//#define N_DAC (24)
//#define N_PWR (5)
//#define NADC (9)
//#define DAC_CMD_OFF 20
#define DYNAMIC_RANGE (16)
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
#define CLK_FREQ (156.25) /* MHz */
#define I2C_POWER_VIO_DEVICE_ID (0x40)
#define I2C_POWER_VA_DEVICE_ID (0x41)
#define I2C_POWER_VB_DEVICE_ID (0x42)
#define I2C_POWER_VC_DEVICE_ID (0x43)
#define I2C_POWER_VD_DEVICE_ID (0x44)
#define I2C_SHUNT_RESISTER_OHMS (0.005)
/** Default Parameters */
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define DEFAULT_NUM_SAMPLES (1)
#define DEFAULT_NUM_FRAMES (100 * 1000 * 1000)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_PERIOD (1 * 1000 * 1000) //ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_VLIMIT (-100)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
/* Defines in the Firmware */
#define WAIT_TME_US_FR_LK_AT_ME_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
#define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (500 * 1000)
#define SLOW_ADC_START_INDEX (1000)
#define SLOW_ADC_END_INDEX (1008)
#define MAX_DAC_VOLTAGE_VALUE (2500)
#define MAX_DAC_UNIT_VALUE (4096)
#define DAC_MAX_VOLTAGE_MV (2500)
#define VCHIP_MAX_MV (2700)
#define VCHIP_MIN_MV (1700)
#define POWER_RGLTR_MAX (2500)
#define POWER_RGLTR_MIN (600)
#define VCHIP_POWER_INCRMNT (200)
#define IP_PACKETSIZE (0x2032)
#ifndef JCTB
#define ADC_PORT_INVERT_VAL (0x453b2593)
#else
#define ADC_PORT_INVERT_VAL (0x453b2593)
#endif
#define MAXIMUM_ADC_CLK (40)
#define PLL_VCO_FREQ_MHZ (400)
/* MSB & LSB DEFINES */
#define MSB_OF_64_BIT_REG_OFST (32)
#define LSB_OF_64_BIT_REG_OFST (0)
#define BIT_32_MSK (0xFFFFFFFF)
/* LTC2620 DAC DEFINES */
#define LTC2620_DAC_CMD_OFST (20)
#define LTC2620_DAC_CMD_MSK (0x0000000F << LTC2620_DAC_CMD_OFST)
#define LTC2620_DAC_ADDR_OFST (16)
#define LTC2620_DAC_ADDR_MSK (0x0000000F << LTC2620_DAC_ADDR_OFST)
#define LTC2620_DAC_DATA_OFST (4)
#define LTC2620_DAC_DATA_MSK (0x00000FFF << LTC2620_DAC_DATA_OFST)
#define LTC2620_DAC_CMD_WRITE (0x00000000 << LTC2620_DAC_CMD_OFST)
#define LTC2620_DAC_CMD_SET (0x00000003 << LTC2620_DAC_CMD_OFST)
#define LTC2620_DAC_CMD_POWER_DOWN (0x00000004 << LTC2620_DAC_CMD_OFST)
#define LTC2620_DAC_NUMBITS (24)
/* MAX1932 HV DEFINES */
#define MAX1932_HV_NUMBITS (8)
#define MAX1932_HV_DATA_OFST (0)
#define MAX1932_HV_DATA_MSK (0x000000FF << MAX1932_HV_DATA_OFST)
/** PLL Reconfiguration Registers */
//https://www.altera.com/documentation/mcn1424769382940.html
#define PLL_MODE_REG (0x00)
#define PLL_MODE_WT_RQUST_VAL (0)
#define PLL_MODE_PLLNG_MD_VAL (1)
#define PLL_STATUS_REG (0x01)
#define PLL_START_REG (0x02)
#define PLL_N_COUNTER_REG (0x03)
#define PLL_M_COUNTER_REG (0x04)
#define PLL_C_COUNTER_REG (0x05)
#define PLL_C_COUNTER_LW_CNT_OFST (0)
#define PLL_C_COUNTER_LW_CNT_MSK (0x000000FF << PLL_C_COUNTER_LW_CNT_OFST)
#define PLL_C_COUNTER_HGH_CNT_OFST (8)
#define PLL_C_COUNTER_HGH_CNT_MSK (0x000000FF << PLL_C_COUNTER_HGH_CNT_OFST)
/* total_div = lw_cnt + hgh_cnt */
#define PLL_C_COUNTER_BYPSS_ENBL_OFST (16)
#define PLL_C_COUNTER_BYPSS_ENBL_MSK (0x00000001 << PLL_C_COUNTER_BYPSS_ENBL_OFST)
/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is bypassed) */
#define PLL_C_COUNTER_ODD_DVSN_OFST (17)
#define PLL_C_COUNTER_ODD_DVSN_MSK (0x00000001 << PLL_C_COUNTER_ODD_DVSN_OFST)
/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle = (hgh_cnt - 0.5) / total_div */
#define PLL_C_COUNTER_SLCT_OFST (18)
#define PLL_C_COUNTER_SLCT_MSK (0x0000001F << PLL_C_COUNTER_SLCT_OFST)
#define PLL_PHASE_SHIFT_REG (0x06)
#define PLL_SHIFT_NUM_SHIFTS_OFST (0)
#define PLL_SHIFT_NUM_SHIFTS_MSK (0x0000FFFF << PLL_SHIFT_NUM_SHIFTS_OFST)
#define PLL_SHIFT_CNT_SELECT_OFST (16)
#define PLL_SHIFT_CNT_SELECT_MSK (0x0000001F << PLL_SHIFT_CNT_SELECT_OFST)
#define PLL_SHIFT_CNT_SLCT_C0_VAL ((0x0 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C1_VAL ((0x1 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C2_VAL ((0x2 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C3_VAL ((0x3 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C4_VAL ((0x4 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C5_VAL ((0x5 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C6_VAL ((0x6 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C7_VAL ((0x7 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C8_VAL ((0x8 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C9_VAL ((0x9 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C10_VAL ((0x10 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C11_VAL ((0x11 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C12_VAL ((0x12 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C13_VAL ((0x13 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C14_VAL ((0x14 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C15_VAL ((0x15 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C16_VAL ((0x16 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_CNT_SLCT_C17_VAL ((0x17 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
#define PLL_SHIFT_UP_DOWN_OFST (21)
#define PLL_SHIFT_UP_DOWN_MSK (0x00000001 << PLL_SHIFT_UP_DOWN_OFST)
#define PLL_SHIFT_UP_DOWN_NEG_VAL ((0x0 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
#define PLL_SHIFT_UP_DOWN_POS_VAL ((0x1 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
#define PLL_K_COUNTER_REG (0x07)
#define PLL_BANDWIDTH_REG (0x08)
#define PLL_CHARGEPUMP_REG (0x09)
#define PLL_VCO_DIV_REG (0x1c)
#define PLL_MIF_REG (0x1f)

1
slsDetectorServers/ctbDetectorServer/slsDetectorServer_funcs.c Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/slsDetectorServer_funcs.c

1
slsDetectorServers/ctbDetectorServer/slsDetectorServer_funcs.h Symbolic link
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@ -0,0 +1 @@
../slsDetectorServer/slsDetectorServer_funcs.h

1
slsDetectorServers/ctbDetectorServer/sls_detector_defs.h Symbolic link
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@ -0,0 +1 @@
../../slsSupportLib/include/sls_detector_defs.h

1
slsDetectorServers/ctbDetectorServer/sls_detector_funcs.h Symbolic link
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@ -0,0 +1 @@
../../slsSupportLib/include/sls_detector_funcs.h

7
slsDetectorServers/ctbDetectorServer/updateAPIVersion.sh Executable file
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@ -0,0 +1,7 @@
SRCFILE=gitInfoCtb.h
DSTFILE=versionAPI.h
SRCPATTERN=GITDATE
DSTPATTERN=APICTB
awk -v a="$SRCFILE" -v b="$DSTFILE" -v c="$SRCPATTERN" -v d="$DSTPATTERN" 'FNR==NR&&$2==c{x=$3} NR!=FNR{if($2==d){$3="0x"substr(x,5)}print > b}' $SRCFILE $DSTFILE

12
slsDetectorServers/jctbDetectorServer/updateGitVersion.sh → slsDetectorServers/ctbDetectorServer/updateGitVersion.sh
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@ -1,8 +1,8 @@
SERVER=jctbDetectorServer
MAINDIR=slsDetectorsPackage
SPECDIR=slsDetectorSoftware/$SERVER
TMPFILE=gitInfoMoenchTmp.h
INCLFILE=gitInfoMoench.h
SERVER=ctbDetectorServer
MAINDIR=slsDetectorPackage
SPECDIR=slsDetectorServers/$SERVER
TMPFILE=gitInfoCtbTmp.h
INCLFILE=gitInfoCtb.h
#evaluate the variables
@ -12,7 +12,7 @@ source $EVALFILE
#get modified date
#RDATE1='git log --pretty=format:"%ci" -1'
RDATE1="find . -type f -exec stat --format '%Y :%y %n' '{}' \; | sort -nr | cut -d: -f2- | egrep -v 'gitInfo|.git|updateGitVersion|.o' | head -n 1"
RDATE1="find ../slsDetectorServer . -type f -exec stat --format '%Y :%y %n' '{}' \; | sort -nr | cut -d: -f2- | egrep -v 'gitInfo|bin|.git|updateGitVersion|.o' | head -n 1"
RDATE=`eval $RDATE1`
NEWDATE=$(sed "s/-//g" <<< $RDATE | awk '{print $1;}')
NEWDATE=${NEWDATE/#/0x}

1
slsDetectorServers/ctbDetectorServer/versionAPI.h Symbolic link
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@ -0,0 +1 @@
../../slsSupportLib/include/versionAPI.h

13
slsDetectorServers/eigerDetectorServer/slsDetectorFunctionList.c
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@ -435,7 +435,7 @@ void setupDetector() {
setReadOutFlags(DEFAULT_READOUT_MODE);
setReadOutFlags(DEFAULT_READOUT_STOREINRAM_MODE);
setReadOutFlags(DEFAULT_READOUT_OVERFLOW32_MODE);
setSpeed(DEFAULT_CLK_SPEED);//clk_devider,half speed
setSpeed(CLOCK_DIVIDER, DEFAULT_CLK_SPEED);//clk_devider,half speed
setIODelay(DEFAULT_IO_DELAY);
setTiming(DEFAULT_TIMING_MODE);
//SetPhotonEnergyCalibrationParameters(-5.8381e-5,1.838515,5.09948e-7,-4.32390e-11,1.32527e-15);
@ -509,7 +509,9 @@ int setDynamicRange(int dr) {
/* parameters - readout */
enum speedVariable setSpeed(int val) {
void setSpeed(enum speedVariable ind, int val) {
if (ind != CLOCK_DIVIDER)
return;
if (val != -1) {
FILE_LOG(logDEBUG1, ("Setting Read out Speed: %d\n", val));
@ -518,7 +520,12 @@ enum speedVariable setSpeed(int val) {
#endif
eiger_readoutspeed = val;
}
return eiger_readoutspeed;
}
int getSpeed(enum speedVariable ind) {
if (ind != CLOCK_DIVIDER)
return -1;
return eiger_readoutspeed;
}

3
slsDetectorServers/eigerDetectorServer/slsDetectorServer_defs.h
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@ -74,6 +74,9 @@ enum {E_PARALLEL, E_NON_PARALLEL, E_SAFE};
#define DEFAULT_TEST_MODE (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define MAX_DAC_VOLTAGE_VALUE (2048)
#define MAX_DAC_UNIT_VALUE (4096)
#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS (0x1FFFFFFF) /** 29 bit register for max subframe exposure value */

1
slsDetectorServers/gotthardDetectorServer/RegisterDefs.h
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@ -116,7 +116,6 @@
#define ADC_SYNC_ENET_DELAY_MSK (0x000000FF << ADC_SYNC_ENET_DELAY_OFST)
#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL ((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_DELAY_ROI_VAL ((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
//FIXME: try with just 0x8 and 0x1.. it is anded with 0000 in firmware anyway
/** Time From Start register */
//#define MU_TIME_REG (0x1a << MEM_MAP_SHIFT)

1
slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c
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@ -783,7 +783,6 @@ ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret) {
int i = 0;
for (i = 0; i < n; ++i) {
FILE_LOG(logINFO, ("\t(%d, %d)\n", arg[i].xmin, arg[i].xmax));
}
}
// only one ROI allowed per module

3
slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h
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@ -51,6 +51,9 @@ enum DACINDEX {VREF_DS, VCASCN_PB, VCASCP_PB, VOUT_CM, VCASC_OUT, VIN
#define DEFAULT_PHASE_SHIFT (120)
#define DEFAULT_TX_UDP_PORT (0xE185)
#define MAX_DAC_VOLTAGE_VALUE (2500)
#define MAX_DAC_UNIT_VALUE (4096)
/* LTC2620 DAC DEFINES *///FIXME: if neeeded
#define LTC2620_DAC_CMD_OFST (20)
#define LTC2620_DAC_CMD_MSK (0x0000000F << LTC2620_DAC_CMD_OFST)

141
slsDetectorServers/jctbDetectorServer/AD9257.h
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@ -1,141 +0,0 @@
#ifndef AD9257_H
#define AD9257_H
#include "ansi.h"
#include "commonServerFunctions.h"
#include <stdio.h>
/* AD9257 ADC DEFINES */
#define AD9257_ADC_NUMBITS (24)
#define AD9257_DEV_IND_2_REG (0x04)
#define AD9257_CHAN_H_OFST (0)
#define AD9257_CHAN_H_MSK (0x00000001 << AD9257_CHAN_H_OFST)
#define AD9257_CHAN_G_OFST (1)
#define AD9257_CHAN_G_MSK (0x00000001 << AD9257_CHAN_G_OFST)
#define AD9257_CHAN_F_OFST (2)
#define AD9257_CHAN_F_MSK (0x00000001 << AD9257_CHAN_F_OFST)
#define AD9257_CHAN_E_OFST (3)
#define AD9257_CHAN_E_MSK (0x00000001 << AD9257_CHAN_E_OFST)
#define AD9257_DEV_IND_1_REG (0x05)
#define AD9257_CHAN_D_OFST (0)
#define AD9257_CHAN_D_MSK (0x00000001 << AD9257_CHAN_D_OFST)
#define AD9257_CHAN_C_OFST (1)
#define AD9257_CHAN_C_MSK (0x00000001 << AD9257_CHAN_C_OFST)
#define AD9257_CHAN_B_OFST (2)
#define AD9257_CHAN_B_MSK (0x00000001 << AD9257_CHAN_B_OFST)
#define AD9257_CHAN_A_OFST (3)
#define AD9257_CHAN_A_MSK (0x00000001 << AD9257_CHAN_A_OFST)
#define AD9257_CLK_CH_DCO_OFST (4)
#define AD9257_CLK_CH_DCO_MSK (0x00000001 << AD9257_CLK_CH_DCO_OFST)
#define AD9257_CLK_CH_IFCO_OFST (5)
#define AD9257_CLK_CH_IFCO_MSK (0x00000001 << AD9257_CLK_CH_IFCO_OFST)
#define AD9257_POWER_MODE_REG (0x08)
#define AD9257_POWER_INTERNAL_OFST (0)
#define AD9257_POWER_INTERNAL_MSK (0x00000003 << AD9257_POWER_INTERNAL_OFST)
#define AD9257_INT_RESET_VAL (0x3)
#define AD9257_INT_CHIP_RUN_VAL (0x0)
#define AD9257_POWER_EXTERNAL_OFST (5)
#define AD9257_POWER_EXTERNAL_MSK (0x00000001 << AD9257_POWER_EXTERNAL_OFST)
#define AD9257_EXT_FULL_POWER_VAL (0x0)
#define AD9257_EXT_STANDBY_VAL (0x1)
#define AD9257_OUT_MODE_REG (0x14)
#define AD9257_OUT_FORMAT_OFST (0)
#define AD9257_OUT_FORMAT_MSK (0x00000001 << AD9257_OUT_FORMAT_OFST)
#define AD9257_OUT_BINARY_OFST_VAL (0)
#define AD9257_OUT_TWOS_COMPL_VAL (1)
#define AD9257_OUT_LVDS_OPT_OFST (6)
#define AD9257_OUT_LVDS_OPT_MSK (0x00000001 << AD9257_OUT_LVDS_OPT_OFST)
#define AD9257_OUT_LVDS_ANSI_VAL (0)
#define AD9257_OUT_LVDS_IEEE_VAL (1)
#define AD9257_OUT_PHASE_REG (0x16)
#define AD9257_OUT_CLK_OFST (0)
#define AD9257_OUT_CLK_MSK (0x0000000F << AD9257_OUT_CLK_OFST)
#define AD9257_OUT_CLK_60_VAL (0x1)
#define AD9257_IN_CLK_OFST (4)
#define AD9257_IN_CLK_MSK (0x00000007 << AD9257_IN_CLK_OFST)
#define AD9257_IN_CLK_0_VAL (0x0)
#define AD9257_VREF_REG (0x18)
#define AD9257_VREF_OFST (0)
#define AD9257_VREF_MSK (0x00000003 << AD9257_VREF_OFST)
#define AD9257_VREF_1_33_VAL (0x2)
#define AD9257_TEST_MODE_REG (0x0D)
#define AD9257_OUT_TEST_OFST (0)
#define AD9257_OUT_TEST_MSK (0x0000000F << AD9257_OUT_TEST_OFST)
#define AD9257_NONE_VAL (0x0)
#define AD9257_MIXED_BIT_FREQ_VAL (0xC)
#define AD9257_TEST_RESET_SHORT_GEN (4)
#define AD9257_TEST_RESET_LONG_GEN (5)
#define AD9257_USER_IN_MODE_OFST (6)
#define AD9257_USER_IN_MODE_MSK (0x00000003 << AD9257_USER_IN_MODE_OFST)
void setAdc(int addr, int val) {
u_int32_t codata;
codata = val + (addr << 8);
printf(" Setting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr);
serializeToSPI(ADC_SPI_REG, codata, ADC_SERIAL_CS_OUT_MSK, AD9257_ADC_NUMBITS,
ADC_SERIAL_CLK_OUT_MSK, ADC_SERIAL_DATA_OUT_MSK, ADC_SERIAL_DATA_OUT_OFST);
}
void prepareADC(){
printf("\n\nPreparing ADC ... \n");
//power mode reset
printf("power mode reset:\n");
setAdc(AD9257_POWER_MODE_REG,
(AD9257_INT_RESET_VAL << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK);
//power mode chip run
printf("power mode chip run:\n");
setAdc(AD9257_POWER_MODE_REG,
(AD9257_INT_CHIP_RUN_VAL << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK);
//output clock phase
printf("output clock phase:\n");
setAdc(AD9257_OUT_PHASE_REG,
(AD9257_OUT_CLK_60_VAL << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK);
// lvds-iee reduced , binary offset
printf("lvds-iee reduced, binary offset:\n");
setAdc(AD9257_OUT_MODE_REG,
(AD9257_OUT_LVDS_IEEE_VAL << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK);
// all devices on chip to receive next command
printf("all devices on chip to receive next command:\n");
setAdc(AD9257_DEV_IND_2_REG,
AD9257_CHAN_H_MSK | AD9257_CHAN_G_MSK | AD9257_CHAN_F_MSK | AD9257_CHAN_E_MSK);
setAdc(AD9257_DEV_IND_1_REG,
AD9257_CHAN_D_MSK | AD9257_CHAN_C_MSK | AD9257_CHAN_B_MSK | AD9257_CHAN_A_MSK |
AD9257_CLK_CH_DCO_MSK | AD9257_CLK_CH_IFCO_MSK);
// vref 1.33
printf("vref 1.33:\n");
setAdc(AD9257_VREF_REG,
(AD9257_VREF_1_33_VAL << AD9257_VREF_OFST) & AD9257_VREF_MSK);
// no test mode
printf("no test mode:\n");
setAdc(AD9257_TEST_MODE_REG,
(AD9257_NONE_VAL << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK);
#ifdef TESTADC
printf("***************************************** *******\n");
printf("******* PUTTING ADC IN TEST MODE!!!!!!!!! *******\n");
printf("***************************************** *******\n");
// mixed bit frequency test mode
printf("mixed bit frequency test mode:\n");
setAdc(AD9257_TEST_MODE_REG,
(AD9257_MIXED_BIT_FREQ_VAL << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK);
#endif
}
#endif //AD9257_H

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slsDetectorServers/jctbDetectorServer/Makefile
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@ -1,59 +0,0 @@
# $Id: Makefile,v 1.1.1.1 2006/02/04 03:35:01 freza Exp $
# first compile
# make cris-axis-linux-gnu
CROSS = bfin-uclinux-
CC = $(CROSS)gcc
CFLAGS += -Wall -DMOENCHD -DMCB_FUNCS -DDACS_INT -DDEBUG -DV1 -DCTB -DOLDVERSION #-DVERBOSE #-DVERYVERBOSE #-DVIRTUAL #-DDACS_INT_CSERVER
PROGS= jctbDetectorServer
INSTDIR= /tftpboot
INSTMODE= 0777
BINS = testlib_sharedlibc
SRCS = server.c server_funcs.c communication_funcs.c firmware_funcs.c slow_adc.c blackfin.c
#mcb_funcs.c sharedmemory.c
OBJS = $(SRCS:%.c=%.o)
all: clean versioning $(PROGS)
test: clean jungfrauADCTEst
boot: $(OBJS)
versioning:
@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
jctbDetectorServerNew: $(OBJS)
echo $(OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@)
jctbDetectorServer: $(OBJS)
echo $(OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@) -DOLDVERSION
jungfrauADCTEst: $(OBJS)
echo $(OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@) -DTESTADC
install: $(PROGS)
$(INSTALL) -d $(INSTDIR)
$(INSTALL) -m $(INSTMODE) $(PROGS) $(INSTDIR)
romfs:
$(ROMFSINST) /bin/$(PROGS)
clean:
rm -rf $(PROGS) *.o *.gdb

1
slsDetectorServers/jctbDetectorServer/ansi.h
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@ -1 +0,0 @@
../../slsReceiverSoftware/include/ansi.h

1
slsDetectorServers/jctbDetectorServer/bf_init.sh
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@ -1 +0,0 @@
export PATH=/afs/psi.ch/project/sls_det_firmware/jungfrau_software/uClinux-2010_64bit/bfin-uclinux/bin:$PATH

150
slsDetectorServers/jctbDetectorServer/blackfin.c
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#include "blackfin.h"
#include <sys/ipc.h>
#include <sys/shm.h>
#include <sys/time.h>
#include <string.h>
#include <sys/utsname.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <netinet/in.h>
#include <netinet/tcp.h>
#include <arpa/inet.h>
#include <netdb.h>
#include <time.h>
#include <sys/time.h>
#include <sys/mman.h>
#include <sys/socket.h>
#include <sys/stat.h>
#include <errno.h>
#include <fcntl.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include "server_defs.h"
#include "registers_m.h"
//for memory mapping
u_int32_t CSP0BASE;
u_int16_t volatile *values;
int mapCSP0(void) {
printf("Mapping memory\n");
#ifndef VIRTUAL
int fd;
fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
if (fd == -1) {
printf("\nCan't find /dev/mem!\n");
return FAIL;
}
printf("/dev/mem opened\n");
CSP0BASE = (u_int32_t)mmap(0, MEM_SIZE, PROT_READ|PROT_WRITE, MAP_FILE|MAP_SHARED, fd, CSP0);
if (CSP0BASE == (u_int32_t)MAP_FAILED) {
printf("\nCan't map memmory area!!\n");
return FAIL;
}
printf("CSP0 mapped\n");
#endif
#ifdef VIRTUAL
CSP0BASE = malloc(MEM_SIZE);
printf("memory allocated\n");
#endif
#ifdef SHAREDMEMORY
if ( (res=inism(SMSV))<0) {
printf("error attaching shared memory! %i",res);
return FAIL;
}
#endif
printf("CSPObase is 0x%08x \n",CSP0BASE);
printf("CSPOBASE=from %08x to %08x\n",CSP0BASE,CSP0BASE+MEM_SIZE);
u_int32_t address;
address = FIFO_DATA_REG;//_OFF;
//values=(u_int32_t*)(CSP0BASE+address*2);
values=(u_int16_t*)(CSP0BASE+address*2);
printf("statusreg=%08x\n",bus_r(STATUS_REG));
printf("\n\n");
return OK;
}
u_int16_t bus_r16(u_int32_t offset){
volatile u_int16_t *ptr1;
ptr1=(u_int16_t*)(CSP0BASE+offset*2);
return *ptr1;
}
u_int16_t bus_w16(u_int32_t offset, u_int16_t data) {
volatile u_int16_t *ptr1;
ptr1=(u_int16_t*)(CSP0BASE+offset*2);
*ptr1=data;
return OK;
}
u_int32_t bus_w(u_int32_t offset, u_int32_t data) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(CSP0BASE+offset*2);
*ptr1=data;
return OK;
}
u_int32_t bus_r(u_int32_t offset) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(CSP0BASE+offset*2);
return *ptr1;
}
// program dacq settings
int64_t set64BitReg(int64_t value, int aLSB, int aMSB){
int64_t v64;
u_int32_t vLSB,vMSB;
if (value!=-1) {
vLSB=value&(0xffffffff);
bus_w(aLSB,vLSB);
v64=value>> 32;
vMSB=v64&(0xffffffff);
bus_w(aMSB,vMSB);
// printf("Wreg64(%x,%x) %08x %08x %016llx\n", aLSB>>11, aMSB>>11, vLSB, vMSB, value);
}
return get64BitReg(aLSB, aMSB);
}
int64_t get64BitReg(int aLSB, int aMSB){
int64_t v64;
u_int32_t vLSB,vMSB;
vLSB=bus_r(aLSB);
vMSB=bus_r(aMSB);
v64=vMSB;
v64=(v64<<32) | vLSB;
// printf("reg64(%x,%x) %x %x %llx\n", aLSB, aMSB, vLSB, vMSB, v64);
return v64;
}
/* /\** */
/* /\** ramType is DARK_IMAGE_REG or GAIN_IMAGE_REG *\/ */
/* u_int16_t ram_w16(u_int32_t ramType, int adc, int adcCh, int Ch, u_int16_t data) { */
/* unsigned int adr = (ramType | adc << 8 | adcCh << 5 | Ch ); */
/* // printf("Writing to addr:%x\n",adr); */
/* return bus_w16(adr,data); */
/* } */
/* /\** ramType is DARK_IMAGE_REG or GAIN_IMAGE_REG *\/ */
/* u_int16_t ram_r16(u_int32_t ramType, int adc, int adcCh, int Ch){ */
/* unsigned int adr = (ramType | adc << 8 | adcCh << 5 | Ch ); */
/* // printf("Reading from addr:%x\n",adr); */
/* return bus_r16(adr); */
/* } */
/* **\/ */

25
slsDetectorServers/jctbDetectorServer/blackfin.h
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@ -1,25 +0,0 @@
#ifndef BLACKFIN_H
#define BLACKFIN_H
#define CSP0 0x20200000
#define MEM_SIZE 0x100000
#ifndef OLDVERSION
#define MEM_MAP_SHIFT 1
#endif
#ifdef OLDVERSION
#define MEM_MAP_SHIFT 11
#endif
#include <sys/types.h>
int mapCSP0(void);
u_int16_t bus_r16(u_int32_t offset);
u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
u_int32_t bus_w(u_int32_t offset, u_int32_t data);
u_int32_t bus_r(u_int32_t offset);
int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
int64_t get64BitReg(int aLSB, int aMSB);
#endif

73
slsDetectorServers/jctbDetectorServer/commonServerFunctions.h
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#ifndef COMMON_SERVER_FUNCTIONS_H
#define COMMON_SERVER_FUNCTIONS_H
#ifndef GOTTHARDD //gotthard already had bus_w etc defined in its firmware_funcs.c (not yet made with common files)
#include "blackfin.h"
#endif
/* global variables */
void SPIChipSelect (u_int32_t* valw, u_int32_t addr, u_int32_t csmask) {
// start point
(*valw) = 0xffffffff; // old board compatibility (not using specific bits)
bus_w (addr, (*valw));
// chip sel bar down
(*valw) &= ~csmask; /* todo with test: done a bit different, not with previous value */
bus_w (addr, (*valw));
}
void SPIChipDeselect (u_int32_t* valw, u_int32_t addr, u_int32_t csmask, u_int32_t clkmask) {
// chip sel bar up
(*valw) |= csmask; /* todo with test: not done for spi */
bus_w (addr, (*valw));
//clk down
(*valw) &= ~clkmask;
bus_w (addr, (*valw));
// stop point = start point of course
(*valw) = 0xffffffff; // old board compatibility (not using specific bits)
bus_w (addr, (*valw));
}
void sendDataToSPI (u_int32_t* valw, u_int32_t addr, u_int32_t val, int numbitstosend, u_int32_t clkmask, u_int32_t digoutmask, int digofset) {
int i = 0;
for (i = 0; i < numbitstosend; ++i) {
// clk down
(*valw) &= ~clkmask;
bus_w (addr, (*valw));
// write data (i)
(*valw) = (((*valw) & ~digoutmask) + // unset bit
(((val >> (numbitstosend - 1 - i)) & 0x1) << digofset)); // each bit from val starting from msb
bus_w (addr, (*valw));
// clk up
(*valw) |= clkmask ;
bus_w (addr, (*valw));
}
}
void serializeToSPI(u_int32_t addr, u_int32_t val, u_int32_t csmask, int numbitstosend, u_int32_t clkmask, u_int32_t digoutmask, int digofset) {
#ifdef VERBOSE
if (numbitstosend == 16)
printf("Writing to SPI Register: 0x%04x\n",val);
else
printf("Writing to SPI Register: 0x%08x\n", val);
#endif
u_int32_t valw;
SPIChipSelect (&valw, addr, csmask);
sendDataToSPI(&valw, addr, val, numbitstosend, clkmask, digoutmask, digofset);
SPIChipDeselect(&valw, addr, csmask, clkmask);
}
#endif //COMMON_SERVER_FUNCTIONS_H

1
slsDetectorServers/jctbDetectorServer/communication_funcs.c
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../commonFiles/communication_funcs.c

1
slsDetectorServers/jctbDetectorServer/communication_funcs.h
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../commonFiles/communication_funcs.h

58
slsDetectorServers/jctbDetectorServer/convert_pof_to_raw.c
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// Converts POF files into RAW files for flashing
#include <stdio.h>
#include <stdlib.h>
// Warning: This program is for testing only.
// It makes some assumptions regarding the pof file and the flash size that might be wrong.
// It also overwrites the destination file without any hesitation.
// Handle with care.
int main(int argc, char* argv[])
{
FILE* src;
FILE* dst;
int x;
int y;
int i;
int filepos;
if (argc < 3)
{
printf("%s Sourcefile Destinationfile\n",argv[0]);
return -1;
}
src = fopen(argv[1],"rb");
dst = fopen(argv[2],"wb");
// Remove header (0...11C)
for (filepos=0; filepos < 0x11C; filepos++)
fgetc(src);
// Write 0x80 times 0xFF (0...7F)
for (filepos=0; filepos < 0x80; filepos++)
fputc(0xFF,dst);
// Swap bits and write to file
for (filepos=0x80; filepos < 0x1000000; filepos++)
{
x = fgetc(src);
if (x < 0) break;
y=0;
for (i=0; i < 8; i++)
y=y| ( (( x & (1<<i) ) >> i) << (7-i) ); // This swaps the bits
fputc(y,dst);
}
if (filepos < 0x1000000)
printf("ERROR: EOF before end of flash\n");
printf("To flash the file in Linux do:\n");
printf(" cat /proc/mtd (to findout the right mtd)\n");
printf(" flash_eraseall /dev/mtdX\n");
printf(" cat file > /dev/mtdX\n");
return 0;
}

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slsDetectorServers/jctbDetectorServer/firmware_funcs.c
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239
slsDetectorServers/jctbDetectorServer/firmware_funcs.h
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#ifndef FIRMWARE_FUNCS_H
#define FIRMWARE_FUNCS_H
#include "sls_detector_defs.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <stdarg.h>
#include <unistd.h>
//#include <asm/page.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdarg.h>
#include <unistd.h>
int mapCSP0(void);
u_int16_t bus_r16(u_int32_t offset);
u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
u_int32_t bus_w(u_int32_t offset, u_int32_t data);
u_int32_t bus_r(u_int32_t offset);
//int setPhaseShiftOnce();
//int phaseStep(int st);
//int dbitPhaseStep(int st);
//int getDbitPhase();
int getPhase(int i);
int cleanFifo();
int setDAQRegister();
int configurePhase(int val, int i);
int configureFrequency(int val, int i);
u_int32_t putout(char *s, int modnum);
u_int32_t readin(int modnum);
//u_int32_t setClockDivider(int d, int ic);
//u_int32_t getClockDivider(int ic);
void resetPLL();
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val, int trig);
u_int32_t getPllReconfigReg(u_int32_t reg, int trig);
u_int32_t setSetLength(int d);
u_int32_t getSetLength();
u_int32_t setWaitStates(int d);
u_int32_t getWaitStates();
//u_int32_t setTotClockDivider(int d);
//u_int32_t getTotClockDivider();
//u_int32_t setTotDutyCycle(int d);
//u_int32_t getTotDutyCycle();
u_int32_t setOversampling(int d);
u_int32_t adcPipeline(int d);
u_int32_t dbitPipeline(int d);
u_int32_t setExtSignal(int d, enum externalSignalFlag mode);
int getExtSignal(int d);
u_int32_t setFPGASignal(int d, enum externalSignalFlag mode);
int getFPGASignal(int d);
int setTiming(int t);
int setConfigurationRegister(int d);
int setToT(int d);
int setContinousReadOut(int d);
int startReceiver(int d);
int setDACRegister(int idac, int val, int imod);
int getDacRegister(int dacnum);
int getTemperature(int tempSensor);
int initHighVoltage(int val,int imod);
int initConfGain(int isettings,int val,int imod);
//int setADC(int adc);
//int configureMAC(int ipad, long long int macad, long long int detectormacadd, int detipad, int ival, int udpport);
int configureMAC(uint32_t destip,uint64_t destmac,uint64_t sourcemac,int detipad,int ival,uint32_t destport);
int getAdcConfigured();
u_int64_t getDetectorNumber();
u_int32_t getFirmwareVersion();
u_int32_t getFirmwareSVNVersion();
int testFifos(void);
u_int32_t testFpga(void);
u_int32_t testRAM(void);
int testBus(void);
int setDigitalTestBit(int ival);
int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
int64_t get64BitReg(int aLSB, int aMSB);
int64_t setFrames(int64_t value);
int64_t getFrames();
int64_t setExposureTime(int64_t value);
int64_t getExposureTime();
int64_t setGates(int64_t value);
int64_t getGates();
int64_t setDelay(int64_t value);
int64_t getDelay();
int64_t setPeriod(int64_t value);
int64_t getPeriod();
int64_t setTrains(int64_t value);
int64_t getTrains();
int64_t setProbes(int64_t value);
int64_t getProbes();
int64_t getProgress();
int64_t setProgress();
int64_t getActualTime();
int64_t getMeasurementTime();
int64_t getFramesFromStart();
u_int32_t runBusy(void);
u_int32_t runState(void);
u_int32_t dataPresent(void);
int startStateMachine();
int stopStateMachine();
int startReadOut();
u_int32_t fifoReset(void);
u_int32_t fifoReadCounter(int fifonum);
u_int32_t fifoReadStatus();
u_int32_t fifo_full(void);
u_int16_t* fifo_read_event(int ns);
u_int16_t* fifo_read_frame();
u_int32_t* decode_data(int* datain);
//u_int32_t move_data(u_int64_t* datain, u_int64_t* dataout);
int setDynamicRange(int dr);
int getDynamicRange();
int getNModBoard();
int setNMod(int n);
int getNMod();
int setStoreInRAM(int b);
int allocateRAM();
int writeADC(int addr, int val);
//int prepareADC();
int clearRAM();
int setMaster(int f);
int setSynchronization(int s);
int loadImage(int index, short int ImageVals[]);
int readCounterBlock(int startACQ, short int CounterVals[]);
int resetCounterBlock(int startACQ);
int calibratePedestal(int frames);
uint64_t writePatternWord(int addr, uint64_t word);
uint64_t writePatternIOControl(uint64_t word);
uint64_t writePatternClkControl(uint64_t word);
int setPatternLoop(int level, int *start, int *stop, int *n);
int setPatternWaitAddress(int level, int addr);
uint64_t setPatternWaitTime(int level, uint64_t t);
void initDac(int dacnum);
int setDac(int dacnum,int dacvalue);
int setPower(int ind, int val);
int setROI(int nroi,ROI* arg,int *retvalsize, int *ret);
int getChannels();
int getCurrent(int idac);
int getVoltage(int idac);
void defineGPIOpins();
void resetFPGA();
void FPGAdontTouchFlash();
void FPGATouchFlash();
int startWritingFPGAprogram(FILE** filefp);
int stopWritingFPGAprogram(FILE* filefp);
int writeFPGAProgram(char* fpgasrc, size_t fsize, FILE* filefp);
void eraseFlash();
/*
u_int32_t setNBits(u_int32_t);
u_int32_t getNBits();
*/
/*
//move to mcb_funcs?
int readOutChan(int *val);
u_int32_t getModuleNumber(int modnum);
int testShiftIn(int imod);
int testShiftOut(int imod);
int testShiftStSel(int imod);
int testDataInOut(int num, int imod);
int testExtPulse(int imod);
int testExtPulseMux(int imod, int ow);
int testDataInOutMux(int imod, int ow, int num);
int testOutMux(int imod);
int testFpgaMux(int imod);
int calibration_sensor(int num, int *values, int *dacs) ;
int calibration_chip(int num, int *values, int *dacs);
*/
int64_t setSamples(int64_t value);
//int setOutputMode(int d);
int setReadOutMode(int arg);
int vLimitCompliant(int val_mV)
#endif

12
slsDetectorServers/jctbDetectorServer/get_server.sh
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@ -1,12 +0,0 @@
#!/bin/sh
serv="pc8498"
f="jungfrauDetectorServerTest"
if [ "$#" -gt 0 ]; then
f=$1
fi
if [ "$#" -gt 1 ]; then
serv=$2
fi
tftp $serv -r $f -g
chmod a+xrw $f

9
slsDetectorServers/jctbDetectorServer/gitInfo.txt
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@ -1,9 +0,0 @@
Path: slsDetectorsPackage/slsDetectorSoftware/jctbDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repsitory UUID: 9ae128961675230ad322ff2867f1862dbe8566a7
Revision: 25
Branch: developer
Last Changed Author: Anna_Bergamaschi
Last Changed Rev: 3764
Last Changed Date: 2018-05-07 14:30:14.000000002 +0200 ./Makefile

6
slsDetectorServers/jctbDetectorServer/gitInfoMoench.h
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#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "9ae128961675230ad322ff2867f1862dbe8566a7"
#define GITAUTH "Anna_Bergamaschi"
#define GITREV 0x3764
#define GITDATE 0x20180507
#define GITBRANCH "developer"

BIN
slsDetectorServers/jctbDetectorServer/jctbDetectorServer_developer
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slsDetectorServers/jctbDetectorServer/mcb_funcs.c
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slsDetectorServers/jctbDetectorServer/mcb_funcs.h
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#ifdef MCB_FUNCS
#ifndef MCB_FUNCS_H
#define MCB_FUNCS_H
#include "sls_detector_defs.h"
#define RGPRVALS {100,50,200}
#define RGSH1VALS {300,200,400}
#define RGSH2VALS {260,300,260}
#define DEFAULTGAIN {11.66,9.32,14.99}
#define DEFAULTOFFSET {817.5,828.6,804.2}
// DAC definitions
enum dacsVal{VDAC0, VDAC1, VDAC2, VDAC3, VDAC4, VDAC5, VDAC6, VDAC7, HIGH_VOLTAGE, CONFGAIN};
/* DAC adresses */
#define DACCS {0,0,1,1,2,2,3,3,4,4,5,5,6,6}
#define DACADDR {0,1,0,1,0,1,0,1,0,1,0,1,0,1}
//Register Definitions for temp,hv,dac gain
enum adcVals{TEMP_FPGA, TEMP_ADC};
//dynamic range
/*
#define MAX5523 commented out by dhanya
#ifndef MAX5523
#define MAX5533
#endif
#ifdef MAX5533
#define DAC_DR 4096
#endif
#ifdef MAX5523
*/
#define DAC_DR 1024
//#endif
//reference voltage
#define DAC_REFOUT1
#ifdef DAC_REFOUT2
#define DAC_MAX 2.425
#define DAC_REFOUT 2
#define DAC_REFOUT1
#endif
#ifdef DAC_REFOUT3
#define DAC_MAX 3.885
#define DAC_REFOUT 3
#define DAC_REFOUT1
#endif
#ifdef DAC_REFOUT0
#define DAC_MAX 1.214
#define DAC_REFOUT 0
#endif
#ifdef DAC_REFOUT1
#define DAC_MAX 1.940
#define DAC_REFOUT 1
#endif
/* dac calibration constants */
#define VA 1.11
#define CVTRIM 52.430851
#define BVTRIM -0.102022
#define AVTRIM 0.000050
#define PARTREF {100,1.55,-2.5,-2.5,0,-2.5}
#define PARTR1 {78,10,10,10,10,10}
#define PARTR2 {0,4.7,27,47,22,47}
//chip shiftin register meaning
#define OUTMUX_OFFSET 20
#define PROBES_OFFSET 4
#define OUTBUF_OFFSET 0
void showbits(int h);
int initDetector();
int copyChannel(sls_detector_channel *destChan, sls_detector_channel *srcChan);
int copyChip(sls_detector_chip *destChip, sls_detector_chip *srcChip);
int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod);
/* Register commands */
/* int clearDACSregister(int imod ); */
/* int nextDAC(int imod ); */
int clearCSregister(int imod );
int setCSregister(int imod );
int nextChip(int imod );
int firstChip(int imod );
int clearSSregister(int imod );
int setSSregister(int imod );
int nextStrip(int imod );
int selChannel(int strip,int imod );
int selChip(int chip,int imod );
int selMod(int mod,int imod );
/* DACs routines */
/* int program_one_dac(int addr, int value,int imod ); */
/* int set_one_dac(int imod); */
/* int initDAC(int dac_addr, int value,int imod ); */
/* int initDACs(int* v,int imod ); */
/* int initDACbyIndex(int ind,int val, int imod); */
/* int initDACbyIndexDACU(int ind,int val, int imod); */
/* int getDACbyIndexDACU(int ind, int imod); */
/* int getThresholdEnergy(); */
/* int setThresholdEnergy(int ethr); */
int setSettings(int i,int imod);
/* Other DAC index routines*/
int getTemperatureByModule(int tempSensor, int imod);
int initHighVoltageByModule(int val, int imod);
int initConfGainByModule(int isettings,int val,int imod);
/* Initialization*/
int initChannel(int ft,int cae, int ae, int coe, int ocoe, int counts,int imod );
int initChannelbyNumber(sls_detector_channel myChan);
int getChannelbyNumber(sls_detector_channel*);
int getTrimbit(int imod, int ichip, int ichan);
int initChip(int obe, int ow,int imod );
int initChipWithProbes(int obe, int ow,int nprobes, int imod);
//int getNProbes();
int initChipbyNumber(sls_detector_chip myChip);
int getChipbyNumber(sls_detector_chip*);
int initMCBregisters(int cm,int imod );
int initModulebyNumber(sls_detector_module);
int getModulebyNumber(sls_detector_module*);
/* To chips */
int clearCounter(int imod );
int clearOutReg(int imod);
int setOutReg(int imod );
int extPulse(int ncal,int imod );
int calPulse(int ncal,int imod );
int counterClear(int imod );
int countEnable(int imod );
int counterSet(int imod );
/* moved from firmware_funcs */
int readOutChan(int *val);
int getModuleNumber(int modnum);
int testShiftIn(int imod);
int testShiftOut(int imod);
int testShiftStSel(int imod);
int testDataInOut(int num, int imod);
int testExtPulse(int imod);
int testExtPulseMux(int imod, int ow);
int testDataInOutMux(int imod, int ow, int num);
int testOutMux(int imod);
int testFpgaMux(int imod);
int calibration_sensor(int num, int *values, int *dacs) ;
int calibration_chip(int num, int *values, int *dacs);
//ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret);
#endif
#endif

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slsDetectorServers/jctbDetectorServer/patternGenerator/generate.sh
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@ -1,30 +0,0 @@
if [ "$#" -eq 0 ]; then
echo "Wrong number of arguments: usage should be $0 patname"
exit 1
fi
infile=$1
outfile=$infile"at"
outfilebin=$infile"bin"
if [ "$#" -ge 2 ]; then
outfile=$2
fi
exe=$infile"exe"
if [ "$#" -ge 4 ]; then
exe=$4
fi
if [ "$#" -ge 3 ]; then
outfilebin=$3
fi
if [ -f "$infile" ]
then
gcc -DINFILE="\"$infile\"" -DOUTFILE="\"$outfile\"" -DOUTFILEBIN="\"$outfilebin\"" -o $exe generator.c ;
echo compiling
$exe ;
echo cleaning
rm $exe
echo done
else
echo "$infile not found."
fi

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slsDetectorServers/jctbDetectorServer/patternGenerator/generator.c
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@ -1,162 +0,0 @@
/****************************************************************************
usage to generate a patter test.pat from test.p
gcc -DINFILE="\"test.p\"" -DOUTFILE="\"test.pat\"" -o test.exe generator.c ; ./test.exe ; rm test.exe
*************************************************************************/
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <sys/utsname.h>
#include <sys/types.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <errno.h>
#include <math.h>
#include <fcntl.h>
#include <stdarg.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#define MAXLOOPS 3
#define MAXTIMERS 3
#define MAXWORDS 1024
uint64_t pat=0;
uint64_t iopat=0;
uint64_t clkpat=0;
int iaddr=0;
int waitaddr[3]={MAXWORDS,MAXWORDS,MAXWORDS};
int startloopaddr[3]={MAXWORDS,MAXWORDS,MAXWORDS};
int stoploopaddr[3]={MAXWORDS,MAXWORDS,MAXWORDS};
int start=0, stop=0;
uint64_t waittime[3]={0,0,0};
int nloop[3]={0,0,0};
char infile[10000], outfile[10000];
FILE *fd, *fd1;
uint64_t PAT[MAXWORDS];
int i,ii,iii,j,jj,jjj,pixx,pixy,memx,memy,muxout,memclk,colclk,rowclk,muxclk,memcol,memrow,loopcounter;
void setstart() {
start=iaddr;
}
void setstop() {
stop=iaddr;
}
void setinput(int bit) {
uint64_t mask=1;
mask=mask<<bit;
iopat &= ~mask;
}
void setoutput(int bit) {
uint64_t mask=1;
mask=mask<<bit;
iopat |= mask;
}
void setclk(int bit) {
uint64_t mask=1;
mask=mask<<bit;
iopat |= mask;
clkpat |= mask;
}
void clearbit(int bit){
uint64_t mask=1;
mask=mask<<bit;
pat &= ~mask;
}
void setbit(int bit){
uint64_t mask=1;
mask=mask<<bit;
pat |= mask;
}
int checkbit(int bit) {
uint64_t mask=1;
mask=mask<<bit;
return (pat & mask ) >>bit;
}
void setstartloop(int iloop) {
if (iloop>=0 && iloop<MAXLOOPS)
startloopaddr[iloop]=iaddr;
}
void setstoploop(int iloop) {
if (iloop>=0 && iloop<MAXLOOPS)
stoploopaddr[iloop]=iaddr;
}
void setnloop(int iloop, int n) {
if (iloop>=0 && iloop<MAXLOOPS)
nloop[iloop]=n;
}
void setwaitpoint(int iloop) {
if (iloop>=0 && iloop<MAXTIMERS)
waitaddr[iloop]=iaddr;
}
void setwaittime(int iloop, uint64_t t) {
if (iloop>=0 && iloop<MAXTIMERS)
waittime[iloop]=t;
}
void pw(){
if (iaddr<MAXWORDS)
PAT[iaddr]= pat;
fprintf(fd,"patword %04x %016llx\n",iaddr, pat);
iaddr++;
if (iaddr>=MAXWORDS) printf("ERROR: too many word in the pattern (%d instead of %d)!",iaddr, MAXWORDS);
}
main(void) {
int iloop=0;
fd=fopen(OUTFILE,"w");
#include INFILE
fprintf(fd,"patioctrl %016llx\n",iopat);
fprintf(fd,"patclkctrl %016llx\n",clkpat);
fprintf(fd,"patlimits %04x %04x\n",start, stop);
for (iloop=0; iloop<MAXLOOPS; iloop++) {
fprintf(fd,"patloop%d %04x %04x\n",iloop, startloopaddr[iloop], stoploopaddr[iloop]);
if ( startloopaddr[iloop]<0 || stoploopaddr[iloop]<= startloopaddr[iloop]) nloop[iloop]=0;
fprintf(fd,"patnloop%d %d\n",iloop, nloop[iloop]);
}
for (iloop=0; iloop<MAXTIMERS; iloop++) {
fprintf(fd,"patwait%d %04x\n",iloop, waitaddr[iloop]);
if (waitaddr[iloop]<0) waittime[iloop]=0;
fprintf(fd,"patwaittime%d %lld\n",iloop, waittime[iloop]);
}
close((int)fd);
fd1=fopen(OUTFILEBIN,"w");
fwrite(PAT,sizeof(uint64_t),iaddr, fd1);
close((int)fd1);
}

201
slsDetectorServers/jctbDetectorServer/patternGenerator/test.p
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@ -1,201 +0,0 @@
//define signals and directions (Input, outputs, clocks)
#define compTestIN 1
setoutput(compTestIN);
#define curON 32
setoutput(curON);
#define side_clk 2
setclk(side_clk);
#define side_din 3
setoutput(side_din);
#define clear_shr 4
setoutput(clear_shr);
#define bottom_din 5
setoutput(bottom_din);
#define bottom_clk 6
setclk(bottom_clk);
#define gHG 7
setoutput(gHG);
#define bypassCDS 31
setoutput(bypassCDS);
#define ENprechPRE 8
setoutput(ENprechPRE);
#define res 9
setoutput(res);
#define pulseOFF 30
setoutput(pulseOFF);
#define connCDS 27
setoutput(connCDS);
#define Dsg_1 24
setoutput(Dsg_1);
#define Dsg_2 25
setoutput(Dsg_2);
#define Dsg_3 23
setoutput(Dsg_3);
#define sto0 10
setoutput(sto0);
#define sto1 11
setoutput(sto1);
#define sto2 12
setoutput(sto2);
#define resCDS 13
setoutput(resCDS);
#define prechargeConnect 14
setoutput(prechargeConnect);
#define pulse 15
setoutput(pulse);
#define PCT_mode 21
setoutput(PCT_mode);
#define res_DGS 16
setoutput(res_DGS);
#define adc_ena 17
setoutput(adc_ena);
#define CLKBIT 18
setclk(CLKBIT);
#define adc_sync 63
setoutput(adc_sync);
#define PW pw()
#define SB(x) setbit(x)
#define CB(x) clearbit(x)
#define CLOCK clearbit(CLKBIT); pw();setbit(CLKBIT);pw()
#define LCLOCK clearbit(CLKBIT); pw();setbit(CLKBIT);pw();clearbit(CLKBIT); pw()
#define CLOCKS(x) for (i=0;i<x;i++) {clearbit(CLKBIT);pw(); setbit(CLKBIT); pw();}
#define STOP setstop();
#define START setstart();
#define REPEAT(x) for (i=0;i<(x);i++) {pw();}
#define DOFOR(x) for (j=0;j<(x);j++) {
// }
#define STARTUP1 CB(compTestIN);SB(clear_shr);CB(side_clk);CB(side_din);CB(bottom_din);CB(bottom_clk);
#define STARTUP2 CB(pulse);SB(PCT_mode);SB(pulseOFF);CB(curON);
#define STARTUP3 SB(res);SB(gHG);SB(ENprechPRE);
#define STARTUP4 SB(bypassCDS); CB(connCDS);CB(sto0);SB(sto1);SB(sto2);
#define STARTUP5 SB(resCDS);CB(Dsg_1);CB(Dsg_2);SB(Dsg_3);CB(prechargeConnect);SB(res_DGS);
#define STARTUP STARTUP1 STARTUP2 STARTUP3 STARTUP4 STARTUP5 PW;
//****NOTES****//
//FUNCTIONS
//Declare functions at the beginning
void load_pix(int nx, int ny)
{//SELECT PIXEL 1,1 for readout
SB(clear_shr);PW;PW;
CB(clear_shr);PW;PW;PW;PW;
SB(side_din);PW;
SB(side_clk);PW;
CB(side_din);
setstartloop(0); //loop on the rows
SB(side_clk);PW;
setstoploop(0); //finish loop on the rows
setnloop(0,ny); //set number row selected -can be changed dynamically
CB(side_clk);PW;
SB(bottom_din);PW;
SB(bottom_clk);PW;
CB(bottom_din);
setstartloop(1); //loop on the columns
SB(bottom_clk);PW;
setstoploop(1); //loop on the columns
setnloop(1,ny); //set number columns selected -can be changed dynamically
}
void load_col(void)
{//SELECT COLUMN 1 for readout
SB(clear_shr);PW;PW;
CB(clear_shr);PW;PW;PW;PW;
SB(bottom_din);PW;
SB(bottom_clk);PW;
CB(bottom_clk);PW;
CB(bottom_din);PW;
}
//END of FUNCTIONS
////////////////////////////////////////////////////////
//LET BYPASS PREAMP AND CDS and write on preamp out.//
//THIS ALLOWS CHECKING SOURCE FOLLOWERS //
////////////////////////////////////////////////////////
PW;
SB(5); PW;
CB(5); PW;
START; //pattern starts from here
STARTUP;
setwaitpoint(0); //set wait points
PW;
setwaittime(0,20); //wait time - can be changed dynamically
SB(adc_ena);PW;
printf("ADC sync %x %d %llx\n",iaddr,adc_sync, pat);
SB(adc_sync);PW;
printf("ADC sync %x %d %llx\n",iaddr, adc_sync, pat);
CB(gHG);
setwaitpoint(1); //set wait points
setwaittime(1,16); //wait time - can be changed dynamically
CB(adc_sync);PW;
load_pix(10, 20);
CB(res);
//CB(Dsg_3);PW;
CB(res_DGS);
setwaitpoint(2); //set wait points
setwaittime(2,1000); //wait time - can be changed dynamically
//SB(res_DGS);
//PW;
//SB(Dsg_3);
//
//CB(connCDS);
//TEST SIGNALS END
//
REPEAT(20)
//****************//
//*FINAL COMMANDS*//
//****************//
CB(adc_ena);PW;
//STARTUP;
STOP; PW; //stops here
//REPEAT(4);

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slsDetectorServers/jctbDetectorServer/program_fpga.sh
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#!/bin/sh
serv="pc8498"
f="Jungfrau_CTB.rawbin"
if [ "$#" -gt 0 ]; then
f=$1
fi
if [ "$#" -gt 1 ]; then
serv=$2
fi
echo "File is $f server is $serv"
mount -t tmpfs none /mnt/
cd /mnt/
tftp -r $f -g $serv
echo 7 > /sys/class/gpio/export
echo 9 > /sys/class/gpio/export
echo in > /sys/class/gpio/gpio7/direction
echo out > /sys/class/gpio/gpio9/direction
echo 0 > /sys/class/gpio/gpio9/value
flash_eraseall /dev/mtd3
cat /mnt/$f > /dev/mtd3
echo 1 > /sys/class/gpio/gpio9/value
cat /sys/class/gpio/gpio7/value

551
slsDetectorServers/jctbDetectorServer/registers_m.h
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#ifndef REGISTERS_G_H
#define REGISTERS_G_H
#include "sls_detector_defs.h"
/* Definitions for FPGA*/
#define CSP0 0x20200000
#define MEM_SIZE 0x100000
/* values defined for FPGA */
#define MCSNUM 0x0
#define FIXED_PATT_VAL 0xacdc1980
#define FPGA_INIT_PAT 0x60008
#define FPGA_INIT_ADDR 0xb0000000
//#ifdef JUNGFRAU_DHANYA
#define POWER_ON_REG 0x5e << MEM_MAP_SHIFT
// Pwr_I2C_SDA <= PowerReg_s(1) when PowerReg_s(3)='1' else 'Z';
// Pwr_I2C_SCL <= PowerReg_s(0) when PowerReg_s(2)='1' else 'Z';
#define PWR_I2C_SCL_BIT 0
#define PWR_I2C_SDA_BIT 1
#define PWR_I2C_SCL_EN_BIT 2
#define PWR_I2C_SDA_EN_BIT 3
#define POWER_STATUS_REG 41 << MEM_MAP_SHIFT
#define ADCREG1 0x08
#define ADCREG2 0x14//20
#define ADCREG3 0x4
#define ADCREG4 0x5
#define ADCREG_VREFS 24
#define DBIT_PIPELINE_REG 89 << MEM_MAP_SHIFT //0x59 same PATTERN_N_LOOP2_REG
#define MEM_MACHINE_FIFOS_REG 79 << MEM_MAP_SHIFT //from gotthard
#define CONFGAIN_REG 93 << MEM_MAP_SHIFT //from gotthard
#define ADC_PIPELINE_REG 66 << MEM_MAP_SHIFT //0x42 same as ADC_OFFSET_REG
//#endif
//#define ADC_OFFSET_REG 93 << MEM_MAP_SHIFT //same as DAQ_REG
#define ADC_INVERSION_REG 67 << MEM_MAP_SHIFT
#define DAC_REG 64 << MEM_MAP_SHIFT//0x17 << MEM_MAP_SHIFT// control the dacs
//ADC
#define ADC_WRITE_REG 65 << MEM_MAP_SHIFT//0x18 << MEM_MAP_SHIFT
//#define ADC_SYNC_REG 66 << MEM_MAP_SHIFT//0x19 << MEM_MAP_SHIFT
//#define HV_REG 67 << MEM_MAP_SHIFT//0x20 << MEM_MAP_SHIFT
//#define MUTIME_REG 0x1a << MEM_MAP_SHIFT
//temperature
#define TEMP_IN_REG 0x1b << MEM_MAP_SHIFT
#define TEMP_OUT_REG 0x1c << MEM_MAP_SHIFT
//configure MAC
#define TSE_CONF_REG 0x1d << MEM_MAP_SHIFT
#define ENET_CONF_REG 0x1e << MEM_MAP_SHIFT
//#define WRTSE_SHAD_REG 0x1f << MEM_MAP_SHIFT
//HV
#define DUMMY_REG 68 << MEM_MAP_SHIFT//0x21 << MEM_MAP_SHIFT
#define FPGA_VERSION_REG 0 << MEM_MAP_SHIFT //0x22 << MEM_MAP_SHIFT
#define PCB_REV_REG 0 << MEM_MAP_SHIFT
#define FIX_PATT_REG 1 << MEM_MAP_SHIFT //0x23 << MEM_MAP_SHIFT
#define CONTROL_REG 79 << MEM_MAP_SHIFT//0x24 << MEM_MAP_SHIFT
#define STATUS_REG 2 << MEM_MAP_SHIFT //0x25 << MEM_MAP_SHIFT
#define CONFIG_REG 77 << MEM_MAP_SHIFT//0x26 << MEM_MAP_SHIFT
#define EXT_SIGNAL_REG 78 << MEM_MAP_SHIFT// 0x27 << MEM_MAP_SHIFT
//#define FPGA_SVN_REG 0x29 << MEM_MAP_SHIFT
#define CHIP_OF_INTRST_REG 0x2A << MEM_MAP_SHIFT
//FIFO
#define LOOK_AT_ME_REG 3 << MEM_MAP_SHIFT //0x28 << MEM_MAP_SHIFT
#define SYSTEM_STATUS_REG 4 << MEM_MAP_SHIFT
#define FIFO_DATA_REG 6 << MEM_MAP_SHIFT
#define FIFO_STATUS_REG 7 << MEM_MAP_SHIFT
// constant FifoDigitalInReg_c : integer := 60;
#define FIFO_DIGITAL_DATA_LSB_REG 60 << MEM_MAP_SHIFT
#define FIFO_DIGITAL_DATA_MSB_REG 61 << MEM_MAP_SHIFT
#define FIFO_DATA_REG_OFF 0x50 << MEM_MAP_SHIFT ///////
//to read back dac registers
//#define MOD_DACS1_REG 0x65 << MEM_MAP_SHIFT
//#define MOD_DACS2_REG 0x66 << MEM_MAP_SHIFT
//#define MOD_DACS3_REG 0x67 << MEM_MAP_SHIFT
//user entered
#define GET_ACTUAL_TIME_LSB_REG 16 << MEM_MAP_SHIFT
#define GET_ACTUAL_TIME_MSB_REG 17 << MEM_MAP_SHIFT
#define GET_MEASUREMENT_TIME_LSB_REG 38 << MEM_MAP_SHIFT
#define GET_MEASUREMENT_TIME_MSB_REG 39 << MEM_MAP_SHIFT
#define SET_DELAY_LSB_REG 96 << MEM_MAP_SHIFT //0x68 << MEM_MAP_SHIFT
#define SET_DELAY_MSB_REG 97 << MEM_MAP_SHIFT //0x69 << MEM_MAP_SHIFT
#define GET_DELAY_LSB_REG 18 << MEM_MAP_SHIFT//0x6a << MEM_MAP_SHIFT
#define GET_DELAY_MSB_REG 19 << MEM_MAP_SHIFT//0x6b << MEM_MAP_SHIFT
#define SET_CYCLES_LSB_REG 98 << MEM_MAP_SHIFT//0x6c << MEM_MAP_SHIFT
#define SET_CYCLES_MSB_REG 99 << MEM_MAP_SHIFT//0x6d << MEM_MAP_SHIFT
#define GET_CYCLES_LSB_REG 20 << MEM_MAP_SHIFT//0x6e << MEM_MAP_SHIFT
#define GET_CYCLES_MSB_REG 21 << MEM_MAP_SHIFT//0x6f << MEM_MAP_SHIFT
#define SET_FRAMES_LSB_REG 100 << MEM_MAP_SHIFT//0x70 << MEM_MAP_SHIFT
#define SET_FRAMES_MSB_REG 101 << MEM_MAP_SHIFT//0x71 << MEM_MAP_SHIFT
#define GET_FRAMES_LSB_REG 22 << MEM_MAP_SHIFT//0x72 << MEM_MAP_SHIFT
#define GET_FRAMES_MSB_REG 23 << MEM_MAP_SHIFT//0x73 << MEM_MAP_SHIFT
#define SET_PERIOD_LSB_REG 102 << MEM_MAP_SHIFT//0x74 << MEM_MAP_SHIFT
#define SET_PERIOD_MSB_REG 103 << MEM_MAP_SHIFT//0x75 << MEM_MAP_SHIFT
#define GET_PERIOD_LSB_REG 24 << MEM_MAP_SHIFT//0x76 << MEM_MAP_SHIFT
#define GET_PERIOD_MSB_REG 25 << MEM_MAP_SHIFT//0x77 << MEM_MAP_SHIFT
//#define PATTERN_WAIT0_TIME_REG_LSB 114 << MEM_MAP_SHIFT
//#define PATTERN_WAIT0_TIME_REG_MSB 115 << MEM_MAP_SHIFT
#define SET_EXPTIME_LSB_REG 114 << MEM_MAP_SHIFT//0x78 << MEM_MAP_SHIFT
#define SET_EXPTIME_MSB_REG 115 << MEM_MAP_SHIFT//0x79 << MEM_MAP_SHIFT
#define GET_EXPTIME_LSB_REG 26 << MEM_MAP_SHIFT//0x7a << MEM_MAP_SHIFT
#define GET_EXPTIME_MSB_REG 27 << MEM_MAP_SHIFT//0x7b << MEM_MAP_SHIFT
#define SET_GATES_LSB_REG 106 << MEM_MAP_SHIFT//0x7c << MEM_MAP_SHIFT
#define SET_GATES_MSB_REG 107 << MEM_MAP_SHIFT//0x7d << MEM_MAP_SHIFT
#define GET_GATES_LSB_REG 28 << MEM_MAP_SHIFT//0x7e << MEM_MAP_SHIFT
#define GET_GATES_MSB_REG 29 << MEM_MAP_SHIFT//0x7f << MEM_MAP_SHIFT
#define DATA_IN_LSB_REG 30 << MEM_MAP_SHIFT
#define DATA_IN_MSB_REG 31 << MEM_MAP_SHIFT
#define PATTERN_OUT_LSB_REG 32 << MEM_MAP_SHIFT
#define PATTERN_OUT_MSB_REG 33 << MEM_MAP_SHIFT
#define FRAMES_FROM_START_LSB_REG 34 << MEM_MAP_SHIFT
#define FRAMES_FROM_START_MSB_REG 35 << MEM_MAP_SHIFT
#define FRAMES_FROM_START_PG_LSB_REG 36 << MEM_MAP_SHIFT
#define FRAMES_FROM_START_PG_MSB_REG 37 << MEM_MAP_SHIFT
#define SLOW_ADC_REG 43 << MEM_MAP_SHIFT
#define PLL_PARAM_REG 80 << MEM_MAP_SHIFT//0x37 << MEM_MAP_SHIFT
#define PLL_PARAM_OUT_REG 5 << MEM_MAP_SHIFT //0x38 << MEM_MAP_SHIFT
#define PLL_CNTRL_REG 81 << MEM_MAP_SHIFT//0x34 << MEM_MAP_SHIFT
#ifdef NEW_GBE_INTERFACE
#define GBE_PARAM_OUT_REG 40 << MEM_MAP_SHIFT
#define GBE_PARAM_REG 69 << MEM_MAP_SHIFT
#define GBE_CNTRL_REG 70 << MEM_MAP_SHIFT
#else
#define RX_UDP_AREG 69 << MEM_MAP_SHIFT //rx_udpip_AReg_c : integer:= 69; *\/
#define UDPPORTS_AREG 70 << MEM_MAP_SHIFT// udpports_AReg_c : integer:= 70; *\/
#define RX_UDPMACL_AREG 71 << MEM_MAP_SHIFT//rx_udpmacL_AReg_c : integer:= 71; *\/
#define RX_UDPMACH_AREG 72 << MEM_MAP_SHIFT//rx_udpmacH_AReg_c : integer:= 72; *\/
#define DETECTORMACL_AREG 73 << MEM_MAP_SHIFT//detectormacL_AReg_c : integer:= 73; *\/
#define DETECTORMACH_AREG 74 << MEM_MAP_SHIFT//detectormacH_AReg_c : integer:= 74; *\/
#define DETECTORIP_AREG 75 << MEM_MAP_SHIFT//detectorip_AReg_c : integer:= 75; *\/
#define IPCHKSUM_AREG 76 << MEM_MAP_SHIFT//ipchksum_AReg_c : integer:= 76; *\/ */
#endif
#define PATTERN_CNTRL_REG 82 << MEM_MAP_SHIFT
#define PATTERN_LIMITS_AREG 83 << MEM_MAP_SHIFT
#define PATTERN_LOOP0_AREG 84 << MEM_MAP_SHIFT
#define PATTERN_N_LOOP0_REG 85 << MEM_MAP_SHIFT
#define PATTERN_LOOP1_AREG 86 << MEM_MAP_SHIFT
#define PATTERN_N_LOOP1_REG 87 << MEM_MAP_SHIFT
#define PATTERN_LOOP2_AREG 88 << MEM_MAP_SHIFT
#define PATTERN_N_LOOP2_REG 89 << MEM_MAP_SHIFT
#define PATTERN_WAIT0_AREG 90 << MEM_MAP_SHIFT
#define PATTERN_WAIT1_AREG 91 << MEM_MAP_SHIFT
#define PATTERN_WAIT2_AREG 92 << MEM_MAP_SHIFT
//#define DAQ_REG 93 << MEM_MAP_SHIFT //unused
#define NSAMPLES_REG 93 << MEM_MAP_SHIFT
#define HV_REG 95 << MEM_MAP_SHIFT
#define PATTERN_IOCTRL_REG_LSB 108 << MEM_MAP_SHIFT
#define PATTERN_IOCTRL_REG_MSB 109 << MEM_MAP_SHIFT
#define PATTERN_IOCLKCTRL_REG_LSB 110 << MEM_MAP_SHIFT
#define PATTERN_IOCLKCTRL_REG_MSB 111 << MEM_MAP_SHIFT
#define PATTERN_IN_REG_LSB 112 << MEM_MAP_SHIFT
#define PATTERN_IN_REG_MSB 113 << MEM_MAP_SHIFT
#define PATTERN_WAIT0_TIME_REG_LSB 114 << MEM_MAP_SHIFT
#define PATTERN_WAIT0_TIME_REG_MSB 115 << MEM_MAP_SHIFT
#define PATTERN_WAIT1_TIME_REG_LSB 116 << MEM_MAP_SHIFT
#define PATTERN_WAIT1_TIME_REG_MSB 117 << MEM_MAP_SHIFT
#define PATTERN_WAIT2_TIME_REG_LSB 118 << MEM_MAP_SHIFT
#define PATTERN_WAIT2_TIME_REG_MSB 119 << MEM_MAP_SHIFT
//#define DAC_REG_OFF 120
//#define DAC_0_1_VAL_REG 120 << MEM_MAP_SHIFT
//#define DAC_2_3_VAL_REG 121 << MEM_MAP_SHIFT
//#define DAC_4_5_VAL_REG 122 << MEM_MAP_SHIFT
//#define DAC_6_7_VAL_REG 123 << MEM_MAP_SHIFT
//#define DAC_8_9_VAL_REG 124 << MEM_MAP_SHIFT
//#define DAC_10_11_VAL_REG 125 << MEM_MAP_SHIFT
//#define DAC_12_13_VAL_REG 126 << MEM_MAP_SHIFT
//#define DAC_14_15_VAL_REG 127 << MEM_MAP_SHIFT
#define DAC_VAL_REG 121 << MEM_MAP_SHIFT
#define DAC_NUM_REG 122 << MEM_MAP_SHIFT
#define DAC_VAL_OUT_REG 42 << MEM_MAP_SHIFT
#define ADC_LATCH_DISABLE_REG 120 << MEM_MAP_SHIFT
/* registers defined in FPGA */
#define GAIN_REG 0
//#define FLOW_CONTROL_REG 0x11 << MEM_MAP_SHIFT
//#define FLOW_STATUS_REG 0x12 << MEM_MAP_SHIFT
//#define FRAME_REG 0x13 << MEM_MAP_SHIFT
#define MULTI_PURPOSE_REG 0
//#define TIME_FROM_START_REG 0x16 << MEM_MAP_SHIFT
#define ROI_REG 0 // 0x35 << MEM_MAP_SHIFT
#define OVERSAMPLING_REG 0 // 0x36 << MEM_MAP_SHIFT
#define MOENCH_CNTR_REG 0 // 0x31 << MEM_MAP_SHIFT
#define MOENCH_CNTR_OUT_REG 0 // 0x33 << MEM_MAP_SHIFT
#define MOENCH_CNTR_CONF_REG 0 // 0x32 << MEM_MAP_SHIFT
//image
#define DARK_IMAGE_REG 0 // 0x81 << MEM_MAP_SHIFT
#define GAIN_IMAGE_REG 0 // 0x82 << MEM_MAP_SHIFT
//counter block memory
#define COUNTER_MEMORY_REG 0 // 0x85 << MEM_MAP_SHIFT
//not used
//#define MCB_DOUT_REG_OFF 0 // 0x200000
//#define FIFO_CNTRL_REG_OFF 0 // 0x300000
//#define FIFO_COUNTR_REG_OFF 0 // 0x400000
//not used so far
//#define SPEED_REG 0 // 0x006000
//#define SET_NBITS_REG 0 // 0x008000
//not used
//#define GET_SHIFT_IN_REG 0 // 0x022000
#define SHIFTMOD 2
#define SHIFTFIFO 9
/** for PCB_REV_REG */
#define DETECTOR_TYPE_MASK 0xFF000000
#define DETECTOR_TYPE_OFFSET 24
#define BOARD_REVISION_MASK 0xFFFFFF
#define MOENCH03_MODULE_ID 2
#define JUNGFRAU_MODULE_ID 1
#define JUNGFRAU_CTB_ID 3
/* for control register (16bit only)*/
#define START_ACQ_BIT 0x0001
#define STOP_ACQ_BIT 0x0002
#define START_FIFOTEST_BIT 0x0004 // ?????
#define STOP_FIFOTEST_BIT 0x0008 // ??????
#define START_READOUT_BIT 0x0010
#define STOP_READOUT_BIT 0x0020
#define START_EXPOSURE_BIT 0x0040
#define STOP_EXPOSURE_BIT 0x0080
#define START_TRAIN_BIT 0x0100
#define STOP_TRAIN_BIT 0x0200
#define FIFO_RESET_BIT 0x8000
#define SYNC_RESET 0x0400
#define GB10_RESET_BIT 0x0800
#define MEM_RESET_BIT 0x1000
/* for status register */
#define RUN_BUSY_BIT 0x00000001
#define READOUT_BUSY_BIT 0x00000002
#define FIFOTEST_BUSY_BIT 0x00000004 //????
#define WAITING_FOR_TRIGGER_BIT 0x00000008
#define DELAYBEFORE_BIT 0x00000010
#define DELAYAFTER_BIT 0x00000020
#define EXPOSING_BIT 0x00000040
#define COUNT_ENABLE_BIT 0x00000080
#define READSTATE_0_BIT 0x00000100
#define READSTATE_1_BIT 0x00000200
#define READSTATE_2_BIT 0x00000400
#define LAM_BIT 0x00000400 // error!
#define SOME_FIFO_FULL_BIT 0x00000800 // error!
#define RUNSTATE_0_BIT 0x00001000
#define RUNSTATE_1_BIT 0x00002000
#define RUNSTATE_2_BIT 0x00004000
#define STOPPED_BIT 0x00008000 // stopped!
#define ALL_FIFO_EMPTY_BIT 0x00010000 // data ready
#define RUNMACHINE_BUSY_BIT 0x00020000
#define READMACHINE_BUSY_BIT 0x00040000
#define PLL_RECONFIG_BUSY 0x00100000
/* for fifo status register */
#define FIFO_ENABLED_BIT 0x80000000
#define FIFO_DISABLED_BIT 0x01000000
#define FIFO_ERROR_BIT 0x08000000
#define FIFO_EMPTY_BIT 0x04000000
#define FIFO_DATA_READY_BIT 0x02000000
#define FIFO_COUNTER_MASK 0x000001ff
#define FIFO_NM_MASK 0x00e00000
#define FIFO_NM_OFF 21
#define FIFO_NC_MASK 0x001ffe00
#define FIFO_NC_OFF 9
/* for config register *///not really used yet
#define TOT_ENABLE_BIT 0x00000002
#define TIMED_GATE_BIT 0x00000004
#define CONT_RO_ENABLE_BIT 0x00080000
#define GB10_NOT_CPU_BIT 0x00001000
#define ADC_OUTPUT_DISABLE_BIT 0x00100
#define DIGITAL_OUTPUT_ENABLE_BIT 0x00200
/* for speed register */
#define CLK_DIVIDER_MASK 0x000000ff
#define CLK_DIVIDER_OFFSET 0
#define SET_LENGTH_MASK 0x00000f00
#define SET_LENGTH_OFFSET 8
#define WAIT_STATES_MASK 0x0000f000
#define WAIT_STATES_OFFSET 12
#define TOTCLK_DIVIDER_MASK 0xff000000
#define TOTCLK_DIVIDER_OFFSET 24
#define TOTCLK_DUTYCYCLE_MASK 0x00ff0000
#define TOTCLK_DUTYCYCLE_OFFSET 16
/* for external signal register */
#define SIGNAL_OFFSET 4
#define SIGNAL_MASK 0xF
#define EXT_SIG_OFF 0x0
#define EXT_GATE_IN_ACTIVEHIGH 0x1
#define EXT_GATE_IN_ACTIVELOW 0x2
#define EXT_TRIG_IN_RISING 0x3
#define EXT_TRIG_IN_FALLING 0x4
#define EXT_RO_TRIG_IN_RISING 0x5
#define EXT_RO_TRIG_IN_FALLING 0x6
#define EXT_GATE_OUT_ACTIVEHIGH 0x7
#define EXT_GATE_OUT_ACTIVELOW 0x8
#define EXT_TRIG_OUT_RISING 0x9
#define EXT_TRIG_OUT_FALLING 0xA
#define EXT_RO_TRIG_OUT_RISING 0xB
#define EXT_RO_TRIG_OUT_FALLING 0xC
/* for temperature register */
#define T1_CLK_BIT 0x00000001
#define T1_CS_BIT 0x00000002
#define T2_CLK_BIT 0x00000004
#define T2_CS_BIT 0x00000008
/* fifo control register */
//#define FIFO_RESET_BIT 0x00000001
//#define FIFO_DISABLE_TOGGLE_BIT 0x00000002
//chip shiftin register meaning
#define OUTMUX_OFF 20
#define OUTMUX_MASK 0x1f
#define PROBES_OFF 4
#define PROBES_MASK 0x7f
#define OUTBUF_OFF 0
#define OUTBUF_MASK 1
/* multi purpose register */
#define PHASE_STEP_BIT 0x00000001
#define PHASE_STEP_OFFSET 0
// #define xxx_BIT 0x00000002
#define RESET_COUNTER_BIT 0x00000004
#define RESET_COUNTER_OFFSET 2
//#define xxx_BIT 0x00000008
//#define xxx_BIT 0x00000010
#define SW1_BIT 0x00000020
#define SW1_OFFSET 5
#define WRITE_BACK_BIT 0x00000040
#define WRITE_BACK_OFFSET 6
#define RESET_BIT 0x00000080
#define RESET_OFFSET 7
#define ENET_RESETN_BIT 0x00000800
#define ENET_RESETN_OFFSET 11
#define INT_RSTN_BIT 0x00002000
#define INT_RSTN_OFFSET 13
#define DIGITAL_TEST_BIT 0x00004000
#define DIGITAL_TEST_OFFSET 14
//#define CHANGE_AT_POWER_ON_BIT 0x00008000
//#define CHANGE_AT_POWER_ON_OFFSET 15
/* settings/conf gain register */
#define GAIN_MASK 0x0000000f
#define GAIN_OFFSET 0
#define SETTINGS_MASK 0x000000f0
#define SETTINGS_OFFSET 4
/* CHIP_OF_INTRST_REG */
#define CHANNEL_MASK 0xffff0000
#define CHANNEL_OFFSET 16
#define ACTIVE_ADC_MASK 0x0000001f
/**ADC SYNC CLEAN FIFO*/
#define ADCSYNC_CLEAN_FIFO_BITS 0x300000
#define CLEAN_FIFO_MASK 0x0fffff
enum {run_clk_c, adc_clk_c, sync_clk_c, dbit_clk_c};
#define PLL_CNTR_ADDR_OFF 16 //PLL_CNTR_REG bits 21 downto 16 represent the counter address
#define PLL_CNTR_RECONFIG_RESET_BIT 0
#define PLL_CNTR_READ_BIT 1
#define PLL_CNTR_WRITE_BIT 2
#define PLL_CNTR_PLL_RESET_BIT 3
#define PLL_CNTR_PHASE_EN_BIT 8
#define PLL_CNTR_UPDN_BIT 9
#define PLL_CNTR_CNTSEL_OFF 10
#define PLL_MODE_REG 0x0
#define PLL_STATUS_REG 0x1
#define PLL_START_REG 0x2
#define PLL_N_COUNTER_REG 0x3
#define PLL_M_COUNTER_REG 0x4
#define PLL_C_COUNTER_REG 0x5 //which ccounter stands in param 22:18; 7:0 lowcount 15:8 highcount; 16 bypassenable; 17 oddivision
#define PLL_PHASE_SHIFT_REG 0x6 // which ccounter stands in param 16:20; 21 updown (1 up, 0 down)
#define PLL_K_COUNTER_REG 0x7
#define PLL_BANDWIDTH_REG 0x8
#define PLL_CHARGEPUMP_REG 0x9
#define PLL_VCO_DIV_REG 0x1c
#define PLL_MIF_REG 0x1f
#define PPL_M_CNT_PARAM_DEFAULT 0x4040
#define PPL_N_CNT_PARAM_DEFAULT 0x20D0C
#define PPL_C0_CNT_PARAM_DEFAULT 0x20D0C
#define PPL_C1_CNT_PARAM_DEFAULT 0xA0A0
#define PPL_C2_CNT_PARAM_DEFAULT 0x20D0C
#define PPL_C3_CNT_PARAM_DEFAULT 0x0808
#define PPL_BW_PARAM_DEFAULT 0x2EE0
#define PPL_VCO_PARAM_DEFAULT 0x1
#define NEW_PLL_RECONFIG
#ifdef NEW_PLL_RECONFIG
#define PLL_VCO_FREQ_MHZ 400//480//800
#else
#define PLL_VCO_FREQ_MHZ 480//800
#endif
/*
GBE parameter and control registers definitions
*/
#define GBE_CTRL_WSTROBE 0
#define GBE_CTRL_VAR_OFFSET 16
#define GBE_CTRL_VAR_MASK 0XF
#define GBE_CTRL_RAMADDR_OFFSET 24
#define GBE_CTRL_RAMADDR_MASK 0X3F
#define GBE_CTRL_INTERFACE 23
#define RX_UDP_IP_ADDR 0
#define RX_UDP_PORTS_ADDR 1
#define RX_UDP_MAC_L_ADDR 2
#define RX_UDP_MAC_H_ADDR 3
#define IPCHECKSUM_ADDR 4
#define GBE_DELAY_ADDR 5
#define GBE_RESERVED1_ADDR 6
#define GBE_RESERVED2_ADDR 7
#define DETECTOR_MAC_L_ADDR 8
#define DETECTOR_MAC_H_ADDR 9
#define DETECTOR_IP_ADDR 10
/**------------------
-- pattern registers definitions
--------------------------------------------- */
#define IOSIGNALS_MASK 0xfffffffffffff
#define ADC_ENABLE_BIT 63
#define APATTERN_MASK 0xffff
#define ASTART_OFFSET 0
#define ASTOP_OFFSET 16
#define PATTERN_CTRL_WRITE_BIT 0
#define PATTERN_CTRL_READ_BIT 1
#define PATTERN_CTRL_ADDR_OFFSET 16
#define MAX_PATTERN_LENGTH 1024
#endif

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slsDetectorServers/jctbDetectorServer/server.c
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/* A simple server in the internet domain using TCP
The port number is passed as an argument */
#include "sls_detector_defs.h"
#include <stdlib.h>
#include "communication_funcs.h"
#include "server_funcs.h"
#include <string.h>
extern int sockfd;
extern int phase_shift;
void error(char *msg)
{
perror(msg);
}
int main(int argc, char *argv[])
{
int portno, b;
char cmd[500];
int retval=OK;
int sd, fd;
int iarg;
int checkType = 1;
for(iarg=1; iarg<argc; iarg++){
if(!strcasecmp(argv[iarg],"-phaseshift")){
if(argc==iarg+1){
printf("No phaseshift given. Exiting.\n");
return 1;
}
if ( sscanf(argv[iarg+1],"%d",&phase_shift)==0) {
printf("could not decode phase shift\n");
return 1;
}
}
else if(!strcasecmp(argv[iarg],"-test")){
if(argc==iarg+1){
printf("No test condition given. Exiting.\n");
return 1;
}
if(!strcasecmp(argv[iarg+1],"with_gotthard")){
checkType = 0;
}else{
printf("could not decode test condition. Possible arguments: with_gotthard. Exiting\n");
return 1;
}
}
}
//stop server
if ((argc > 2) && (!strcasecmp(argv[2],"stopserver"))){
portno = DEFAULT_PORTNO+1;
if ( sscanf(argv[1],"%d",&portno) ==0) {
printf("could not open stop server: unknown port\n");
return 1;
}
b=0;
printf("\n\nStop Server\nOpening stop server on port %d\n",portno);
checkType=0;
}
//control server
else {
portno = DEFAULT_PORTNO;
if(checkType)
sprintf(cmd,"%s %d stopserver &",argv[0],DEFAULT_PORTNO+1);
else
sprintf(cmd,"%s %d stopserver -test with_gotthard &",argv[0],DEFAULT_PORTNO+1);
printf("\n\nControl Server\nOpening control server on port %d\n",portno );
//printf("\n\ncmd:%s\n",cmd);
system(cmd);
b=1;
checkType=1;
}
init_detector(b, checkType);
sd=bindSocket(portno);
sockfd=sd;
if (getServerError(sd)) {
printf("server error!\n");
return -1;
}
/* assign function table */
function_table();
#ifdef VERBOSE
printf("function table assigned \n");
#endif
/* waits for connection */
while(retval!=GOODBYE) {
#ifdef VERBOSE
printf("\n");
#endif
#ifdef VERY_VERBOSE
printf("Waiting for client call\n");
#endif
fd=acceptConnection(sockfd);
#ifdef VERY_VERBOSE
printf("Conenction accepted\n");
#endif
retval=decode_function(fd);
#ifdef VERY_VERBOSE
printf("function executed\n");
#endif
closeConnection(fd);
#ifdef VERY_VERBOSE
printf("connection closed\n");
#endif
}
exitServer(sockfd);
printf("Goodbye!\n");
return 0;
}

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slsDetectorServers/jctbDetectorServer/server_defs.h
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#ifndef SERVER_DEFS_H
#define SERVER_DEFS_H
#include "sls_detector_defs.h"
#include <stdint.h>
// Hardware definitions
#define NCHAN 36
#define NCHIP 1
#define NADC 9 //
/* #ifdef CTB */
/* #define NDAC 24 */
/* #define NPWR 5 */
/* #else */
/* #define NDAC 16 */
/* #define NPWR 0 */
/* #endif */
#define DAC_CMD_OFF 20
#define NMAXMODX 1
#define NMAXMODY 1
#define NMAXMOD (NMAXMODX*NMAXMODY)
#define NCHANS (NCHAN*NCHIP*NMAXMOD)
#define NDACS (NDAC*NMAXMOD)
/**when moench readout tested with gotthard module*/
#define TRIM_DR (((int)pow(2,NTRIMBITS))-1)
#define COUNT_DR (((int)pow(2,NCOUNTBITS))-1)
#define ALLMOD 0xffff
#define ALLFIFO 0xffff
#define GOTTHARD_ADCSYNC_VAL 0x32214
#define ADCSYNC_VAL 0x02111
#define TOKEN_RESTART_DELAY 0x88000000
#define TOKEN_RESTART_DELAY_ROI 0x1b000000
#define TOKEN_TIMING_REV1 0x1f16
#define TOKEN_TIMING_REV2 0x1f0f
#define DEFAULT_PHASE_SHIFT 0 // 120
#define DEFAULT_IP_PACKETSIZE 0x0522
#define DEFAULT_UDP_PACKETSIZE 0x050E
#define ADC1_IP_PACKETSIZE 256*2+14+20
#define ADC1_UDP_PACKETSIZE 256*2+4+8+2
#ifdef VIRTUAL
#define DEBUGOUT
#endif
#define CLK_FREQ 156.25E+6
#define ADC_CLK_FREQ 32E+6
#endif

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slsDetectorServers/jctbDetectorServer/server_funcs.c
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102
slsDetectorServers/jctbDetectorServer/server_funcs.h
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#ifndef SERVER_FUNCS_H
#define SERVER_FUNCS_H
#include "sls_detector_defs.h"
#include <stdio.h>
/*
#include <sys/types.h>
#include <sys/socket.h>
#include <netinet/in.h>
*/
#include "communication_funcs.h"
#define GOODBYE -200
int sockfd;
int function_table();
int decode_function(int);
const char* getFunctionName(enum detFuncs func);
int init_detector(int,int);
int M_nofunc(int);
int exit_server(int);
// General purpose functions
int get_detector_type(int);
int set_number_of_modules(int);
int get_max_number_of_modules(int);
int exec_command(int);
int set_external_signal_flag(int);
int set_external_communication_mode(int);
int get_id(int);
int digital_test(int);
int write_register(int);
int read_register(int);
int set_dac(int);
int get_adc(int);
int set_channel(int);
int set_chip(int);
int set_module(int);
int get_channel(int);
int get_chip(int);
int get_module(int);
int get_threshold_energy(int);
int set_threshold_energy(int);
int set_settings(int);
int start_acquisition(int);
int stop_acquisition(int);
int start_readout(int);
int get_run_status(int);
int read_frame(int);
int read_all(int);
int start_and_read_all(int);
int set_timer(int);
int get_time_left(int);
int set_dynamic_range(int);
int set_roi(int);
int get_roi(int);
int set_speed(int);
int set_readout_flags(int);
int execute_trimming(int);
int lock_server(int);
int set_port(int);
int get_last_client_ip(int);
int set_master(int);
int set_synchronization(int);
int update_client(int);
int send_update(int);
int configure_mac(int);
int load_image(int);
int read_counter_block(int);
int reset_counter_block(int);
int calibrate_pedestal(int);
int set_roi(int);
int set_ctb_pattern(int);
int write_adc_register(int);
int power_chip(int);
int reset_fpga(int);
int program_fpga(int);
int activate(int);
int prepare_acquisition(int);
int cleanup_acquisition(int);
#endif

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slsDetectorServers/jctbDetectorServer/sharedmemory.c
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#include "sharedmemory.h"
struct statusdata *stdata;
int inism(int clsv) {
static int scansmid;
if (clsv==SMSV) {
if ( (scansmid=shmget(SMKEY,1024,IPC_CREAT | 0666 ))==-1 ) {
return -1;
}
if ( (stdata=shmat(scansmid,NULL,0))==(void*)-1) {
return -2;
}
}
if (clsv==SMCL) {
if ( (scansmid=shmget(SMKEY,0,0) )==-1 ) {
return -3;
}
if ( (stdata=shmat(scansmid,NULL,0))==(void*)-1) {
return -4;
}
}
return 1;
}
void write_status_sm(char *status) {
strcpy(stdata->status,status);
}
void write_stop_sm(int v) {
stdata->stop=v;
}
void write_runnumber_sm(int v) {
stdata->runnumber=v;
}

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slsDetectorServers/jctbDetectorServer/sharedmemory.h
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#ifndef SM
#define SM
#include "sls_detector_defs.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <stdarg.h>
#include <unistd.h>
//#include <asm/page.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdarg.h>
#include <unistd.h>
#include <sys/shm.h>
#include <sys/ipc.h>
#include <sys/stat.h>
/* key for shared memory */
#define SMKEY 10001
#define SMSV 1
#define SMCL 2
struct statusdata {
int runnumber;
int stop;
char status[20];
} ;
/* for shared memory */
int inism(int clsv);
void write_status_sm(char *status);
void write_stop_sm(int v);
void write_runnumber_sm(int v);
#endif

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slsDetectorServers/jctbDetectorServer/slow_adc.c
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#include "firmware_funcs.h"
#include "registers_m.h"
#include "server_defs.h"
#include "blackfin.h"
int prepareSlowADCSeq() {
// u_int16_t vv=0x3c40;
u_int16_t codata=( 1<<13) | (7<<10) | (7<<7) | (1<<6) | (0<<3) | (2<<1) | 1;
u_int32_t valw;
int obit, ibit;
// int cnv_bit=16, sdi_bit=17, sck_bit=18;
int cnv_bit=10, sdi_bit=8, sck_bit=9;
// int oval=0;
printf("Codata is %04x\n",codata);
/* //convert */
valw=(1<<cnv_bit);
bus_w(ADC_WRITE_REG,valw);
usleep(20);
valw=0;
bus_w(ADC_WRITE_REG,(valw));
usleep(20);
for (ibit=0; ibit<14; ibit++) {
obit=((codata >> (13-ibit)) & 1);
// printf("%d",obit);
valw = obit << sdi_bit;
bus_w(ADC_WRITE_REG,valw);
usleep(20);
bus_w(ADC_WRITE_REG,valw|(1<<sck_bit));
usleep(20);
bus_w(ADC_WRITE_REG,valw);
}
// printf("\n");
bus_w(ADC_WRITE_REG,0);
/* //convert */
valw=(1<<cnv_bit);
bus_w(ADC_WRITE_REG,valw);
usleep(20);
valw=0;
bus_w(ADC_WRITE_REG,(valw));
usleep(20);
return 0;
}
int prepareSlowADC(int ichan) {
// u_int16_t vv=0x3c40;
// u_int16_t codata=( 1<<13) | (7<<10) | (7<<7) | (1<<6) | (0<<3) | (2<<1) | 1;
u_int16_t codata=(1<<13) | (7<<10) | (ichan<<7) | (1<<6) | (0<<3) | (0<<1) | 1; //read single channel
if (ichan<0) codata=( 1<<13) | (3<<10) | (7<7) | (1<<6) | (0<<3) | (0<<1) | 1;
u_int32_t valw;
int obit, ibit;
// int cnv_bit=16, sdi_bit=17, sck_bit=18;
int cnv_bit=10, sdi_bit=8, sck_bit=9;
// int oval=0;
printf("Codata is %04x\n",codata);
/* //convert */
valw=(1<<cnv_bit);
bus_w(ADC_WRITE_REG,valw);
usleep(20);
valw=0;
bus_w(ADC_WRITE_REG,(valw));
usleep(20);
for (ibit=0; ibit<14; ibit++) {
obit=((codata >> (13-ibit)) & 1);
// printf("%d",obit);
valw = obit << sdi_bit;
bus_w(ADC_WRITE_REG,valw);
usleep(20);
bus_w(ADC_WRITE_REG,valw|(1<<sck_bit));
usleep(20);
bus_w(ADC_WRITE_REG,valw);
}
// printf("\n");
bus_w(ADC_WRITE_REG,0);
/* //convert */
valw=(1<<cnv_bit);
bus_w(ADC_WRITE_REG,valw);
usleep(20);
valw=0;
bus_w(ADC_WRITE_REG,(valw));
usleep(20);
return 0;
}
int readSlowADC(int ichan) {
// u_int16_t vv=0x3c40;
// u_int16_t codata=( 1<<13) | (7<<10) | (ichan<<7) | (1<<6) | (0<<3) | (0<<1) | 1; //read single channel
u_int32_t valw;
int i, obit;
// int cnv_bit=16, sdi_bit=17, sck_bit=18;
int cnv_bit=10, sdi_bit=8, sck_bit=9;
int oval=0;
printf("DAC index is %d\n",ichan);
if (ichan<-1 || ichan>7)
return -1;
prepareSlowADC(ichan);
/* printf("Codata is %04x\n",codata); */
/* /\* //convert *\/ */
/* valw=(1<<cnv_bit); */
/* bus_w(ADC_WRITE_REG,valw); */
/* usleep(20); */
/* valw=0; */
/* bus_w(ADC_WRITE_REG,(valw)); */
/* usleep(20); */
/* for (ibit=0; ibit<14; ibit++) { */
/* obit=((codata >> (13-ibit)) & 1); */
/* // printf("%d",obit); */
/* valw = obit << sdi_bit; */
/* bus_w(ADC_WRITE_REG,valw); */
/* usleep(20); */
/* bus_w(ADC_WRITE_REG,valw|(1<<sck_bit)); */
/* usleep(20); */
/* bus_w(ADC_WRITE_REG,valw); */
/* } */
/* // printf("\n"); */
/* bus_w(ADC_WRITE_REG,0); */
for (ichan=0; ichan<9; ichan++) {
/* //convert */
valw=(1<<cnv_bit);
bus_w(ADC_WRITE_REG,valw);
usleep(20);
valw=0;
bus_w(ADC_WRITE_REG,(valw));
usleep(20);
// printf("Channel %d ",ichan);
//read
oval=0;
for (i=0;i<16;i++) {
obit=bus_r16(SLOW_ADC_REG)&0x1;
// printf("%d",obit);
//write data (i)
// usleep(0);
oval|=obit<<(15-i);
//cldwn
valw=0;
bus_w(ADC_WRITE_REG,valw);
bus_w(ADC_WRITE_REG,valw|(1<<sck_bit));
usleep(20);
bus_w(ADC_WRITE_REG,valw);
usleep(20);
}
printf("\t");
printf("Value %d is %d (%d mV)\n",ichan, oval,2500*oval/65535);
}
printf("Value %d is %d\n",ichan, oval);
return 2500*oval/65535;
}

10
slsDetectorServers/jctbDetectorServer/slow_adc.h
View File

@ -1,10 +0,0 @@
#ifndef SLOW_ADC_H
#define SLOW_ADC_H
int prepareSlowADCSeq();
int prepareSlowADC(int ichan);
int readSlowADC(int ichan);
#endif

1
slsDetectorServers/jctbDetectorServer/sls_detector_defs.h
View File

@ -1 +0,0 @@
../commonFiles/sls_detector_defs.h

1
slsDetectorServers/jctbDetectorServer/sls_detector_funcs.h
View File

@ -1 +0,0 @@
../commonFiles/sls_detector_funcs.h

1
slsDetectorServers/jctbDetectorServer/sls_receiver_defs.h
View File

@ -1 +0,0 @@
../../slsReceiverSoftware/include/sls_receiver_defs.h

1
slsDetectorServers/jctbDetectorServer/sls_receiver_funcs.h
View File

@ -1 +0,0 @@
../../slsReceiverSoftware/include/sls_receiver_funcs.h

46
slsDetectorServers/jctbDetectorServer/stop_server.c
View File

@ -1,46 +0,0 @@
/* A simple server in the internet domain using TCP
The port number is passed as an argument */
#include "sls_detector_defs.h"
#include "communication_funcs.h"
#include "firmware_funcs.h"
int sockfd;
int main(int argc, char *argv[])
{
int portno;
int retval=0;
portno = DEFAULT_PORTNO;
bindSocket(portno);
if (getServerError())
return -1;
/* waits for connection */
while(retval!=GOODBYE) {
#ifdef VERBOSE
printf("\n");
#endif
#ifdef VERY_VERBOSE
printf("Stop server: waiting for client call\n");
#endif
acceptConnection();
retval=stopStateMachine();
closeConnection();
}
exitServer();
printf("Goodbye!\n");
return 0;
}

2
slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h
View File

@ -364,7 +364,7 @@
#define SET_PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
#define SET_PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
/* Set Period 64 bit register */
/* Set Exptime 64 bit register */
#define SET_EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT)
#define SET_EXPTIME_MSB_REG (0x69 << MEM_MAP_SHIFT)

314
slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
View File

@ -407,7 +407,7 @@ void setupDetector() {
bus_w(DAQ_REG, 0x0); /* Only once at server startup */
FILE_LOG(logINFOBLUE, ("Setting Default parameters\n"));
setSpeed(HALF_SPEED);
setClockDivider(HALF_SPEED);
cleanFifos();
resetCore();
@ -424,7 +424,7 @@ void setupDetector() {
setTimer(DELAY_AFTER_TRIGGER, DEFAULT_DELAY);
setTimer(STORAGE_CELL_NUMBER, DEFAULT_NUM_STRG_CLLS);
selectStoragecellStart(DEFAULT_STRG_CLL_STRT);
/*setSpeed(HALF_SPEED); depends if all the previous stuff works*/
/*setClockDivider(HALF_SPEED); depends if all the previous stuff works*/
setTiming(DEFAULT_TIMING_MODE);
setHighVoltage(DEFAULT_HIGH_VOLTAGE);
@ -464,38 +464,6 @@ int setDefaultDacs() {
/* firmware functions (resets) */
int powerChip (int on){
if(on != -1){
if(on){
FILE_LOG(logINFO, ("Powering chip: on\n"));
bus_w(CHIP_POWER_REG, bus_r(CHIP_POWER_REG) | CHIP_POWER_ENABLE_MSK);
}
else{
FILE_LOG(logINFO, ("Powering chip: off\n"));
bus_w(CHIP_POWER_REG, bus_r(CHIP_POWER_REG) & ~CHIP_POWER_ENABLE_MSK);
}
}
return ((bus_r(CHIP_POWER_REG) & CHIP_POWER_STATUS_MSK) >> CHIP_POWER_STATUS_OFST);
}
int autoCompDisable(int on) {
if(on != -1){
if(on){
FILE_LOG(logINFO, ("Auto comp disable mode: on\n"));
bus_w(VREF_COMP_MOD_REG, bus_r(VREF_COMP_MOD_REG) | VREF_COMP_MOD_ENABLE_MSK);
}
else{
FILE_LOG(logINFO, ("Auto comp disable mode: off\n"));
bus_w(VREF_COMP_MOD_REG, bus_r(VREF_COMP_MOD_REG) & ~VREF_COMP_MOD_ENABLE_MSK);
}
}
return (bus_r(VREF_COMP_MOD_REG) & VREF_COMP_MOD_ENABLE_MSK);
}
void cleanFifos() {
#ifdef VIRTUAL
@ -524,33 +492,6 @@ void resetPeripheral() {
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_PERIPHERAL_RST_MSK);
}
int adcPhase(int st){ /**carlos needed clkphase 1 and 2? cehck with Aldo */
FILE_LOG(logINFO, ("Setting ADC Phase to %d\n", st));
if (st > 65535 || st < -65535)
return clkPhase[0];
clkPhase[1] = st - clkPhase[0];
if (clkPhase[1] == 0)
return clkPhase[0];
configurePll();
clkPhase[0] = st;
return clkPhase[0];
}
int getPhase() {
return clkPhase[0];
}
void configureASICTimer() {
FILE_LOG(logINFO, ("Configuring ASIC Timer\n"));
bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_PRCHRG_TMR_MSK) | ASIC_CTRL_PRCHRG_TMR_VAL);
bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_DS_TMR_MSK) | ASIC_CTRL_DS_TMR_VAL);
}
@ -566,91 +507,29 @@ int setDynamicRange(int dr){
/* parameters - readout */
/* parameters - speed, readout */
enum speedVariable setSpeed(int val) {
// setting
if(val >= 0) {
// stop state machine if running
if(runBusy())
stopStateMachine();
uint32_t txndelay_msk = 0;
switch(val){
// todo in firmware, for now setting half speed
case FULL_SPEED://40
FILE_LOG(logINFO, ("Setting Half Speed (20 MHz):\n"));
FILE_LOG(logINFO, ("\tSetting Sample Reg to 0x%x\n", SAMPLE_ADC_HALF_SPEED));
bus_w(SAMPLE_REG, SAMPLE_ADC_HALF_SPEED);
txndelay_msk = (bus_r(CONFIG_REG) & CONFIG_TDMA_TIMESLOT_MSK); // read config tdma timeslot value
FILE_LOG(logINFO, ("\tSetting Config Reg to 0x%x\n", CONFIG_HALF_SPEED | txndelay_msk));
bus_w(CONFIG_REG, CONFIG_HALF_SPEED | txndelay_msk);
FILE_LOG(logINFO, ("\tSetting ADC Ofst Reg to 0x%x\n", ADC_OFST_HALF_SPEED_VAL));
bus_w(ADC_OFST_REG, ADC_OFST_HALF_SPEED_VAL);
FILE_LOG(logINFO, ("\tSetting ADC Phase Reg to 0x%x\n", ADC_PHASE_HALF_SPEED));
adcPhase(ADC_PHASE_HALF_SPEED);
break;
case HALF_SPEED:
FILE_LOG(logINFO, ("Setting Half Speed (20 MHz):\n"));
FILE_LOG(logINFO, ("\tSetting Sample Reg to 0x%x\n", SAMPLE_ADC_HALF_SPEED));
bus_w(SAMPLE_REG, SAMPLE_ADC_HALF_SPEED);
txndelay_msk = (bus_r(CONFIG_REG) & CONFIG_TDMA_TIMESLOT_MSK); // read config tdma timeslot value
FILE_LOG(logINFO, ("\tSetting Config Reg to 0x%x\n", CONFIG_HALF_SPEED | txndelay_msk));
bus_w(CONFIG_REG, CONFIG_HALF_SPEED | txndelay_msk);
FILE_LOG(logINFO, ("\tSetting ADC Ofst Reg to 0x%x\n", ADC_OFST_HALF_SPEED_VAL));
bus_w(ADC_OFST_REG, ADC_OFST_HALF_SPEED_VAL);
FILE_LOG(logINFO, ("\tSetting ADC Phase Reg to 0x%x\n", ADC_PHASE_HALF_SPEED));
adcPhase(ADC_PHASE_HALF_SPEED);
break;
case QUARTER_SPEED:
FILE_LOG(logINFO, ("Setting Half Speed (10 MHz):\n"));
FILE_LOG(logINFO, ("\tSetting Sample Reg to 0x%x\n", SAMPLE_ADC_QUARTER_SPEED));
bus_w(SAMPLE_REG, SAMPLE_ADC_QUARTER_SPEED);
txndelay_msk = (bus_r(CONFIG_REG) & CONFIG_TDMA_TIMESLOT_MSK); // read config tdma timeslot value
FILE_LOG(logINFO, ("\tSetting Config Reg to 0x%x\n", CONFIG_QUARTER_SPEED | txndelay_msk));
bus_w(CONFIG_REG, CONFIG_QUARTER_SPEED | txndelay_msk);
FILE_LOG(logINFO, ("\tSetting ADC Ofst Reg to 0x%x\n", ADC_OFST_QUARTER_SPEED_VAL));
bus_w(ADC_OFST_REG, ADC_OFST_QUARTER_SPEED_VAL);
FILE_LOG(logINFO, ("\tSetting ADC Phase Reg to 0x%x\n", ADC_PHASE_QUARTER_SPEED));
adcPhase(ADC_PHASE_QUARTER_SPEED);
break;
}
}
//getting
u_int32_t speed = bus_r(CONFIG_REG) & CONFIG_READOUT_SPEED_MSK;
switch(speed){
case CONFIG_FULL_SPEED_40MHZ_VAL:
return FULL_SPEED;
case CONFIG_HALF_SPEED_20MHZ_VAL:
return HALF_SPEED;
case CONFIG_QUARTER_SPEED_10MHZ_VAL:
return QUARTER_SPEED;
default:
return -1;
}
void setSpeed(enum speedVariable ind, int val) {
switch(ind) {
case CLOCK_DIVIDER:
setClockDivider(val);
case ADC_PHASE:
setAdcPhase(val);
default:
return;
}
}
int getSpeed(enum speedVariable ind) {
switch(ind) {
case CLOCK_DIVIDER:
return getClockDivider();
case ADC_PHASE:
return getPhase();
default:
return -1;
}
}
@ -1292,10 +1171,149 @@ int setDetectorPosition(int pos[]) {
/* jungfrau specific - pll, flashing fpga */
/* jungfrau specific - powerchip, autocompdisable, asictimer, clockdiv, pll, flashing fpga */
int powerChip (int on){
if(on != -1){
if(on){
FILE_LOG(logINFO, ("Powering chip: on\n"));
bus_w(CHIP_POWER_REG, bus_r(CHIP_POWER_REG) | CHIP_POWER_ENABLE_MSK);
}
else{
FILE_LOG(logINFO, ("Powering chip: off\n"));
bus_w(CHIP_POWER_REG, bus_r(CHIP_POWER_REG) & ~CHIP_POWER_ENABLE_MSK);
}
}
return ((bus_r(CHIP_POWER_REG) & CHIP_POWER_STATUS_MSK) >> CHIP_POWER_STATUS_OFST);
}
int autoCompDisable(int on) {
if(on != -1){
if(on){
FILE_LOG(logINFO, ("Auto comp disable mode: on\n"));
bus_w(VREF_COMP_MOD_REG, bus_r(VREF_COMP_MOD_REG) | VREF_COMP_MOD_ENABLE_MSK);
}
else{
FILE_LOG(logINFO, ("Auto comp disable mode: off\n"));
bus_w(VREF_COMP_MOD_REG, bus_r(VREF_COMP_MOD_REG) & ~VREF_COMP_MOD_ENABLE_MSK);
}
}
return (bus_r(VREF_COMP_MOD_REG) & VREF_COMP_MOD_ENABLE_MSK);
}
void configureASICTimer() {
FILE_LOG(logINFO, ("Configuring ASIC Timer\n"));
bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_PRCHRG_TMR_MSK) | ASIC_CTRL_PRCHRG_TMR_VAL);
bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_DS_TMR_MSK) | ASIC_CTRL_DS_TMR_VAL);
}
int setClockDivider(int val) {
// setting
if(val >= 0) {
// stop state machine if running
if(runBusy())
stopStateMachine();
uint32_t txndelay_msk = 0;
switch(val){
// todo in firmware, for now setting half speed
case FULL_SPEED://40
FILE_LOG(logINFO, ("Setting Half Speed (20 MHz):\n"));
FILE_LOG(logINFO, ("\tSetting Sample Reg to 0x%x\n", SAMPLE_ADC_HALF_SPEED));
bus_w(SAMPLE_REG, SAMPLE_ADC_HALF_SPEED);
txndelay_msk = (bus_r(CONFIG_REG) & CONFIG_TDMA_TIMESLOT_MSK); // read config tdma timeslot value
FILE_LOG(logINFO, ("\tSetting Config Reg to 0x%x\n", CONFIG_HALF_SPEED | txndelay_msk));
bus_w(CONFIG_REG, CONFIG_HALF_SPEED | txndelay_msk);
FILE_LOG(logINFO, ("\tSetting ADC Ofst Reg to 0x%x\n", ADC_OFST_HALF_SPEED_VAL));
bus_w(ADC_OFST_REG, ADC_OFST_HALF_SPEED_VAL);
FILE_LOG(logINFO, ("\tSetting ADC Phase Reg to 0x%x\n", ADC_PHASE_HALF_SPEED));
setAdcPhase(ADC_PHASE_HALF_SPEED);
break;
case HALF_SPEED:
FILE_LOG(logINFO, ("Setting Half Speed (20 MHz):\n"));
FILE_LOG(logINFO, ("\tSetting Sample Reg to 0x%x\n", SAMPLE_ADC_HALF_SPEED));
bus_w(SAMPLE_REG, SAMPLE_ADC_HALF_SPEED);
txndelay_msk = (bus_r(CONFIG_REG) & CONFIG_TDMA_TIMESLOT_MSK); // read config tdma timeslot value
FILE_LOG(logINFO, ("\tSetting Config Reg to 0x%x\n", CONFIG_HALF_SPEED | txndelay_msk));
bus_w(CONFIG_REG, CONFIG_HALF_SPEED | txndelay_msk);
FILE_LOG(logINFO, ("\tSetting ADC Ofst Reg to 0x%x\n", ADC_OFST_HALF_SPEED_VAL));
bus_w(ADC_OFST_REG, ADC_OFST_HALF_SPEED_VAL);
FILE_LOG(logINFO, ("\tSetting ADC Phase Reg to 0x%x\n", ADC_PHASE_HALF_SPEED));
setAdcPhase(ADC_PHASE_HALF_SPEED);
break;
case QUARTER_SPEED:
FILE_LOG(logINFO, ("Setting Half Speed (10 MHz):\n"));
FILE_LOG(logINFO, ("\tSetting Sample Reg to 0x%x\n", SAMPLE_ADC_QUARTER_SPEED));
bus_w(SAMPLE_REG, SAMPLE_ADC_QUARTER_SPEED);
txndelay_msk = (bus_r(CONFIG_REG) & CONFIG_TDMA_TIMESLOT_MSK); // read config tdma timeslot value
FILE_LOG(logINFO, ("\tSetting Config Reg to 0x%x\n", CONFIG_QUARTER_SPEED | txndelay_msk));
bus_w(CONFIG_REG, CONFIG_QUARTER_SPEED | txndelay_msk);
FILE_LOG(logINFO, ("\tSetting ADC Ofst Reg to 0x%x\n", ADC_OFST_QUARTER_SPEED_VAL));
bus_w(ADC_OFST_REG, ADC_OFST_QUARTER_SPEED_VAL);
FILE_LOG(logINFO, ("\tSetting ADC Phase Reg to 0x%x\n", ADC_PHASE_QUARTER_SPEED));
setAdcPhase(ADC_PHASE_QUARTER_SPEED);
break;
}
}
}
int getClockDivider() {
u_int32_t speed = bus_r(CONFIG_REG) & CONFIG_READOUT_SPEED_MSK;
switch(speed){
case CONFIG_FULL_SPEED_40MHZ_VAL:
return FULL_SPEED;
case CONFIG_HALF_SPEED_20MHZ_VAL:
return HALF_SPEED;
case CONFIG_QUARTER_SPEED_10MHZ_VAL:
return QUARTER_SPEED;
default:
return -1;
}
}
int setAdcPhase(int st){ /**carlos needed clkphase 1 and 2? cehck with Aldo */
FILE_LOG(logINFO, ("Setting ADC Phase to %d\n", st));
if (st > 65535 || st < -65535)
return clkPhase[0];
clkPhase[1] = st - clkPhase[0];
if (clkPhase[1] == 0)
return clkPhase[0];
configurePll();
clkPhase[0] = st;
return clkPhase[0];
}
int getPhase() {
return clkPhase[0];
}
void resetPLL() {
#ifdef VIRTUAL
return;
@ -1530,8 +1548,8 @@ enum runStatus getRunStatus(){
FILE_LOG(logINFO, ("Status Register: %08x\n",retval));
//running
if(((retval & RUN_BUSY_MSK) >> RUN_BUSY_OFST)) {
if ((retval & WAITING_FOR_TRIGGER_MSK) >> WAITING_FOR_TRIGGER_OFST) {
if (retval & RUN_BUSY_MSK) {
if (retval & WAITING_FOR_TRIGGER_MSK) {
FILE_LOG(logINFOBLUE, ("Status: WAITING\n"));
s = WAITING;
}
@ -1543,10 +1561,10 @@ enum runStatus getRunStatus(){
//not running
else {
if ((retval & STOPPED_MSK) >> STOPPED_OFST) {
if (retval & STOPPED_MSK) {
FILE_LOG(logINFOBLUE, ("Status: STOPPED\n"));
s = STOPPED;
} else if ((retval & RUNMACHINE_BUSY_MSK) >> RUNMACHINE_BUSY_OFST) {
} else if (retval & RUNMACHINE_BUSY_MSK) {
FILE_LOG(logINFOBLUE, ("Status: READ MACHINE BUSY\n"));
s = TRANSMITTING;
} else if (!retval) {

7
slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h
View File

@ -46,8 +46,8 @@ enum NETWORKINDEX { TXN_FRAME };
#define NDAC (8)
#define NDAC_OLDBOARD (16)
#define DYNAMIC_RANGE (16)
#define NUM_BITS_PER_PIXEL (DYNAMIC_RANGE / 8)
#define DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
#define DATA_BYTES (NCHIP * NCHAN * NUM_BYTES_PER_PIXEL)
#define IP_PACKETSIZE (0x2052)
#define CLK_RUN (40) /* MHz */
#define CLK_SYNC (20) /* MHz */
@ -66,6 +66,9 @@ enum NETWORKINDEX { TXN_FRAME };
#define DEFAULT_NUM_STRG_CLLS (0)
#define DEFAULT_STRG_CLL_STRT (0xf)
#define MAX_DAC_VOLTAGE_VALUE (2500)
#define MAX_DAC_UNIT_VALUE (4096)
/* Defines in the Firmware */
#define FIX_PATT_VAL (0xACDC2014)
#define ADC_PORT_INVERT_VAL (0x453b2a9c)

94
slsDetectorServers/slsDetectorServer/AD7689.h Executable file
View File

@ -0,0 +1,94 @@
#pragma once
//#include "commonServerFunctions.h" // blackfin.h, ansi.h
/* AD7689 ADC DEFINES */
/** Read back CFG Register */
#define AD7689_CFG_RB_OFST (0)
#define AD7689_CFG_RB_MSK (0x00000001 << AD7689_CFG_RB_OFST)
/** Channel sequencer */
#define AD7689_CFG_SEQ_OFST (1)
#define AD7689_CFG_SEQ_MSK (0x00000003 << AD7689_CFG_SEQ_OFST)
#define AD7689_CFG_SEQ_DSBLE_VAL ((0x0 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_UPDTE_DRNG_SQNCE_VAL ((0x1 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_SCN_WTH_TMP_VAL ((0x2 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_SCN_WTHT_TMP_VAL ((0x3 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
/** Reference/ buffer selection */
#define AD7689_CFG_REF_OFST (3)
#define AD7689_CFG_REF_MSK (0x00000007 << AD7689_CFG_REF_OFST)
/** Internal reference. REF = 2.5V buffered output. Temperature sensor enabled. */
#define AD7689_CFG_REF_INT_2500MV_VAL ((0x0 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_OFST)
/** Internal reference. REF = 4.096V buffered output. Temperature sensor enabled. */
#define AD7689_CFG_REF_INT_4096MV_VAL ((0x1 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor enabled. Internal buffer disabled. */
#define AD7689_CFG_REF_EXT_TMP_VAL ((0x2 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor enabled. Internal buffer enabled. */
#define AD7689_CFG_REF_EXT_TMP_INTBUF_VAL ((0x3 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor disabled. Internal buffer disabled. */
#define AD7689_CFG_REF_EXT_VAL ((0x6 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor disabled. Internal buffer enabled. */
#define AD7689_CFG_REF_EXT_INTBUF_VAL ((0x7 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** bandwidth of low pass filter */
#define AD7689_CFG_BW_OFST (6)
#define AD7689_CFG_BW_MSK (0x00000001 << AD7689_CFG_REF_OFST)
#define AD7689_CFG_BW_ONE_FOURTH_VAL ((0x0 << AD7689_CFG_BW_OFST) & AD7689_CFG_BW_MSK)
#define AD7689_CFG_BW_FULL_VAL ((0x1 << AD7689_CFG_BW_OFST) & AD7689_CFG_BW_MSK)
/** input channel selection IN0 - IN7 */
#define AD7689_CFG_IN_OFST (7)
#define AD7689_CFG_IN_MSK (0x00000007 << AD7689_CFG_IN_OFST)
/** input channel configuration */
#define AD7689_CFG_INCC_OFST (10)
#define AD7689_CFG_INCC_MSK (0x00000007 << AD7689_CFG_INCC_OFST)
#define AD7689_CFG_INCC_BPLR_DFFRNTL_PRS_VAL ((0x0 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_BPLR_IN_COM_VAL ((0x2 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_TMP_VAL ((0x3 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_DFFRNTL_PRS_VAL ((0x4 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_IN_COM_VAL ((0x6 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_IN_GND_VAL ((0x7 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
/** configuration update */
#define AD7689_CFG_CFG_OFST (13)
#define AD7689_CFG_CFG_MSK (0x00000001 << AD7689_CFG_CFG_OFST)
#define AD7689_CFG_CFG_NO_UPDATE_VAL ((0x0 << AD7689_CFG_CFG_OFST) & AD7689_CFG_CFG_MSK)
#define AD7689_CFG_CFG_OVRWRTE_VAL ((0x1 << AD7689_CFG_CFG_OFST) & AD7689_CFG_CFG_MSK)
int getAD7689(int ind) {
}
void setAD7689(int addr, int val) {
u_int32_t codata;
codata = val + (addr << 8);
FILE_LOG(logINFO, ("\tSetting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr));
serializeToSPI(ADC_SPI_REG, codata, ADC_SERIAL_CS_OUT_MSK, AD9257_ADC_NUMBITS,
ADC_SERIAL_CLK_OUT_MSK, ADC_SERIAL_DATA_OUT_MSK, ADC_SERIAL_DATA_OUT_OFST);
}
void prepareAD7689(){
FILE_LOG(logINFOBLUE, ("Preparing AD7689 (Slow ADCs):\n"));
uint16_t codata = (
// read back
AD7689_CFG_RB_MSK |
// scan sequence IN0-IN7 then temperature sensor
AD7689_CFG_SEQ_SCN_WTH_TMP_VAL |
// Internal reference. REF = 2.5V buffered output. Temperature sensor enabled.
AD7689_CFG_REF_INT_2500MV_VAL |
// full bandwidth of low pass filter
AD7689_CFG_BW_FULL_VAL |
// scan upto channel 7
AD7689_CFG_IN_MSK |
// input channel configuration (unipolar. inx to gnd)
AD7689_CFG_INCC_UNPLR_IN_GND_VAL |
// overwrite configuration
AD7689_CFG_CFG_OVRWRTE_VAL);
}

7
slsDetectorServers/slsDetectorServer/AD9257.h
View File

@ -125,6 +125,13 @@
#define AD9257_VREF_1_6_VAL ((0x3 << AD9257_VREF_OFST) & AD9257_VREF_MSK)
#define AD9257_VREF_2_0_VAL ((0x4 << AD9257_VREF_OFST) & AD9257_VREF_MSK)
int getMaxValidVref() {
return 0x4;
}
void setVrefVoltage(int val) {
setAdc9257(AD9257_VREF_REG, val);
}
void setAdc9257(int addr, int val) {

136
slsDetectorServers/slsDetectorServer/I2C.h Executable file
View File

@ -0,0 +1,136 @@
#pragma once
#include "blackfin.h" /** I2C_CLOCK_MHZ should be defined */
#define I2C_DATA_RATE_KBPS (200)
#define I2C_SCL_PERIOD_NS ((1000 * 1000) / I2C_DATA_RATE_KBPS)
#define I2C_SCL_LOW_PERIOD_NS (I2C_SCL_PERIOD_NS / 2)
#define I2C_SDA_DATA_HOLD_TIME_NS (I2C_SCL_HIGH_PERIOD_NS / 2)
#define I2C_SCL_LOW_COUNT ((I2C_SCL_LOW_PERIOD_NS / 1000) * I2C_CLOCK_MHZ) // convert to us, then to clock (defined in blackfin.h)
#define I2C_SDA_DATA_HOLD_COUNT ((I2C_SDA_DATA_HOLD_TIME_NS / 1000) * I2C_CLOCK_MHZ) // convert to us, then to clock (defined in blackfin.h)
/** Control Register */
#define I2C_CTRL_ENBLE_CORE_OFST (0)
#define I2C_CTRL_ENBLE_CORE_MSK (0x00000001 << I2C_CTRL_ENBLE_CORE_OFST)
#define I2C_CTRL_BUS_SPEED_OFST (1)
#define I2C_CTRL_BUS_SPEED_MSK (0x00000001 << I2C_CTRL_BUS_SPEED_OFST)
#define I2C_CTRL_BUS_SPEED_STNDRD_100_VAL ((0x0 << I2C_CTRL_BUS_SPEED_OFST) & I2C_CTRL_BUS_SPEED_MSK) // standard mode (up to 100 kbps)
#define I2C_CTRL_BUS_SPEED_FAST_400_VAL ((0x1 << I2C_CTRL_BUS_SPEED_OFST) & I2C_CTRL_BUS_SPEED_MSK) // fast mode (up to 400 kbps)
/** if actual level of transfer command fifo <= thd level, TX_READY interrupt asserted */
#define I2C_CTRL_TFR_CMD_FIFO_THD_OFST (2)
#define I2C_CTRL_TFR_CMD_FIFO_THD_MSK (0x00000003 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST)
#define I2C_CTRL_TFR_CMD_EMPTY_VAL ((0x0 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_ONE_FOURTH_VAL ((0x1 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_ONE_HALF_VAL ((0x2 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_NOT_FULL_VAL ((0x3 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
/** if actual level of receive data fifo <= thd level, RX_READY interrupt asserted */
#define I2C_CTRL_RX_DATA_FIFO_THD_OFST (4)
#define I2C_CTRL_RX_DATA_FIFO_THD_MSK (0x00000003 << I2C_CTRL_RX_DATA_FIFO_THD_OFST)
#define I2C_CTRL_RX_DATA_1_VALID_ENTRY_VAL ((0x0 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_ONE_FOURTH_VAL ((0x1 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_ONE_HALF_VAL ((0x2 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_FULL_VAL ((0x3 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
/** Transfer Command Fifo register */
#define I2C_TFR_CMD_RW_OFST (0)
#define I2C_TFR_CMD_RW_MSK (0x00000001 << I2C_TFR_CMD_RW_OFST)
#define I2C_TFR_CMD_RW_WRITE_VAL ((0x0 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
#define I2C_TFR_CMD_RW_READ_VAL ((0x1 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
#define I2C_TFR_CMD_ADDR_OFST (1)
#define I2C_TFR_CMD_ADDR_MSK (0x0000007F << I2C_TFR_CMD_ADDR_OFST)
/** when writing, rw and addr converts to data to be written mask */
#define I2C_TFR_CMD_DATA_FR_WR_OFST (0)
#define I2C_TFR_CMD_DATA_FR_WR_MSK (0x000000FF << I2C_TFR_CMD_DATA_FR_WR_OFST)
#define I2C_TFR_CMD_STOP_OFST (8)
#define I2C_TFR_CMD_STOP_MSK (0x00000001 << I2C_TFR_CMD_ADDR_OFST)
#define I2C_TFR_CMD_RPTD_STRT_OFST (9)
#define I2C_TFR_CMD_RPTD_STRT_MSK (0x00000001 << I2C_TFR_CMD_RPTD_STRT_OFST)
/**
* Configure the I2C core,
* Enable core and
* Calibrate the calibration register for current readout
* @param sclLowCountReg register to set low count of the serial clock
* @param sclHighCountReg register to set high count of the serial clock
* @param sdaHoldTimeReg register to set hold time of the serial data
* @oaram controlReg register to set control reg (bus speed and enabling core)
*/
void I2C_ConfigureI2CCore(uint32_t sclLowCountReg, uint32_t sclHighCountReg, uint32_t sdaHoldTimeReg, uint32_t controlReg) {
FILE_LOG(logINFOBLUE, ("Configuring I2C Core for %d kbps:\n", I2C_DATA_RATE_KBPS));
FILE_LOG(logINFOBLUE, ("\tSetting SCL Low Period: %d ns (0x%x clocks)\n", I2C_SCL_LOW_PERIOD_NS, I2C_SCL_LOW_COUNT));
bus_w(sclLowPeriodReg, (uint32_t)I2C_SCL_LOW_COUNT);
FILE_LOG(logINFOBLUE, ("\tSetting SCL High Period: %d ns (0x%x clocks)\n", I2C_SCL_HIGH_PERIOD_NS, I2C_SCL_LOW_COUNT));
bus_w(sclHighPeriodReg, (uint32_t)I2C_SCL_LOW_COUNT);
FILE_LOG(logINFOBLUE, ("\tSetting SDA Hold Time: %d ns (0x%x clocks)\n", I2C_SDA_DATA_HOLD_TIME_NS, I2C_SDA_DATA_HOLD_COUNT));
bus_w(sdaHoldTimeReg, (uint32_t)I2C_SDA_DATA_HOLD_COUNT);
FILE_LOG(logINFOBLUE, ("\tEnabling core\n"));
bus_w(controlReg, I2C_CNTRL_ENBLE_CORE_MSK | I2C_CTRL_BUS_SPEED_FAST_400_VAL);// fixme: (works?)
}
/**
* Read register
* @param transferCommandReg transfer command fifo register
* @param rxDataFifoLevelReg receive data fifo level register
* @param deviceId device Id
* @param addr register address
* @returns value read from register
*/
uint32_t I2C_Read(uint32_t transferCommandReg, uint32_t rxDataFifoLevelReg, uint32_t devId, uint32_t addr) {
// device Id mask
uint32_t devIdMask = ((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
// write I2C ID
bus_w(transferCommandReg, (devIdMask & ~(I2C_TFR_CMD_RW_MSK)));
// write register addr
bus_w(transferCommandReg, addr);
// repeated start with read
bus_w(transferCommandReg, (devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL));
// continue reading
bus_w(transferCommandReg, 0x0);
// stop reading
bus_w(transferCommandReg, I2C_TFR_CMD_STOP_MSK);
// read value
return bus_r(rxDataFifoLevelReg);
}
/**
* Write register (16 bit value)
* @param transferCommandReg transfer command fifo register
* @param deviceId device Id
* @param addr register address
* @param data data to be written (16 bit)
*/
void I2C_Write(uint32_t transferCommandReg, uint32_t devId, uint32_t addr, uint16_t data) {
// device Id mask
uint32_t devIdMask = ((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
// write I2C ID
bus_w(transferCommandReg, (devIdMask & ~(I2C_TFR_CMD_RW_MSK)));
// write register addr
bus_w(transferCommandReg, addr);
// repeated start with write
bus_w(transferCommandReg, (devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK & ~(I2C_TFR_CMD_RW_MSK)));
uint8_t msb = data & 0xFF00;
uint8_t lsb = data & 0x00FF;
// writing data MSB
bus_w(transferCommandReg, ((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK));
// writing data LSB and stop writing bit
bus_w(transferCommandReg, ((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) | I2C_TFR_CMD_STOP_MSK);
}

126
slsDetectorServers/slsDetectorServer/INA226.h Executable file
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@ -0,0 +1,126 @@
#pragma once
#include "I2C.h"
/** INA226 defines */
/** Register set */
#define INA226_CONFIGURATION_REG (0x00) //R/W
#define INA226_SHUNT_VOLTAGE_REG (0x01) //R
#define INA226_BUS_VOLTAGE_REG (0x02) //R
#define INA226_POWER_REG (0x03) //R
#define INA226_CURRENT_REG (0x04) //R
#define INA226_CALIBRATION_REG (0x05) //R/W
#define INA226_MASK_ENABLE_REG (0x06) //R/W
#define INA226_ALERT_LIMIT_REG (0x07) //R/W
#define INA226_MANUFACTURER_ID_REG (0xFE) //R
#define INA226_DIE_ID_REG (0xFF) //R
/** bus voltage register */
#define INA226_BUS_VOLTAGE_VMIN_UV (1250) // 1.25mV
#define INA226_BUS_VOLTAGE_MX_STPS (0x7FFF + 1)
#define INA226_BUS_VOLTAGE_VMAX_UV (INA226_BUS_VOLTAGE_VMIN_UV * INA226_BUS_VOLTAGE_MX_STPS) // 40960000uV, 40.96V
/** current register */
#define INA226_CURRENT_IMIN_UA (100) //100uA can be changed
#define INA226_CURRENT_MX_STPS (0x7FFF + 1)
#define INA226_CURRENT_IMAX_UA (INA226_CURRENT_IMIN_UA * INA226_CURRENT_MX_STPS)
/** calibration register */
#define INA226_CALIBRATION_MSK (0x7FFF)
/** get calibration register value to be set */
#define INA226_getCalibrationValue(rOhm) (0.00512 /(INA226_CURRENT_IMIN_UA * 1e-6 * rohm))
/** get current unit */
#define INA226_getConvertedCurrentUnits(shuntVReg, calibReg) (shuntVReg * calibReg / 2048)
/**
* Configure the I2C core and Enable core
* @param sclLowCountReg register to set low count of the serial clock (defined in Registerdefs.h)
* @param sclHighCountReg register to set high count of the serial clock (defined in Registerdefs.h)
* @param sdaHoldTimeReg register to set hold time of the serial data (defined in Registerdefs.h)
* @param controlReg register to set control reg (bus speed and enabling core) (defined in Registerdefs.h)
*/
void INA226_ConfigureI2CCore(uint32_t sclLowCountReg, uint32_t sclHighCountReg, uint32_t sdaHoldTimeReg, uint32_t controlReg) {
I2C_ConfigureI2CCore(sclLowCountReg, sclHighCountReg, sdaHoldTimeReg, controlReg);
}
/**
* Calibrate resolution of current register
* @param shuntResisterOhm shunt resister value in Ohms
* @param transferCommandReg transfer command fifo register (defined in RegisterDefs.h)
* @param deviceId device Id (defined in slsDetectorServer_defs.h)
*/
void INA226_CalibrateCurrentRegister(uint32_t shuntResisterOhm, uint32_t transferCommandReg, uint32_t deviceId) {
// get calibration value based on shunt resistor
uint16_t calVal = INA226_getCalibrationValue(shuntResisterOhm) & INA226_CALIBRATION_MSK;
FILE_LOG(logINFO, ("\tWriting to Calibration reg: 0x%0x\n", calVal));
// calibrate current register
I2C_Write(transferCommandReg, deviceId, INA226_CALIBRATION_REG, calVal);
}
/**
* Read voltage of device
* @param transferCommandReg transfer command fifo register (defined in RegisterDefs.h)
* @param rxDataFifoLevelReg receive data fifo level register (defined in RegisterDefs.h)
* @param deviceId device Id (defined in slsDetectorServer_defs.h)
* @returns voltage in mV
*/
int INA226_ReadVoltage(uint32_t transferCommandReg, uint32_t rxDataFifoLevelReg, uint32_t deviceId) {
FILE_LOG(logDEBUG1, ("\tReading voltage\n"));
uint32_t regval = I2C_Read(transferCommandReg, rxDataFifoLevelReg, deviceId, INA226_BUS_VOLTAGE_REG);
FILE_LOG(logDEBUG1, ("\tvoltage read: 0x%08x\n", regval));
// value converted in mv
uint32_t vmin = INA226_BUS_VOLTAGE_VMIN_UV;
uint32_t vmax = INA226_BUS_VOLTAGE_VMAX_UV;
uint32_t nsteps = INA226_BUS_VOLTAGE_MX_STPS;
// value in uV
int retval = (vmin + (vmax - vmin) * regval / (nsteps - 1));
FILE_LOG(logDEBUG1, ("\tvoltage read: 0x%d uV\n", retval));
// value in mV
retval /= 1000;
FILE_LOG(logDEBUG1, ("\tvoltage read: %d mV\n", retval));
return retval;
}
/**
* Read current
* @param transferCommandReg transfer command fifo register (defined in RegisterDefs.h)
* @param rxDataFifoLevelReg receive data fifo level register (defined in RegisterDefs.h)
* @param deviceId device Id (should be defined in slsDetectorServer_defs.h)
* @returns current in mA
*/
int INA226_ReadCurrent(uint32_t transferCommandReg, uint32_t rxDataFifoLevelReg, uint32_t deviceId) {
FILE_LOG(logDEBUG1, ("\tReading current\n"));
// read shunt voltage register
FILE_LOG(logDEBUG1, ("\tReading shunt voltage reg\n"));
uint32_t shuntVoltageRegVal = I2C_Read(transferCommandReg, rxDataFifoLevelReg, deviceId, INA226_SHUNT_VOLTAGE_REG);
FILE_LOG(logDEBUG1, ("\tshunt voltage reg: 0x%08x\n", regval));
// read calibration register
FILE_LOG(logDEBUG1, ("\tReading calibration reg\n"));
uint32_t calibrationRegVal = I2C_Read(transferCommandReg, rxDataFifoLevelReg, deviceId, INA226_CALIBRATION_REG);
FILE_LOG(logDEBUG1, ("\tcalibration reg: 0x%08x\n", regval));
// value for current
uint32_t retval = INA226_getConvertedCurrentUnits(shuntVoltageRegVal, calibrationRegVal);
FILE_LOG(logDEBUG1, ("\tcurrent unit value: %d\n", retval));
// current in uA
retval *= INA226_CURRENT_IMIN_UA;
FILE_LOG(logDEBUG1, ("\tcurrent: %d uA\n", retval));
// current in mA
retval /= 1000;
FILE_LOG(logDEBUG1, ("\tcurrent: %d mA\n", retval));
return retval;
}

26
slsDetectorServers/slsDetectorServer/Makefile
View File

@ -1,26 +0,0 @@
CC = gcc
CLAGS += -Wall -DVIRTUAL -DDACS_INT -DGENERICD # -DSLS_DETECTOR_FUNCTION_LIST
LDLIBS += -lm
PROGS = genericDetectorServer
DESTDIR ?= bin
INSTMODE = 0777
SRC_CLNT = slsDetectorServer.c slsDetectorServer_funcs.c communication_funcs.c slsDetectorFunctionList.c
OBJS = $(SRC_CLNT:.cpp=.o)
all: clean $(PROGS)
boot: $(OBJS)
$(PROGS):
echo $(OBJS)
mkdir -p $(DESTDIR)
$(CC) $(SRC_CLNT) $(CLAGS) $(LDLIBS) -o $@
mv $(PROGS) $(DESTDIR)
clean:
rm -rf $(DESTDIR)/$(PROGS) *.o

3
slsDetectorServers/slsDetectorServer/blackfin.h
View File

@ -11,7 +11,8 @@ u_int64_t CSP0BASE = 0;
#define CSP0 0x20200000
#define MEM_SIZE 0x100000
/** I2C defines */
#define I2C_CLOCK_MHZ (131.25)
/**
* Write into a 16 bit register

10
slsDetectorServers/slsDetectorServer/commonServerFunctions.h
View File

@ -2,7 +2,7 @@
#include "blackfin.h"
void SPIChipSelect (u_int32_t* valw, u_int32_t addr, u_int32_t csmask) {
void SPIChipSelect (uint32_t* valw, uint32_t addr, uint32_t csmask) {
// start point
(*valw) = 0xffffffff; // old board compatibility (not using specific bits)
@ -14,7 +14,7 @@ void SPIChipSelect (u_int32_t* valw, u_int32_t addr, u_int32_t csmask) {
}
void SPIChipDeselect (u_int32_t* valw, u_int32_t addr, u_int32_t csmask, u_int32_t clkmask) {
void SPIChipDeselect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask) {
// chip sel bar up
(*valw) |= csmask; /* todo with test: not done for spi */
bus_w (addr, (*valw));
@ -28,7 +28,7 @@ void SPIChipDeselect (u_int32_t* valw, u_int32_t addr, u_int32_t csmask, u_int3
bus_w (addr, (*valw));
}
void sendDataToSPI (u_int32_t* valw, u_int32_t addr, u_int32_t val, int numbitstosend, u_int32_t clkmask, u_int32_t digoutmask, int digofset) {
void sendDataToSPI (uint32_t* valw, uint32_t addr, uint32_t val, int numbitstosend, uint32_t clkmask, uint32_t digoutmask, int digofset) {
int i = 0;
for (i = 0; i < numbitstosend; ++i) {
@ -48,13 +48,13 @@ void sendDataToSPI (u_int32_t* valw, u_int32_t addr, u_int32_t val, int numbitst
}
void serializeToSPI(u_int32_t addr, u_int32_t val, u_int32_t csmask, int numbitstosend, u_int32_t clkmask, u_int32_t digoutmask, int digofset) {
void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask, int numbitstosend, uint32_t clkmask, uint32_t digoutmask, int digofset) {
if (numbitstosend == 16) {
FILE_LOG(logDEBUG1, ("Writing to SPI Register: 0x%04x\n", val));
} else {
FILE_LOG(logDEBUG1, ("Writing to SPI Register: 0x%08x\n", val));
}
u_int32_t valw;
uint32_t valw;
SPIChipSelect (&valw, addr, csmask);

54
slsDetectorServers/slsDetectorServer/communication_funcs.c
View File

@ -299,14 +299,52 @@ int receiveData(int file_des, void* buf,int length, intType itype){
int sendDataOnly(int file_des, void* buf,int length) {
if (!length)
return 0;
int lret = write(file_des, buf, length); //value of -1 is other end socket crash as sigpipe is ignored
if (lret < 0) {
FILE_LOG(logERROR, ("Could not write to %s socket. Possible socket crash\n",
(isControlServer ? "control":"stop")));
}
return lret;
if (!length)
return 0;
int bytesSent = 0;
int retry = 0; // retry index when buffer is blocked (write returns 0)
while (bytesSent < length) {
// setting a max packet size for blackfin driver (and network driver does not do a check if packets sent)
int bytesToSend = length - bytesSent;
if (bytesToSend > BLACKFIN_DRVR_SND_LMT)
bytesToSend = BLACKFIN_DRVR_SND_LMT;
// send
int rc = write(file_des, (char*)((char*)buf + bytesSent), bytesToSend);
// error
if (rc < 0) {
FILE_LOG(logERROR, ("Could not write to %s socket. Possible socket crash\n",
(isControlServer ? "control":"stop")));
return bytesSent;
}
// also error, wrote nothing, buffer blocked up, too fast sending for client
if (rc == 0) {
FILE_LOG(logERROR, ("Could not write to %s socket. Buffer full. Retry: %d\n",
(isControlServer ? "control":"stop"), retry));
++retry;
// wrote nothing for many loops
if (retry >= BLACKFIN_RSND_PCKT_LOOP) {
FILE_LOG(logERROR, ("Could not write to %s socket. Buffer full! Too fast! No more.\n",
(isControlServer ? "control":"stop")));
return bytesSent;
}
usleep(BLACKFIN_RSND_WAIT_US);
}
// wrote something, reset retry
else {
retry = 0;
if (rc != bytesToSend) {
FILE_LOG(logWARNING, ("Only partial write to %s socket. Expected to write %d bytes, wrote %d\n",
(isControlServer ? "control":"stop"), bytesToSend, rc));
}
}
bytesSent += rc;
}
return bytesSent;
}

838
slsDetectorServers/slsDetectorServer/slsDetectorFunctionList.c
View File

@ -1,838 +0,0 @@
#ifdef SLS_DETECTOR_FUNCTION_LIST
#include "slsDetectorFunctionList.h"
#include "slsDetectorServer_defs.h"
#include <stdio.h>
#include <string.h>
const int nChans=NCHAN;
const int nChips=NCHIP;
const int nDacs=NDAC;
const int nAdcs=NADC;
const int allSelected=-2;
const int noneSelected=-1;
sls_detector_module *detectorModules=NULL;
int *detectorChips=NULL;
int *detectorChans=NULL;
dacs_t *detectorDacs=NULL;
dacs_t *detectorAdcs=NULL;
int nModY = NMAXMOD;
int nModX = NMAXMOD;
int dynamicRange= DYNAMIC_RANGE;
int dataBytes = NMAXMOD*NCHIP*NCHAN*2;
int masterMode = NO_MASTER;
int syncMode = NO_SYNCHRONIZATION;
int timingMode = AUTO_TIMING;
enum detectorSettings thisSettings;
int sChan, sChip, sMod, sDac, sAdc;
int nModBoard;
extern int dataBytes;
int initializeDetectorStructure(){
int imod;
int n=getNModBoard(X)*getNModBoard(Y);
#ifdef VERBOSE
printf("Board is for %d modules\n",n);
#endif
detectorModules=malloc(n*sizeof(sls_detector_module));
detectorChips=malloc(n*NCHIP*sizeof(int));
detectorChans=malloc(n*NCHIP*NCHAN*sizeof(int));
detectorDacs=malloc(n*NDAC*sizeof(int));
detectorAdcs=malloc(n*NADC*sizeof(int));
#ifdef VERBOSE
printf("modules from 0x%x to 0x%x\n",(unsigned int)(detectorModules), (unsigned int)(detectorModules+n));
printf("chips from 0x%x to 0x%x\n",(unsigned int)(detectorChips), (unsigned int)(detectorChips+n*NCHIP));
printf("chans from 0x%x to 0x%x\n",(unsigned int)(detectorChans), (unsigned int)(detectorChans+n*NCHIP*NCHAN));
printf("dacs from 0x%x to 0x%x\n",(unsigned int)(detectorDacs), (unsigned int)(detectorDacs+n*NDAC));
printf("adcs from 0x%x to 0x%x\n",(unsigned int)(detectorAdcs), (unsigned int)(detectorAdcs+n*NADC));
#endif
for (imod=0; imod<n; imod++) {
(detectorModules+imod)->dacs=detectorDacs+imod*NDAC;
(detectorModules+imod)->adcs=detectorAdcs+imod*NADC;
(detectorModules+imod)->chipregs=detectorChips+imod*NCHIP;
(detectorModules+imod)->chanregs=detectorChans+imod*NCHIP*NCHAN;
(detectorModules+imod)->ndac=NDAC;
(detectorModules+imod)->nadc=NADC;
(detectorModules+imod)->nchip=NCHIP;
(detectorModules+imod)->nchan=NCHIP*NCHAN;
(detectorModules+imod)->module=imod;
(detectorModules+imod)->gain=0;
(detectorModules+imod)->offset=0;
(detectorModules+imod)->reg=0;
/* initialize registers, dacs, retrieve sn, adc values etc */
}
thisSettings=UNINITIALIZED;
sChan=noneSelected;
sChip=noneSelected;
sMod=noneSelected;
sDac=noneSelected;
sAdc=noneSelected;
return OK;
}
int setupDetector(){
//testFpga();
//testRAM();
//setSettings(GET_SETTINGS,-1);
//setFrames(1);
//setTrains(1);
//setExposureTime(1e6);
//setPeriod(1e9);
//setDelay(0);
//setGates(0);
//setTiming(GET_EXTERNAL_COMMUNICATION_MODE);
//setMaster(GET_MASTER);
//setSynchronization(GET_SYNCHRONIZATION_MODE);
return OK;
}
int setNMod(int nm, enum dimension dim){
return 1;
}
int getNModBoard(enum dimension arg){
return 1;
}
int64_t getModuleId(enum idMode arg, int imod){
//DETECTOR_SERIAL_NUMBER
//DETECTOR_FIRMWARE_VERSION
return 0;
}
int64_t getDetectorId(enum idMode arg){
//DETECTOR_SOFTWARE_VERSION defined in slsDetector_defs.h?
return 0;
}
int moduleTest( enum digitalTestMode arg, int imod){
//template testShiftIn from mcb_funcs.c
//CHIP_TEST
//testShiftIn
//testShiftOut
//testShiftStSel
//testDataInOutMux
//testExtPulseMux
//testOutMux
//testFpgaMux
return OK;
}
int detectorTest( enum digitalTestMode arg){
//templates from firmware_funcs.c
//DETECTOR_FIRMWARE_TEST:testFpga()
//DETECTOR_MEMORY_TEST:testRAM()
//DETECTOR_BUS_TEST:testBus()
//DETECTOR_SOFTWARE_TEST:testFpga()
return OK;
}
double setDAC(enum dacIndex ind, double val, int imod){
//template initDACbyIndexDACU from mcb_funcs.c
//check that slsDetectorServer_funcs.c set_dac() has all the specific dac enums
//set dac and write to a register in fpga to remember dac value when server restarts
return 0;
}
double getADC(enum dacIndex ind, int imod){
//get adc value
return 0;
}
int setChannel(sls_detector_channel myChan){
//template initChannelByNumber() from mcb_funcs.c
return myChan.reg;
}
int getChannel(sls_detector_channel *myChan){
//template getChannelbyNumber() from mcb_funcs.c
return FAIL;
}
int setChip(sls_detector_chip myChip){
//template initChipbyNumber() from mcb_funcs.c
return myChip.reg;
}
int getChip(sls_detector_chip *myChip){
//template getChipbyNumber() from mcb_funcs.c
return FAIL;
}
int setModule(sls_detector_module myChan){
//template initModulebyNumber() from mcb_funcs.c
return OK;
}
int getModule(sls_detector_module *myChan){
//template getModulebyNumber() from mcb_funcs.c
return FAIL;
}
int getThresholdEnergy(int imod){
//template getThresholdEnergy() from mcb_funcs.c
//depending on settings
return FAIL;
}
int setThresholdEnergy(int thr, int imod){
//template getThresholdEnergy() from mcb_funcs.c
//depending on settings
return FAIL;
}
enum detectorSettings setSettings(enum detectorSettings sett, int imod){
//template setSettings() from mcb_funcs.c
//reads the dac registers from fpga to confirm which settings, if weird, undefined
return OK;
}
int startStateMachine(){
//template startStateMachine() from firmware_funcs.c
/*
fifoReset();
now_ptr=(char*)ram_values;
//send start acquisition to fpga
*/
return FAIL;
}
int stopStateMachine(){
//template stopStateMachine() from firmware_funcs.c
// send stop to fpga
//if status = busy after 500us, return FAIL
return FAIL;
}
int startReadOut(){
//template startReadOut() from firmware_funcs.c
//send fpga start readout
return FAIL;
}
enum runStatus getRunStatus(){
//template runState() from firmware_funcs.c
//get status from fpga
return ERROR;
}
char *readFrame(int *ret, char *mess){
//template fifo_read_event() from firmware_funcs.c
//checks if state machine running and if fifo has data(look_at_me_reg) and accordingly reads frame
// memcpy(now_ptr, values, dataBytes);
//returns ptr to values
return NULL;
}
int64_t setTimer(enum timerIndex ind, int64_t val){
//template setDelay() from firmware_funcs.c
//writes to reg
//FRAME_NUMBER
//ACQUISITION_TIME
//FRAME_PERIOD
//DELAY_AFTER_TRIGGER
//GATES_NUMBER
//PROBES_NUMBER
//CYCLES_NUMBER
return 0;
}
int64_t getTimeLeft(enum timerIndex ind){
//template getDelay() from firmware_funcs.c
//reads from reg
//FRAME_NUMBER
//ACQUISITION_TIME
//FRAME_PERIOD
//DELAY_AFTER_TRIGGER
//GATES_NUMBER
//PROBES_NUMBER
//CYCLES_NUMBER
return -1;
}
int setDynamicRange(int dr){
//template setDynamicRange() from firmware_funcs.c
return 0;
}
enum readOutFlags setReadOutFlags(enum readOutFlags val){
//template setStoreInRAM from firmware_funcs.c
return -1;
}
int setROI(int n, ROI arg[], int *retvalsize, int *ret){
return FAIL;
}
int setSpeed(enum speedVariable arg, int val){
//template setClockDivider() from firmware_funcs.c
//CLOCK_DIVIDER
//WAIT_STATES
//SET_SIGNAL_LENGTH
//TOT_CLOCK_DIVIDER
//TOT_DUTY_CYCLE
//returns eg getClockDivider from firmware_funcs.c
return 0;
}
int executeTrimming(enum trimMode mode, int par1, int par2, int imod){
// template trim_with_noise from trimming_funcs.c
return FAIL;
}
int configureMAC(int ipad, long long int imacadd, long long int iservermacadd, int dtb){
//detector specific.
return FAIL;
}
int loadImage(enum imageType index, char *imageVals){
//detector specific.
return FAIL;
}
int readCounterBlock(int startACQ, char *counterVals){
//detector specific.
return FAIL;
}
int resetCounterBlock(int startACQ){
//detector specific.
return FAIL;
}
int startReceiver(int d){
return 0;
}
int calibratePedestal(int frames){
return 0;
}
int calculateDataBytes(){
return 0;
}
int getTotalNumberOfChannels(){return 0;}
int getTotalNumberOfChips(){return 0;}
int getTotalNumberOfModules(){return 0;}
int getNumberOfChannelsPerChip(){return 0;}
int getNumberOfChannelsPerModule(){return 0;}
int getNumberOfChipsPerModule(){return 0;}
int getNumberOfDACsPerModule(){return 0;}
int getNumberOfADCsPerModule(){return 0;}
enum externalSignalFlag getExtSignal(int signalindex){
//template getExtSignal from firmware_funcs.c
//return signals[signalindex];
return -1;
}
enum externalSignalFlag setExtSignal(int signalindex, enum externalSignalFlag flag){
//template setExtSignal from firmware_funcs.c
//in short..sets signals array, checks if agrees with timing mode, writes to fpga reg, calls synchronization and then settiming
/*
if (signalindex>=0 && signalindex<4) {
signals[signalindex]=flag;
#ifdef VERBOSE
printf("settings signal variable number %d to value %04x\n", signalindex, signals[signalindex]);
#endif
// if output signal, set it!
switch (flag) {
case GATE_IN_ACTIVE_HIGH:
case GATE_IN_ACTIVE_LOW:
if (timingMode==GATE_FIX_NUMBER || timingMode==GATE_WITH_START_TRIGGER)//timingMode = AUTO_TIMING by default and is set in setTiming()
setFPGASignal(signalindex,flag); //not implemented here, checks if flag within limits and writes to fpga reg
else
setFPGASignal(signalindex,SIGNAL_OFF);
break;
case TRIGGER_IN_RISING_EDGE:
case TRIGGER_IN_FALLING_EDGE:
if (timingMode==TRIGGER_EXPOSURE || timingMode==GATE_WITH_START_TRIGGER)
setFPGASignal(signalindex,flag);
else
setFPGASignal(signalindex,SIGNAL_OFF);
break;
case RO_TRIGGER_IN_RISING_EDGE:
case RO_TRIGGER_IN_FALLING_EDGE:
if (timingMode==BURST_TRIGGER)
setFPGASignal(signalindex,flag);
else
setFPGASignal(signalindex,SIGNAL_OFF);
break;
case MASTER_SLAVE_SYNCHRONIZATION:
setSynchronization(syncMode);//syncmode = NO_SYNCHRONIZATION by default and set with this function
break;
default:
setFPGASignal(signalindex,mode);
}
setTiming(GET_EXTERNAL_COMMUNICATION_MODE);
}
*/
return getExtSignal(signalindex);
}
enum externalCommunicationMode setTiming( enum externalCommunicationMode arg){
//template setTiming from firmware_funcs.c
//template getFPGASignal from firmware_funcs.c
//getFPGASignal(signalindex) used later on in this fucntion
//gets flag from fpga reg, checks if flag within limits,
//if( flag=SIGNAL_OFF and signals[signalindex]==MASTER_SLAVE_SYNCHRONIZATION), return -1, (ensures masterslaveflag !=off now)
//else return flag
int ret=GET_EXTERNAL_COMMUNICATION_MODE;
//sets timingmode variable
//ensures that the signals are in acceptance with timing mode and according sets the timing mode
/*
int g=-1, t=-1, rot=-1;
int i;
switch (ti) {
case AUTO_TIMING:
timingMode=ti;
// disable all gates/triggers in except if used for master/slave synchronization
for (i=0; i<4; i++) {
if (getFPGASignal(i)>0 && getFPGASignal(i)<GATE_OUT_ACTIVE_HIGH && signals[i]!=MASTER_SLAVE_SYNCHRONIZATION)
setFPGASignal(i,SIGNAL_OFF);
}
break;
case TRIGGER_EXPOSURE:
timingMode=ti;
// if one of the signals is configured to be trigger, set it and unset possible gates
for (i=0; i<4; i++) {
if (signals[i]==TRIGGER_IN_RISING_EDGE || signals[i]==TRIGGER_IN_FALLING_EDGE)
setFPGASignal(i,signals[i]);
else if (signals[i]==GATE_IN_ACTIVE_HIGH || signals[i]==GATE_IN_ACTIVE_LOW)
setFPGASignal(i,SIGNAL_OFF);
else if (signals[i]==RO_TRIGGER_IN_RISING_EDGE || signals[i]==RO_TRIGGER_IN_FALLING_EDGE)
setFPGASignal(i,SIGNAL_OFF);
}
break;
case TRIGGER_READOUT:
timingMode=ti;
// if one of the signals is configured to be trigger, set it and unset possible gates
for (i=0; i<4; i++) {
if (signals[i]==RO_TRIGGER_IN_RISING_EDGE || signals[i]==RO_TRIGGER_IN_FALLING_EDGE)
setFPGASignal(i,signals[i]);
else if (signals[i]==GATE_IN_ACTIVE_HIGH || signals[i]==GATE_IN_ACTIVE_LOW)
setFPGASignal(i,SIGNAL_OFF);
else if (signals[i]==TRIGGER_IN_RISING_EDGE || signals[i]==TRIGGER_IN_FALLING_EDGE)
setFPGASignal(i,SIGNAL_OFF);
}
break;
case GATE_FIX_NUMBER:
timingMode=ti;
// if one of the signals is configured to be trigger, set it and unset possible gates
for (i=0; i<4; i++) {
if (signals[i]==RO_TRIGGER_IN_RISING_EDGE || signals[i]==RO_TRIGGER_IN_FALLING_EDGE)
setFPGASignal(i,SIGNAL_OFF);
else if (signals[i]==GATE_IN_ACTIVE_HIGH || signals[i]==GATE_IN_ACTIVE_LOW)
setFPGASignal(i,signals[i]);
else if (signals[i]==TRIGGER_IN_RISING_EDGE || signals[i]==TRIGGER_IN_FALLING_EDGE)
setFPGASignal(i,SIGNAL_OFF);
}
break;
case GATE_WITH_START_TRIGGER:
timingMode=ti;
for (i=0; i<4; i++) {
if (signals[i]==RO_TRIGGER_IN_RISING_EDGE || signals[i]==RO_TRIGGER_IN_FALLING_EDGE)
setFPGASignal(i,SIGNAL_OFF);
else if (signals[i]==GATE_IN_ACTIVE_HIGH || signals[i]==GATE_IN_ACTIVE_LOW)
setFPGASignal(i,signals[i]);
else if (signals[i]==TRIGGER_IN_RISING_EDGE || signals[i]==TRIGGER_IN_FALLING_EDGE)
setFPGASignal(i,signals[i]);
}
break;
default:
;
}
for (i=0; i<4; i++) {
if (signals[i]!=MASTER_SLAVE_SYNCHRONIZATION) {
if (getFPGASignal(i)==RO_TRIGGER_IN_RISING_EDGE || getFPGASignal(i)==RO_TRIGGER_IN_FALLING_EDGE)
rot=i;
else if (getFPGASignal(i)==GATE_IN_ACTIVE_HIGH || getFPGASignal(i)==GATE_IN_ACTIVE_LOW)
g=i;
else if (getFPGASignal(i)==TRIGGER_IN_RISING_EDGE || getFPGASignal(i)==TRIGGER_IN_FALLING_EDGE)
t=i;
}
}
if (g>=0 && t>=0 && rot<0) {
ret=GATE_WITH_START_TRIGGER;
} else if (g<0 && t>=0 && rot<0) {
ret=TRIGGER_EXPOSURE;
} else if (g>=0 && t<0 && rot<0) {
ret=GATE_FIX_NUMBER;
} else if (g<0 && t<0 && rot>0) {
ret=TRIGGER_READOUT;
} else if (g<0 && t<0 && rot<0) {
ret=AUTO_TIMING;
}
*/
return ret;
}
enum masterFlags setMaster(enum masterFlags arg){
//template setMaster from firmware_funcs.c
/*
int i;
switch(f) {
case NO_MASTER:
// switch of gates or triggers
masterMode=NO_MASTER;
for (i=0; i<4; i++) {
if (signals[i]==MASTER_SLAVE_SYNCHRONIZATION) {
setFPGASignal(i,SIGNAL_OFF);
}
}
break;
case IS_MASTER:
// configure gate or trigger out
masterMode=IS_MASTER;
for (i=0; i<4; i++) {
if (signals[i]==MASTER_SLAVE_SYNCHRONIZATION) {
switch (syncMode) {
case NO_SYNCHRONIZATION:
setFPGASignal(i,SIGNAL_OFF);
break;
case MASTER_GATES:
setFPGASignal(i,GATE_OUT_ACTIVE_HIGH);
break;
case MASTER_TRIGGERS:
setFPGASignal(i,TRIGGER_OUT_RISING_EDGE);
break;
case SLAVE_STARTS_WHEN_MASTER_STOPS:
setFPGASignal(i,RO_TRIGGER_OUT_RISING_EDGE);
break;
default:
;
}
}
}
break;
case IS_SLAVE:
// configure gate or trigger in
masterMode=IS_SLAVE;
for (i=0; i<4; i++) {
if (signals[i]==MASTER_SLAVE_SYNCHRONIZATION) {
switch (syncMode) {
case NO_SYNCHRONIZATION:
setFPGASignal(i,SIGNAL_OFF);
break;
case MASTER_GATES:
setFPGASignal(i,GATE_IN_ACTIVE_HIGH);
break;
case MASTER_TRIGGERS:
setFPGASignal(i,TRIGGER_IN_RISING_EDGE);
break;
case SLAVE_STARTS_WHEN_MASTER_STOPS:
setFPGASignal(i,TRIGGER_IN_RISING_EDGE);
break;
default:
;
}
}
}
break;
default:
//do nothing
;
}
switch(masterMode) {
case NO_MASTER:
return NO_MASTER;
case IS_MASTER:
for (i=0; i<4; i++) {
if (signals[i]==MASTER_SLAVE_SYNCHRONIZATION) {
switch (syncMode) {
case NO_SYNCHRONIZATION:
return IS_MASTER;
case MASTER_GATES:
if (getFPGASignal(i)==GATE_OUT_ACTIVE_HIGH)
return IS_MASTER;
else
return NO_MASTER;
case MASTER_TRIGGERS:
if (getFPGASignal(i)==TRIGGER_OUT_RISING_EDGE)
return IS_MASTER;
else
return NO_MASTER;
case SLAVE_STARTS_WHEN_MASTER_STOPS:
if (getFPGASignal(i)==RO_TRIGGER_OUT_RISING_EDGE)
return IS_MASTER;
else
return NO_MASTER;
default:
return NO_MASTER;
}
}
}
case IS_SLAVE:
for (i=0; i<4; i++) {
if (signals[i]==MASTER_SLAVE_SYNCHRONIZATION) {
switch (syncMode) {
case NO_SYNCHRONIZATION:
return IS_SLAVE;
case MASTER_GATES:
if (getFPGASignal(i)==GATE_IN_ACTIVE_HIGH)
return IS_SLAVE;
else
return NO_MASTER;
case MASTER_TRIGGERS:
case SLAVE_STARTS_WHEN_MASTER_STOPS:
if (getFPGASignal(i)==TRIGGER_IN_RISING_EDGE)
return IS_SLAVE;
else
return NO_MASTER;
default:
return NO_MASTER;
}
}
}
}
*/
return NO_MASTER;
}
enum synchronizationMode setSynchronization(enum synchronizationMode arg){
/*
int i;
switch(s) {
case NO_SYNCHRONIZATION:
syncMode=NO_SYNCHRONIZATION;
for (i=0; i<4; i++) {
if (signals[i]==MASTER_SLAVE_SYNCHRONIZATION) {
setFPGASignal(i,SIGNAL_OFF);
}
}
break;
// disable external signals?
case MASTER_GATES:
// configure gate in or out
syncMode=MASTER_GATES;
for (i=0; i<4; i++) {
if (signals[i]==MASTER_SLAVE_SYNCHRONIZATION) {
if (masterMode==IS_MASTER)
setFPGASignal(i,GATE_OUT_ACTIVE_HIGH);
else if (masterMode==IS_SLAVE)
setFPGASignal(i,GATE_IN_ACTIVE_HIGH);
}
}
break;
case MASTER_TRIGGERS:
// configure trigger in or out
syncMode=MASTER_TRIGGERS;
for (i=0; i<4; i++) {
if (signals[i]==MASTER_SLAVE_SYNCHRONIZATION) {
if (masterMode==IS_MASTER)
setFPGASignal(i,TRIGGER_OUT_RISING_EDGE);
else if (masterMode==IS_SLAVE)
setFPGASignal(i,TRIGGER_IN_RISING_EDGE);
}
}
break;
case SLAVE_STARTS_WHEN_MASTER_STOPS:
// configure trigger in or out
syncMode=SLAVE_STARTS_WHEN_MASTER_STOPS;
for (i=0; i<4; i++) {
if (signals[i]==MASTER_SLAVE_SYNCHRONIZATION) {
if (masterMode==IS_MASTER)
setFPGASignal(i,RO_TRIGGER_OUT_RISING_EDGE);
else if (masterMode==IS_SLAVE)
setFPGASignal(i,TRIGGER_IN_RISING_EDGE);
}
}
break;
default:
//do nothing
;
}
switch (syncMode) {
case NO_SYNCHRONIZATION:
return NO_SYNCHRONIZATION;
case MASTER_GATES:
for (i=0; i<4; i++) {
if (signals[i]==MASTER_SLAVE_SYNCHRONIZATION) {
if (masterMode==IS_MASTER && getFPGASignal(i)==GATE_OUT_ACTIVE_HIGH)
return MASTER_GATES;
else if (masterMode==IS_SLAVE && getFPGASignal(i)==GATE_IN_ACTIVE_HIGH)
return MASTER_GATES;
}
}
return NO_SYNCHRONIZATION;
case MASTER_TRIGGERS:
for (i=0; i<4; i++) {
if (signals[i]==MASTER_SLAVE_SYNCHRONIZATION) {
if (masterMode==IS_MASTER && getFPGASignal(i)==TRIGGER_OUT_RISING_EDGE)
return MASTER_TRIGGERS;
else if (masterMode==IS_SLAVE && getFPGASignal(i)==TRIGGER_IN_RISING_EDGE)
return MASTER_TRIGGERS;
}
}
return NO_SYNCHRONIZATION;
case SLAVE_STARTS_WHEN_MASTER_STOPS:
for (i=0; i<4; i++) {
if (signals[i]==MASTER_SLAVE_SYNCHRONIZATION) {
if (masterMode==IS_MASTER && getFPGASignal(i)==RO_TRIGGER_OUT_RISING_EDGE)
return SLAVE_STARTS_WHEN_MASTER_STOPS;
else if (masterMode==IS_SLAVE && getFPGASignal(i)==TRIGGER_IN_RISING_EDGE)
return SLAVE_STARTS_WHEN_MASTER_STOPS;
}
}
return NO_SYNCHRONIZATION;
default:
return NO_SYNCHRONIZATION;
}
*/
return NO_SYNCHRONIZATION;
}
#endif

108
slsDetectorServers/slsDetectorServer/slsDetectorFunctionList.h
View File

@ -15,12 +15,10 @@ Here are the definitions, but the actual implementation should be done for each
// basic tests
#if defined(EIGERD) || defined(JUNGFRAUD) || defined(GOTTHARDD)
int isFirmwareCheckDone();
int getFirmwareCheckResult(char** mess);
#endif
void basictests();
#if defined(GOTTHARDD) || defined(JUNGFRAUD)
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD)
int checkType();
u_int32_t testFpga(void);
int testBus(void);
@ -28,14 +26,14 @@ int testBus(void);
#ifdef GOTTHARDD
int detectorTest(enum digitalTestMode arg, int ival);
#elif JUNGFRAUD
#elif defined(JUNGFRAUD) || defined(CHIPTESTBOARDD)
int detectorTest(enum digitalTestMode arg);
#endif
// Ids
int64_t getDetectorId(enum idMode arg);
u_int64_t getFirmwareVersion();
#ifdef JUNGFRAUD
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD)
u_int64_t getFirmwareAPIVersion();
u_int16_t getHardwareVersionNumber();
u_int16_t getHardwareSerialNumber();
@ -60,6 +58,11 @@ void getModuleConfiguration();
void allocateDetectorStructureMemory();
#endif
void setupDetector();
#ifdef CHIPTESTBOARDD
int allocateRAM();
void updateDataBytes();
int getChannels();
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD)
int setDefaultDacs();
#endif
@ -80,14 +83,9 @@ uint32_t readRegister16And32(uint32_t offset);
// firmware functions (resets)
#ifdef JUNGFRAUD
int powerChip (int on);
void cleanFifos();
void resetCore();
void resetPeripheral();
int autoCompDisable(int on);
int adcPhase(int st);
int getPhase();
void configureASICTimer();
#elif GOTTHARDD
void setPhaseShiftOnce();
void setPhaseShift(int numphaseshift);
@ -100,19 +98,24 @@ void setROIADC(int adc);
void setGbitReadout();
int readConfigFile();
void setMasterSlaveConfiguration();
#elif CHIPTESTBOARDD
void cleanFifos();
void resetCore();
void resetPeripheral();
#endif
// parameters - dr, roi
int setDynamicRange(int dr);
#ifdef GOTTHARDD
#if defined(GOTTHARDD) || defined(CHIPTESTBOARDD)
ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret);
#endif
// parameters - readout
#ifndef GOTTHARDD
enum speedVariable setSpeed(int val);
void setSpeed(enum speedVariable ind, int val);
int getSpeed(enum speedVariable ind);
#endif
#ifdef EIGERD
#if defined(EIGERD) || defined(CHIPTESTBOARDD)
enum readOutFlags setReadOutFlags(enum readOutFlags val);
#endif
@ -122,16 +125,17 @@ int selectStoragecellStart(int pos);
#endif
int64_t setTimer(enum timerIndex ind, int64_t val);
int64_t getTimeLeft(enum timerIndex ind);
#if defined(JUNGFRAUD) || (GOTTHARDD)
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD)
int validateTimer(enum timerIndex ind, int64_t val, int64_t retval);
#endif
// parameters - module, settings
#ifndef CHIPTESTBOARDD
int setModule(sls_detector_module myMod, char* mess);
int getModule(sls_detector_module *myMod);
enum detectorSettings setSettings(enum detectorSettings sett);
enum detectorSettings getSettings();
#endif
// parameters - threshold
#ifdef EIGERD
@ -140,20 +144,42 @@ int setThresholdEnergy(int ev);
#endif
// parameters - dac, adc, hv
#if defined(GOTTHARDD) || defined(JUNGFRAUD)
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined (CHIPTESTBOARDD)
void serializeToSPI(u_int32_t addr, u_int32_t val, u_int32_t csmask, int numbitstosend, u_int32_t clkmask, u_int32_t digoutmask, int digofset); //commonServerFunction.h
void initDac(int dacnum);
int voltageToDac(int value);
int dacToVoltage(unsigned int digital);
#endif
#ifdef CHIPTESTBOARDD
int generalVoltageToDac(int value, int vmin, int vmax, int check);
int generalDacToVoltage(unsigned int digital, int vmin, int vmax, int check);
#endif
#ifdef GOTTHARDD
extern void setAdc9257(int addr, int val); // AD9257.h
extern void setAdc9252(int addr, int val); // AD9252.h (old board)
#elif JUNGFRAUD
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD)
extern void setAdc9257(int addr, int val); // AD9257.h
#endif
#ifdef CHIPTESTBOARDD
extern int getMaxValidVref(); // AD9257.h
extern void setVrefVoltage(int val) // AD9257.h
#endif
void setDAC(enum DACINDEX ind, int val, int mV, int retval[]);
#ifdef CHIPTESTBOARDD
int isVLimitCompliant(int mV);
int getVLimit();
void setVLimit(int l);
int isVchipValid(int val);
int getVchip();
void setVchip(int val);
int getVChipToSet(enum DACINDEX ind, int val);
int getDACIndexFromADCIndex(enum ADCINDEX ind);
int getADCIndexFromDACIndex(enum DACINDEX ind);
int isPowerValid(int val);
int getPower();
void setPower(DACINDEX ind, int val);
#endif
/*#ifdef GOTTHARDD
void initDAC(int dac_addr, int value);
void clearDACSregister();
@ -162,6 +188,10 @@ void program_one_dac(int addr, int value);
u_int32_t putout(char *s);
#endif*/
int getADC(enum ADCINDEX ind);
#ifdef CHIPTESTBOARDD
int getVoltage(int idac);
int getCurrent(int idac);
#endif
int setHighVoltage(int val);
@ -198,8 +228,41 @@ void loadImage(enum imageType index, short int imageVals[]);
int readCounterBlock(int startACQ, short int counterVals[]);
int resetCounterBlock(int startACQ);
// jungfrau specific - pll, flashing firmware
// chip test board specific - powerchip, sendudp, pll, flashing firmware
#elif CHIPTESTBOARDD
int powerChip (int on);
int sendUDP(int enable);
void resetPLL();
void setPllReconfigReg(u_int32_t reg, u_int32_t val);
void configurePhase(CLKINDEX ind, int val);
int getPhase(CLKINDEX ind);
void configureFrequency(CLKINDEX ind, int val);
int getFrequency(CLKINDEX ind);
void configureSyncFrequency(CLKINDEX ind);
void setAdcOffsetRegister(int adc, int val);
void getAdcOffsetRegister(int adc);
extern void eraseFlash(); // programfpga.h
extern int startWritingFPGAprogram(FILE** filefp); // programfpga.h
extern void stopWritingFPGAprogram(FILE* filefp); // programfpga.h
extern int writeFPGAProgram(char* fpgasrc, size_t fsize, FILE* filefp); // programfpga.h
// ctb patterns
uint64_t writePatternIOControl(uint64_t word);
uint64_t writePatternClkControl(uint64_t word);
uint64_t readPatternWord(int addr);
uint64_t writePatternWord(int addr, uint64_t word);
int setPatternWaitAddress(int level, int addr);
uint64_t setPatternWaitTime(int level, uint64_t t);
void setPatternLoop(int level, int *startAddr, int *stopAddr, int *nLoop);
// jungfrau specific - powerchip, autocompdisable, clockdiv, asictimer, clock, pll, flashing firmware
#elif JUNGFRAUD
int powerChip (int on);
int autoCompDisable(int on);
void configureASICTimer();
int setClockDivider(int val);
int getClockDivider();
int setAdcPhase(int st);
int getPhase();
void resetPLL();
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val);
void configurePll();
@ -230,6 +293,7 @@ int getAllTrimbits();
int getBebFPGATemp();
int activate(int enable);
#endif
#if defined(JUNGFRAUD) || defined(EIGERD)
int setNetworkParameter(enum NETWORKINDEX mode, int value);
#endif
@ -254,6 +318,12 @@ int startReadOut();
#endif
enum runStatus getRunStatus();
void readFrame(int *ret, char *mess);
#ifdef CHIPTESTBOARDD
void unsetFifoReadStrobes();
void readSample();
int checkDataPresent();
int readFrameFromFifo();
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD)
u_int32_t runBusy();
#endif

2
slsDetectorServers/slsDetectorServer/slsDetectorServer.c
View File

@ -63,7 +63,7 @@ int main(int argc, char *argv[]){
FILE_LOG(logINFO, ("Detected phase shift of %d\n", phaseShift));
}
#endif
#ifdef JUNGFRAUD
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD)
else if(!strcasecmp(argv[i],"-update")){
FILE_LOG(logINFO, ("Detected update mode\n"));
debugflag = PROGRAMMING_MODE;

31
slsDetectorServers/slsDetectorServer/slsDetectorServer_defs.h
View File

@ -1,31 +0,0 @@
/*
* slsDetectorServer_defs.h
*
* Created on: Jan 24, 2013
* Author: l_maliakal_d
*/
#ifndef SLSDETECTORSERVER_DEFS_H_
#define SLSDETECTORSERVER_DEFS_H_
#include "sls_detector_defs.h"
#include <stdint.h>
/** This is only an example file!!! */
/*
#define GOODBYE (-200)
enum DAC_INDEX {examplesdac}
Hardware Definitions
#define NMAXMOD (1)
#define NMOD (1)
#define NCHAN (256 * 256)
#define NCHIP (4)
#define NADC (0)
#define NDAC (16)
#define NGAIN (0)
#define NOFFSET (0)
*/
#endif /* SLSDETECTORSERVER_DEFS_H_ */

671
slsDetectorServers/slsDetectorServer/slsDetectorServer_funcs.c
View File

@ -14,6 +14,8 @@ const enum detectorType myDetectorType = GOTTHARD;
const enum detectorType myDetectorType = EIGER;
#elif JUNGFRAUD
const enum detectorType myDetectorType = JUNGFRAU;
#elif CHIPTESTBOARDD
const enum detectorType myDetectorType = CHIPTESTBOARD;
#else
const enum detectorType myDetectorType = GENERIC;
#endif
@ -31,6 +33,11 @@ extern char mess[MAX_STR_LENGTH];
// Variables that will be exported
int sockfd = 0;
int debugflag = 0;
#ifdef CHIPTESTBOARDD
int dataBytes = 0;
uint16_t *ramValues = 0;
int nframes = 0;
#endif
// Local variables
int (*flist[NUM_DET_FUNCTIONS])(int);
@ -110,6 +117,42 @@ int decode_function(int file_des) {
return ret;
}
const char* getTimerName(enum timerIndex ind) {
switch (ind) {
case FRAME_NUMBER: return "frame_number";
case ACQUISITION_TIME: return "acquisition_time";
case FRAME_PERIOD: return "frame_period";
case DELAY_AFTER_TRIGGER: return "delay_after_trigger";
case GATES_NUMBER: return "gates_number";
case CYCLES_NUMBER: return "cycles_number";
case ACTUAL_TIME: return "actual_time";
case MEASUREMENT_TIME: return "measurement_time";
case PROGRESS: return "progress";
case MEASUREMENTS_NUMBER: return "measurements_number";
case FRAMES_FROM_START: return "frames_from_start";
case FRAMES_FROM_START_PG: return "frames_from_start_pg";
case SAMPLES_JCTB: return "samples_jctb";
case SUBFRAME_ACQUISITION_TIME: return "subframe_acquisition_time";
case SUBFRAME_DEADTIME: return "subframe_deadtime";
case STORAGE_CELL_NUMBER: return "storage_cell_number";
default: return "unknown_timer";
}
}
const char* getSpeedName(enum speedVariable ind) {
switch (ind) {
case CLOCK_DIVIDER: return "clock_divider";
case PHASE_SHIFT: return "phase_shift";
case OVERSAMPLING: return "oversampling";
case ADC_CLOCK: return "adc_clock";
case ADC_PHASE: return "adc_phase";
case ADC_PIPELINE: return "adc_pipeline";
case DBIT_CLOCK: return "dbit_clock";
case DBIT_PHASE: return "dbit_phase";
case DBIT_PIPELINE: return "dbit_pipeline";
default: return "unknown_speed";
}
}
const char* getFunctionName(enum detFuncs func) {
switch (func) {
@ -538,12 +581,6 @@ int set_dac(int file_des) {
enum DACINDEX serverDacIndex = 0;
// check if dac exists for this detector
#ifdef JUNGFRAUD
if ((ind != HV_NEW) && (ind >= NDAC_OLDBOARD)) { //for compatibility with old board
modeNotImplemented("Dac Index", (int)ind);
} else
serverDacIndex = ind;
#else
switch (ind) {
#ifdef GOTTHARDD
case G_VREF_DS :
@ -570,72 +607,104 @@ int set_dac(int file_des) {
case G_IB_TESTC:
serverDacIndex = IB_TESTC;
break;
case HV_POT:
break;
case HIGH_VOLTAGE:
break;
#elif EIGERD
case TRIMBIT_SIZE:
serverDacIndex = VTR;
serverDacIndex = VTR;
break;
case THRESHOLD:
serverDacIndex = VTHRESHOLD;
serverDacIndex = VTHRESHOLD;
break;
case E_SvP:
serverDacIndex = SVP;
serverDacIndex = SVP;
break;
case E_SvN:
serverDacIndex = SVN;
serverDacIndex = SVN;
break;
case E_Vtr:
serverDacIndex = VTR;
serverDacIndex = VTR;
break;
case E_Vrf:
serverDacIndex = VRF;
serverDacIndex = VRF;
break;
case E_Vrs:
serverDacIndex = VRS;
serverDacIndex = VRS;
break;
case E_Vtgstv:
serverDacIndex = VTGSTV;
serverDacIndex = VTGSTV;
break;
case E_Vcmp_ll:
serverDacIndex = VCMP_LL;
serverDacIndex = VCMP_LL;
break;
case E_Vcmp_lr:
serverDacIndex = VCMP_LR;
serverDacIndex = VCMP_LR;
break;
case E_cal:
serverDacIndex = CAL;
serverDacIndex = CAL;
break;
case E_Vcmp_rl:
serverDacIndex = VCMP_RL;
serverDacIndex = VCMP_RL;
break;
case E_Vcmp_rr:
serverDacIndex = VCMP_RR;
serverDacIndex = VCMP_RR;
break;
case E_rxb_rb:
serverDacIndex = RXB_RB;
serverDacIndex = RXB_RB;
break;
case E_rxb_lb:
serverDacIndex = RXB_LB;
serverDacIndex = RXB_LB;
break;
case E_Vcp:
serverDacIndex = VCP;
serverDacIndex = VCP;
break;
case E_Vcn:
serverDacIndex = VCN;
serverDacIndex = VCN;
break;
case E_Vis:
serverDacIndex = VIS;
serverDacIndex = VIS;
break;
case HV_NEW:
case HIGH_VOLTAGE:
case IO_DELAY:
break;
#elif CHIPTESTBOARDD
case ADC_VPP:
case HIGH_VOLTAGE:
break;
case V_POWER_A:
serverDacIndex = D_PWR_A;
break;
case V_POWER_B:
serverDacIndex = D_PWR_B;
break;
case V_POWER_C:
serverDacIndex = D_PWR_C;
break;
case V_POWER_D:
serverDacIndex = D_PWR_D;
break;
case V_POWER_IO:
serverDacIndex = D_PWR_IO;
break;
case V_POWER_CHIP:
serverDacIndex = D_PWR_CHIP;
break;
#endif
default:
modeNotImplemented("Dac Index", (int)ind);
#ifdef JUNGFRAUD
if ((ind == HIGH_VOLTAGE) || (ind < NDAC_OLDBOARD)) { //for compatibility with old board
serverDacIndex = ind;
break;
}
#elif CHIPTESTBOARDD
if (ind < NDAC_ONLY) {
serverDacIndex = ind;
break;
}
#endif
modeNotImplemented("Dac Index", (int)ind);
break;
}
#endif
// index exists
if (ret == OK) {
@ -644,9 +713,23 @@ int set_dac(int file_des) {
(mV ? "mV" : "dac units")));
// set & get
if ((val == -1) || ((val != -1) && (Server_VerifyLock() == OK))) {
if ((val == -1) || (Server_VerifyLock() == OK)) {
switch(ind) {
// adc vpp
#ifdef CHIPTESTBOARDD
case ADC_VPP:
if (val < 0 || val > getMaxValidVref()) {
ret = FAIL;
strcpy(mess,"Could not set dac. Adc Vpp value should be between 0 and %d\n", maxValidVref());
FILE_LOG(logERROR,(mess));
} else {
setVrefVoltage(val);
retval = val; // cannot read
}
break;
#endif
// io delay
#ifdef EIGERD
case IO_DELAY:
@ -657,10 +740,12 @@ int set_dac(int file_des) {
#endif
// high voltage
case HV_POT:
case HV_NEW:
case HIGH_VOLTAGE:
retval[0] = setHighVoltage(val);
FILE_LOG(logDEBUG1, ("High Voltage: %d\n", retval[0]));
#if defined(JUNGFRAUD) || defined (CHIPTESTBOARDD)
validate(val, retval[0], "set high voltage", DEC);
#endif
#ifdef GOTTHARDD
if (retval[0] == -1) {
ret = FAIL;
@ -685,9 +770,90 @@ int set_dac(int file_des) {
#endif
break;
// power, vlimit
#ifdef CHIPTESTBOARDD
case V_POWER_A:
case V_POWER_B:
case V_POWER_C:
case V_POWER_D:
case V_POWER_IO:
if (!mV) {
ret = FAIL;
sprintf(mess,"Could not set power. Power regulator %d should be in mV and not dac units.\n", ind);
FILE_LOG(logERROR,(mess));
} else if (checkVLimitCompliant() == FAIL) {
ret = FAIL;
sprintf(mess,"Could not set power. Power regulator %d exceeds voltage limit %d.\n", ind, getVLimit());
FILE_LOG(logERROR,(mess));
} else if (!isPowerValid(val)) {
ret = FAIL;
sprintf(mess,"Could not set power. Power regulator %d should be between %d and %d mV\n", POWER_RGLTR_MIN, POWER_RGLTR_MAX);
FILE_LOG(logERROR,(mess));
} else {
if (val != -1)
setPower(serverDacIndex, val);
retval[0] = getPower(serverDacIndex);
FILE_LOG(logDEBUG1, ("Power regulator(%d): %d\n", ind, retval[0]));
validate(val, retval[0], "set power regulator", DEC);
}
break;
case V_POWER_CHIP:
if (!mV) {
ret = FAIL;
sprintf(mess,"Could not set Vchip. Should be in mV and not dac units.\n");
FILE_LOG(logERROR,(mess));
} else if (!isVchipValid(val)) {
ret = FAIL;
sprintf(mess,"Could not set Vchip. Should be between %d and %d mV\n", VCHIP_MIN_MV, VCHIP_MAX_MV);
FILE_LOG(logERROR,(mess));
} else {
if (val >= 0) // not letting user set to -100, it will affect setting
setVchip(val);
retval[0] = getVchip();
FILE_LOG(logDEBUG1, ("Vchip: %d\n", retval[0]));
validate(val, retval[0], "set vchip", DEC);
}
break;
case VLIMIT:
if (!mV) {
ret = FAIL;
strcpy(mess,"Could not set power. VLimit should be in mV and not dac units.\n");
FILE_LOG(logERROR,(mess));
} else {
if (val >= 0)
setVLimit(val);
retval[0] = getVLimit();
FILE_LOG(logDEBUG1, ("VLimit: %d\n", retval[0]));
validate(val, retval[0], "set vlimit", DEC);
}
break;
#endif
// dacs
default:
setDAC(serverDacIndex, val, mV, retval);
if (mV && val > MAX_DAC_VOLTAGE_VALUE) {
ret = FAIL;
sprintf(mess,"Could not set dac %d to value %d. Allowed limits (0 - %d mV).\n", ind, val, MAX_DAC_VOLTAGE_VALUE);
FILE_LOG(logERROR,(mess));
} else if (!mV && val > MAX_DAC_UNIT_VALUE ) {
ret = FAIL;
sprintf(mess,"Could not set dac %d to value %d. Allowed limits (0 - %d dac units).\n", ind, val, MAX_DAC_UNIT_VALUE);
FILE_LOG(logERROR,(mess));
} else {
#ifdef CHIPTESTBOARDD
if ((mV && checkVLimitCompliant() == FAIL) ||
(!mv && checkVLimitCompliant(dacToVoltage(val)) == FAIL)) {
ret = FAIL;
sprintf(mess,"Could not set dac %d to value %d. "
"Exceeds voltage limit %d.\n",
ind, (mV ? val : dacToVoltage(val)), getVLimit());
FILE_LOG(logERROR,(mess));
} else
#endif
setDAC(serverDacIndex, val, mV, retval);
}
#ifdef EIGERD
if (val != -1) {
//changing dac changes settings to undefined
@ -779,8 +945,44 @@ int get_adc(int file_des) {
case TEMPERATURE_FPGA3:
serverAdcIndex = TEMP_FPGAFEBR;
break;
#elif CHIPTESTBOARDD
case V_POWER_A:
serverAdcIndex = V_PWR_A;
break;
case V_POWER_B:
serverAdcIndex = V_PWR_B;
break;
case V_POWER_C:
serverAdcIndex = V_PWR_C;
break;
case V_POWER_D:
serverAdcIndex = V_PWR_D;
break;
case V_POWER_IO:
serverAdcIndex = V_PWR_IO;
break;
case I_POWER_A:
serverAdcIndex = I_PWR_A;
break;
case I_POWER_B:
serverAdcIndex = I_PWR_B;
break;
case I_POWER_C:
serverAdcIndex = I_PWR_C;
break;
case I_POWER_D:
serverAdcIndex = I_PWR_D;
break;
case I_POWER_IO:
serverAdcIndex = I_PWR_IO;
break;
#endif
default:
#ifdef CHIPTESTBOARDD
if (ind >= SLOW_ADC_START_INDEX && ind <= SLOW_ADC_END_INDEX) {
break;
}
#endif
modeNotImplemented("Adc Index", (int)ind);
break;
}
@ -862,6 +1064,10 @@ int set_module(int file_des) {
memset(mess, 0, sizeof(mess));
enum detectorSettings retval = -1;
#ifdef CHIPTESTBOARDD
functionNotImplemented();
#else
sls_detector_module module;
int *myDac = NULL;
int *myChan = NULL;
@ -959,6 +1165,8 @@ int set_module(int file_des) {
}
if (myChan != NULL) free(myChan);
if (myDac != NULL) free(myDac);
#endif
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
}
@ -985,6 +1193,10 @@ int get_module(int file_des) {
} else
module.dacs = myDac;
#ifdef CHIPTESTBOARDD
functionNotImplemented();
#endif
#ifdef EIGERD
// allocate chans
if (ret == OK) {
@ -1034,10 +1246,14 @@ int set_settings(int file_des) {
if (receiveData(file_des, &isett, sizeof(isett), INT32) < 0)
return printSocketReadError();
#ifdef CHIPTESTBOARDD
functionNotImplemented();
#else
FILE_LOG(logDEBUG1, ("Setting settings %d\n", isett));
//set & get
if ((isett == GET_SETTINGS) || ((isett != GET_SETTINGS) && (Server_VerifyLock() == OK))) {
if ((isett == GET_SETTINGS) || (Server_VerifyLock() == OK)) {
// check index
switch(isett) {
@ -1083,6 +1299,8 @@ int set_settings(int file_des) {
#endif
}
}
#endif
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
}
@ -1229,6 +1447,35 @@ int read_all(int file_des) {
FILE_LOG(logDEBUG1, ("Reading all frames\n"));
// only set
if (Server_VerifyLock() == OK) {
#ifdef CHIPTESTBOARDD
// read from fifo enabled
if (!sendUDP(-1)) {
nframes = 0;
// keep reading frames
while(readFrameFromFifo() == OK) {
// (to the receiver)
Server_SendResult(file_des, INT32, NO_UPDATE, ramValues, dataBytes);// (or get as arg first)send number of bytes (dataBytes) first //FIXME
FILE_LOG(logDEBUG1, "Frame %d sent\n", nframes);
++nframes;
}
// finished readng frames
// frames left to give status
int64_t retval = getTimeLeft(FRAME_NUMBER) + 2;
if ( retval > 1) {
ret = FAIL;
sprintf(mess,"No data and run stopped: %lld frames left\n",(long long int)retval);
FILE_LOG(logERROR, (mess));
} else {
ret = OK; // send number of bytes (8) first to acknowledge finish of acquisition //FIXME
FILE_LOG(logINFOGREEN, ("Acquisition successfully finished\n"));
}
Server_SendResult(file_des, INT32, UPDATE, NULL, 0); // to the client
}
// read from receiver
else
#endif
readFrame(&ret, mess);
}
return Server_SendResult(file_des, INT32, UPDATE, NULL, 0);
@ -1249,21 +1496,26 @@ int set_timer(int file_des) {
return printSocketReadError();
enum timerIndex ind = (int)args[0];
int64_t tns = args[1];
char timerName[20] = {0};
strcpy(timerName, getTimerName(ind));
#ifdef EIGERD
int64_t subexptime = 0;
#endif
FILE_LOG(logDEBUG1, ("Setting timer index %d to %lld ns\n", ind, tns));
FILE_LOG(logDEBUG1, ("Setting timer %s(%d) to %lld ns\n", ind, timerName, tns));
// set & get
if ((tns == -1) || ((tns != -1) && (Server_VerifyLock() == OK))) {
if ((tns == -1) || (Server_VerifyLock() == OK)) {
// check index
switch (ind) {
case FRAME_NUMBER:
#ifndef CHIPTESTBOARDD
case ACQUISITION_TIME:
#endif
case FRAME_PERIOD:
case CYCLES_NUMBER:
#if defined(GOTTHARDD) || defined(JUNGFRAUD)
case SAMPLES_JCTB:
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD)
case DELAY_AFTER_TRIGGER:
#endif
retval = setTimer(ind, tns);
@ -1305,20 +1557,30 @@ int set_timer(int file_des) {
break;
#endif
default:
modeNotImplemented("Timer index", (int)ind);
modeNotImplemented(timerName, (int)ind);
break;
}
// validate
sprintf(timerName, "set %s", timerName);
#ifdef EIGERD
validate64(tns, retval, "set timer", DEC); // copied to server, not read from detector register
validate64(tns, retval, timerName, DEC); // copied to server, not read from detector register
#else
switch(ind) {
case FRAME_NUMBER:
case CYCLES_NUMBER:
case STORAGE_CELL_NUMBER:
validate64(tns, retval, "set timer", DEC); // no conversion, so all good
validate64(tns, retval, timerName, DEC); // no conversion, so all good
break;
case SAMPLES_JCTB:
if (retval == -1) {
ret = FAIL;
retval = setTimer(ind, -1);
sprintf(mess, "Could not set samples to %lld. Could not allocate RAM\n",
(long long unsigned int)tns);
FILE_LOG(logERROR,(mess));
} else
validate64(tns, retval, timerName, DEC); // no conversion, so all good
case ACQUISITION_TIME:
case FRAME_PERIOD:
case DELAY_AFTER_TRIGGER:
@ -1327,11 +1589,12 @@ int set_timer(int file_des) {
// losing precision due to conversion to clock (also gotthard master delay is different)
if (validateTimer(ind, tns, retval) == FAIL) {
ret = FAIL;
sprintf(mess, "Could not set timer. Set %lld, but read %lld\n",
sprintf(mess, "Could not %s. Set %lld, but read %lld\n", timerName,
(long long unsigned int)tns, (long long unsigned int)retval);
FILE_LOG(logERROR,(mess));
}
break;
default:
break;
}
@ -1378,10 +1641,21 @@ int get_time_left(int file_des) {
case FRAMES_FROM_START_PG:
case ACTUAL_TIME:
case MEASUREMENT_TIME:
case FRAME_NUMBER:
case FRAME_PERIOD:
case DELAY_AFTER_TRIGGER:
case CYCLES_NUMBER:
#elif GOTTHARDD
case ACQUISITION_TIME:
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD)
case FRAME_NUMBER:
case FRAME_PERIOD:
case DELAY_AFTER_TRIGGER:
case CYCLES_NUMBER:
#elif CHIPTESTBOARDD
case FRAMES_FROM_START:
case FRAMES_FROM_START_PG:
case ACTUAL_TIME:
case MEASUREMENT_TIME:
case FRAME_NUMBER:
case FRAME_PERIOD:
case DELAY_AFTER_TRIGGER:
@ -1414,7 +1688,7 @@ int set_dynamic_range(int file_des) {
FILE_LOG(logDEBUG1, ("Setting dr to %d\n", dr));
// set & get
if ((dr == -1) || ((dr != -1) && (Server_VerifyLock() == OK))) {
if ((dr == -1) || (Server_VerifyLock() == OK)) {
#ifdef EIGERD
int old_dr = setDynamicRange(-1);
@ -1480,7 +1754,7 @@ int set_readout_flags(int file_des) {
functionNotImplemented();
#else
// set & get
if ((arg == GET_READOUT_FLAGS) || ((arg != GET_READOUT_FLAGS) && (Server_VerifyLock() == OK))) {
if ((arg == GET_READOUT_FLAGS) || (Server_VerifyLock() == OK)) {
switch(arg) {
case STORE_IN_RAM:
@ -1493,6 +1767,13 @@ int set_readout_flags(int file_des) {
retval = setReadOutFlags(arg);
FILE_LOG(logDEBUG1, ("Read out flags: 0x%x\n", retval));
validate((int)arg, (int)(retval & arg), "set readout flag", HEX);
#ifdef CHIPTESTBOARDD
if (retval == -2) {
ret = FAIL;
sprintf(mess, "Readout Flags failed. Cannot allocate RAM\n");
FILE_LOG(logERROR,(mess));
}
#endif
break;
default:
modeNotImplemented("Read out flag index", (int)arg);
@ -1542,20 +1823,26 @@ int set_roi(int file_des) {
}
}
#ifndef GOTTHARDD
#if !defined(GOTTHARDD) || !defined(CHIPTESTBOARDD)
functionNotImplemented();
#else
// set & get
if ((narg == GET_READOUT_FLAGS) || ((narg != GET_READOUT_FLAGS) && (Server_VerifyLock() == OK))) {
if (narg > 1) {
if ((narg == GET_READOUT_FLAGS) || (Server_VerifyLock() == OK)) {
if (myDetectorType == GOTTHARDD && narg > 1) {
ret = FAIL;
strcpy(mess,"Can not set more than one ROI per module.\n");
FILE_LOG(logERROR,(mess));
} else {
retval = setROI(narg, arg, &nretval, &ret);
if (ret == FAIL) {
sprintf(mess,"Could not set all roi. "
"Set %d rois, but read %d rois\n", narg, nretval);
if (nretval == -1) // chip test board
sprintf(mess,"Could not set ROI. Max ROI level (100) reached!\n");
else if (nretval == -2)
sprintf(mess, "Could not set ROI. Could not allocate RAM\n",
(long long unsigned int)tns);
else
sprintf(mess,"Could not set all roi. "
"Set %d rois, but read %d rois\n", narg, nretval);
FILE_LOG(logERROR,(mess));
}
FILE_LOG(logDEBUG1, ("nRois: %d\n", nretval));
@ -1598,31 +1885,52 @@ int set_speed(int file_des) {
#else
enum speedVariable ind = args[0];
int val = args[1];
FILE_LOG(logDEBUG1, ("Setting speed index %d to %d\n", ind, val));
int GET_VAL = -1;
if ((ind == PHASESHIFT) || (val == ADC_PHASE) || (val == DBIT_PHASE))
GET_VAL = 100000;
// set & get
if ((val == -1) || ((val != -1) && (Server_VerifyLock() == OK))) {
// check index
switch(ind) {
char speedName[20] = {0};
strcpy(speedName, getSpeedName(ind));
FILE_LOG(logDEBUG1, ("Setting speed index %s (%d) to %d\n", speedName, ind, val));
// check index
switch(ind) {
#ifdef JUNGFRAUD
case ADC_PHASE:
retval = adcPhase(val);
FILE_LOG(logDEBUG1, ("ADc Phase: %d\n", retval));
if (val != 100000) {
validate(val, retval, "set adc phase ", DEC);
}
break;
case ADC_PHASE:
#elif CHIPTESTBOARDD
case ADC_PHASE:
case PHASE_SHIFT:
case DBIT_PHASE:
case ADC_CLOCK:
case DBIT_CLOCK:
case ADC_PIPELINE:
case DBIT_PIPELINE:
#endif
case CLOCK_DIVIDER:
retval = setSpeed(val);
FILE_LOG(logDEBUG1, ("Clock: %d\n", retval));
validate(val, retval, "set clock ", DEC);
break;
default:
modeNotImplemented("Speed index", (int)ind);
break;
}
}
case CLOCK_DIVIDER:
break;
default:
modeNotImplemented(speedName, (int)ind);
break;
}
if (ret == OK) {
// set
if ((val != GET_VAL) && (Server_VerifyLock() == OK))
setSpeed(ind, val);
// get
retval = getSpeed(ind);
FILE_LOG(logDEBUG1, ("%s: %d\n", speedName, retval));
// validate
if (GET_VAL == -1) {
char validateName[20] = {0};
sprintf(validateName, "set %s", speedName);
validate(val, retval, validateName, DEC);
} else if (ret == OK && val != GET_VAL && retval != val ) {
ret = FAIL;
sprintf(mess, "Could not set %s. Set %d, but read %d\n", speedName, val, retval);
FILE_LOG(logERROR,(mess));
}
}
#endif
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
@ -2080,7 +2388,7 @@ int enable_ten_giga(int file_des) {
functionNotImplemented();
#else
// set & get
if ((arg == -1) || ((arg != -1) && (Server_VerifyLock() == OK))) {
if ((arg == -1) || (Server_VerifyLock() == OK)) {
retval = enableTenGigabitEthernet(arg);
FILE_LOG(logDEBUG1, ("10GbE: %d\n", retval));
validate(arg, retval, "enable/disable 10GbE", DEC);
@ -2127,7 +2435,208 @@ int set_all_trimbits(int file_des) {
int set_ctb_pattern(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int retval32 = -1;
int64_t retval64 = -1;
int retvals[3] = {-1, -1, -1};
int mode = -1;
// mode 0: control or word
int addr = -1;
uint64_t word = -1;
// mode 1: pattern loop
int loopLevel = -1;
int startAddr = -1;
int stopAddr = -1;
int numLoops = -1;
// mode 2: wait address
// mode 3: wait time
uint64_t timeval = -1;
// mode 4: set word
uint64_t pattern[MAX_PATTERN_LENGTH] = {0};
if (receiveData(file_des, &mode, sizeof(mode), INT32) < 0)
return printSocketReadError();
switch (mode) {
case 0:// control or word
if (receiveData(file_des, &addr, sizeof(addr), INT32) < 0)
return printSocketReadError();
if (receiveData(file_des, &word, sizeof(word), INT64) < 0)
return printSocketReadError();
break;
case 1:// pattern loop
if (receiveData(file_des, &loopLevel, sizeof(loopLevel), INT32) < 0)
return printSocketReadError();
if (receiveData(file_des, &startAddr, sizeof(startAddr), INT32) < 0)
return printSocketReadError();
if (receiveData(file_des, &stopAddr, sizeof(stopAddr), INT32) < 0)
return printSocketReadError();
if (receiveData(file_des, &numLoops, sizeof(numLoops), INT32) < 0)
return printSocketReadError();
break;
case 2: // wait address
if (receiveData(file_des, &loopLevel, sizeof(loopLevel), INT32) < 0)
return printSocketReadError();
if (receiveData(file_des, &addr, sizeof(addr), INT32) < 0)
return printSocketReadError();
break;
case 3:// wait time
if (receiveData(file_des, &loopLevel, sizeof(loopLevel), INT32) < 0)
return printSocketReadError();
if (receiveData(file_des, &t, sizeof(t), INT32) < 0)
return printSocketReadError();
case 4:// set word
if (receiveData(file_des, &pattern, sizeof(pattern), INT64) < 0)
return printSocketReadError();
break;
default:
break;
}
#ifndef CHIPTESTBOARDD
functionNotImplemented();
#else
FILE_LOG(logDEBUG1, ("Setting Pattern: mode %d\n", mode));
char tempName[100];
memset(tempName, 0, 100);
int failCount = 0;
switch (mode) {
case 0:
// control or word
if ((word == -1) || (Server_VerifyLock() == OK)) {
// address for set word should be valid (if not -1 or -2, it goes to setword)
if (addr < -2 || addr > MAX_PATTERN_LENGTH) {
ret = FAIL;
sprintf(mess, "Cannot set Pattern (Word, addr:%d). Addr must be less than %d\n",
addr, MAX_PATTERN_LENGTH);
FILE_LOG(logERROR, (mess));
} else {
switch (addr) {
case -1:
strcpy(tempName, "Pattern (I/O Control Register)");
FILE_LOG(logDEBUG1, ("Setting %s to 0x%llx\n", tempName, (long long int) word));
retval64 = writePatternIOControl(word);
break;
case -2:
strcpy(tempName, "Pattern (Clock Control Register)");
FILE_LOG(logDEBUG1, ("Setting %s to 0x%llx\n", tempName, (long long int) word));
retval64 = writePatternClkControl(word);
break;
default:
sprintf(tempName, "Pattern (Word, addr:0x%x)", addr);
FILE_LOG(logDEBUG1, ("Setting %s to 0x%llx\n", tempName, (long long int) word));
retval64 = writePatternWord(word);
break;
}
FILE_LOG(logDEBUG1, ("%s: 0x%llx\n", tempName, (long long int)retval64));
validate64(word, retval64, tempName, HEX);
}
}
return Server_SendResult(file_des, INT64, UPDATE, retval64, sizeof(retval64);
// pattern loop
case 1:
if (loopLevel < -1 || loopLevel > 2) { // -1 complete pattern
modeNotImplemented("Pattern (Pattern Loop) Level", loopLevel);
}
// level 0-2, addr upto patternlength + 1
else if ((level != -1) && (startAddr > (MAX_PATTERN_LENGTH + 1) || stopAddr > (MAX_PATTERN_LENGTH + 1))) {
ret = FAIL;
sprintf(mess, "Cannot set Pattern (Pattern Loop, level:%d, addr:%d). Addr must be less than %d\n",
level, addr, MAX_PATTERN_LENGTH + 1);
FILE_LOG(logERROR, (mess));
}
//level -1, addr upto patternlength
else if ((level == -1) && (startAddr > MAX_PATTERN_LENGTH || stopAddr > MAX_PATTERN_LENGTH)) {
ret = FAIL;
sprintf(mess, "Cannot set Pattern (Pattern Loop, complete pattern, addr:%d). Addr must be less than %d\n",
addr, MAX_PATTERN_LENGTH);
FILE_LOG(logERROR, (mess));
}
else if ((startAddr == -1 && stopAddr == -1 && numLoops == -1) || (Server_VerifyLock() == OK)) {
setPatternLoop(loopLevel, &startAddr, &stopAddr, &numLoops);
}
retval[0] = startAddr;
retval[1] = stopAddr;
retval[2] = numLoops;
return Server_SendResult(file_des, INT32, UPDATE, retvals, sizeof(retvals);
case 2:
// wait address
if ((addr == -1) || (Server_VerifyLock() == OK)) {
if (loopLevel < 0 || loopLevel > 2) {
modeNotImplemented("Pattern (Wait Address) Level", loopLevel);
} else if (addr > (MAX_PATTERN_LENGTH + 1)) {
ret = FAIL;
sprintf(mess, "Cannot set Pattern (Wait Address, addr:%d). Addr must be less than %d\n",
addr, MAX_PATTERN_LENGTH + 1);
FILE_LOG(logERROR, (mess));
} else {
sprintf(tempName, "Pattern (Wait Address, Level:%d)", loopLevel);
FILE_LOG(logDEBUG1, ("Setting %s to 0x%x\n", tempName, addr));
retval32 = setPatternWaitAddress(loopLevel, addr);
FILE_LOG(logDEBUG1, ("%s: 0x%x\n", tempName, retval32));
validate(addr, retval32, tempName, HEX);
}
}
return Server_SendResult(file_des, INT32, UPDATE, retval32, sizeof(retval32);
case 3:
// wait time
if ((timeval == -1) || (Server_VerifyLock() == OK)) {
if (loopLevel < 0 || loopLevel > 2) {
modeNotImplemented("Pattern (Wait Time) Level", loopLevel);
} else {
sprintf(tempName, "Pattern (Wait Time, Level:%d)", loopLevel);
FILE_LOG(logDEBUG1, ("Setting %s to 0x%llx\n", tempName, (long long int)timeval));
retval64 = setPatternWaitTime(loopLevel, timeval);
FILE_LOG(logDEBUG1, ("%s: 0x%llx\n", tempName, (long long int)retval64));
validate64(timeval, retval64, tempName, HEX);
}
}
return Server_SendResult(file_des, INT64, UPDATE, retval64, sizeof(retval64);
case 4:
// set word array(set only)
if (Server_VerifyLock() == OK) {
FILE_LOG(logDEBUG1, ("Setting Pattern (Word Array)\n"));
failCount = 0;
int iaddr = 0; // if warning change to addr // FIXME
for (iaddr = 0; iaddr < MAX_PATTERN_LENGTH; ++iaddr) {
sprintf(tempName, "Pattern (Word Array, addr:%d)", iaddr);
FILE_LOG(logDEBUG1, ("Setting %s to 0x%llx\n", tempName, (long long int) pattern[iaddr]));
retval64 = writePatternWord(iaddr, pattern[iaddr]);//FIXME: earlier was word, but makes no sense (random value)
FILE_LOG(logDEBUG1, ("%s: 0x%llx\n", tempName, (long long int)retval64));
validate64(pattern[iaddr], retval64, tempName, HEX);
if (ret == FAIL) {
++failCount;
ret = OK;
}
}
if (failCount) {
ret = FAIL;
sprintf(mess, "Could not set Pattern (Word Array) %d addresses.\n", failCount);
FILE_LOG(logERROR,(mess));
}
}
return Server_SendResult(file_des, INT64, UPDATE, NULL, 0);
default:
modeNotImplemented("Pattern mode index", mode);
break;
}
#endif
return Server_SendResult(file_des, INT32, UPDATE, NULL, 0);
}
@ -2364,7 +2873,7 @@ int set_network_parameter(int file_des) {
enum NETWORKINDEX serverIndex = 0;
// set & get
if ((value == -1) || ((value != -1) && (Server_VerifyLock() == OK))) {
if ((value == -1) || (Server_VerifyLock() == OK)) {
// check index
switch (mode) {
#ifdef EIGERD
@ -2572,7 +3081,7 @@ int power_chip(int file_des) {
functionNotImplemented();
#else
// set & get
if ((arg == -1) || ((arg != -1) && (Server_VerifyLock() == OK))) {
if ((arg == -1) || (Server_VerifyLock() == OK)) {
retval = powerChip(arg);
FILE_LOG(logDEBUG1, ("Power chip: %d\n", retval));
validate(arg, retval, "power on/off chip", DEC);
@ -2605,7 +3114,7 @@ int set_activate(int file_des) {
functionNotImplemented();
#else
// set & get
if ((arg == -1) || ((arg != -1) && (Server_VerifyLock() == OK))) {
if ((arg == -1) || (Server_VerifyLock() == OK)) {
retval = activate(arg);
FILE_LOG(logDEBUG1, ("Activate: %d\n", retval));
validate(arg, retval, "set activate", DEC);
@ -2655,7 +3164,7 @@ int threshold_temp(int file_des) {
functionNotImplemented();
#else
// set & get
if ((arg == -1) || ((arg != -1) && (Server_VerifyLock() == OK))) {
if ((arg == -1) || (Server_VerifyLock() == OK)) {
if (arg > MAX_THRESHOLD_TEMP_VAL) {
ret = FAIL;
sprintf(mess,"Threshold Temp %d should be in range: 0 - %d\n",
@ -2689,7 +3198,7 @@ int temp_control(int file_des) {
functionNotImplemented();
#else
// set & get
if ((arg == -1) || ((arg != -1) && (Server_VerifyLock() == OK))) {
if ((arg == -1) || (Server_VerifyLock() == OK)) {
retval = setTemperatureControl(arg);
FILE_LOG(logDEBUG1, ("Temperature control: %d\n", retval));
validate(arg, retval, "set temperature control", DEC);
@ -2715,7 +3224,7 @@ int temp_event(int file_des) {
functionNotImplemented();
#else
// set & get
if ((arg == -1) || ((arg != -1) && (Server_VerifyLock() == OK))) {
if ((arg == -1) || (Server_VerifyLock() == OK)) {
retval = setTemperatureEvent(arg);
FILE_LOG(logDEBUG1, ("Temperature event: %d\n", retval));
validate(arg, retval, "set temperature event", DEC);
@ -2742,7 +3251,7 @@ int auto_comp_disable(int file_des) {
functionNotImplemented();
#else
// set & get
if ((arg == -1) || ((arg != -1) && (Server_VerifyLock() == OK))) {
if ((arg == -1) || (Server_VerifyLock() == OK)) {
retval = autoCompDisable(arg);
FILE_LOG(logDEBUG1, ("Auto comp disable: %d\n", retval));
validate(arg, retval, "set auto comp disable", DEC);
@ -2769,7 +3278,7 @@ int storage_cell_start(int file_des) {
functionNotImplemented();
#else
// set & get
if ((arg == -1) || ((arg != -1) && (Server_VerifyLock() == OK))) {
if ((arg == -1) || (Server_VerifyLock() == OK)) {
if (arg > MAX_STORAGE_CELL_VAL) {
ret = FAIL;
strcpy(mess,"Max Storage cell number should not exceed 15\n");

2
slsDetectorServers/slsDetectorServer/slsDetectorServer_funcs.h
View File

@ -7,6 +7,8 @@ enum numberMode {DEC, HEX};
int printSocketReadError();
void init_detector();
int decode_function(int);
const char* getTimerName(enum timerIndex ind);
const char* getSpeedName(enum speedVariable ind);
const char* getFunctionName(enum detFuncs func);
void function_table();
void functionNotImplemented();

46
slsDetectorServers/slsDetectorServer/slsDetector_stopServer.c
View File

@ -1,46 +0,0 @@
/* A simple server in the internet domain using TCP
The port number is passed as an argument */
#include "communication_funcs.h"
#include "slsDetectorFunctionList.h"/*#include "slsDetector_firmware.h" for the time being*/
#include "slsDetectorServer_defs.h"
#include <stdio.h>
#include <stdlib.h>
int sockfd;
int main(int argc, char *argv[])
{
int portno;
int retval=0;
int sd,fd;
portno = DEFAULT_PORTNO;
sd=bindSocket(portno); //defined in communication_funcs
if (getServerError(sd)) //defined in communication_funcs
return -1;
/* waits for connection */
while(retval!=GOODBYE) {
#ifdef VERBOSE
printf("\n");
#endif
#ifdef VERY_VERBOSE
printf("Stop server: waiting for client call\n");
#endif
fd=acceptConnection(sd); //defined in communication_funcs
retval=stopStateMachine();//defined in slsDetectorFirmare_funcs
closeConnection(fd); //defined in communication_funcs
}
exitServer(sd); //defined in communication_funcs
printf("Goodbye!\n");
return 0;
}

1
slsDetectorServers/slsDetectorServer/sls_detector_defs.h
View File

@ -1 +0,0 @@
../commonFiles/sls_detector_defs.h

1
slsDetectorServers/slsDetectorServer/sls_detector_funcs.h
View File

@ -1 +0,0 @@
../commonFiles/sls_detector_funcs.h

4
slsDetectorSoftware/multiSlsDetector/multiSlsDetector.cpp
View File

@ -1404,7 +1404,7 @@ int multiSlsDetector::setDAC(int val, dacIndex idac, int mV, int detPos) {
// multi
auto r = parallelCall(&slsDetector::setDAC, val, idac, mV);
if (idac != HV_NEW)
if (getDetectorsType() != EIGER || idac != HIGH_VOLTAGE)
return sls::minusOneIfDifferent(r);
// ignore slave values for hv (-999)
@ -3286,7 +3286,7 @@ int multiSlsDetector::dumpDetectorSetup(const std::string &fname, int level) {
names[nvar++] = "delay";
names[nvar++] = "clkdivider";
break;
case JUNGFRAUCTB:
case CHIPTESTBOARD:
names[nvar++] = "dac:0";
names[nvar++] = "dac:1";
names[nvar++] = "dac:2";

27
slsDetectorSoftware/slsDetector/slsDetector.cpp
View File

@ -328,7 +328,7 @@ void slsDetector::setDetectorSpecificParameters(detectorType type, detParameterL
list.nGappixelsX = 0;
list.nGappixelsY = 0;
break;
case JUNGFRAUCTB:
case CHIPTESTBOARD:
list.nChanX = 36;
list.nChanY = 1;
list.nChipX = 1;
@ -463,7 +463,7 @@ void slsDetector::initializeDetectorStructure(detectorType type) {
case JUNGFRAU:
thisDetector->receiver_framesPerFile = JFRAU_MAX_FRAMES_PER_FILE;
break;
case JUNGFRAUCTB:
case CHIPTESTBOARD:
thisDetector->receiver_framesPerFile = JFRAU_MAX_FRAMES_PER_FILE;
break;
default:
@ -500,7 +500,7 @@ void slsDetector::initializeDetectorStructure(detectorType type) {
thisDetector->dynamicRange/8;
// special for jctb
if (thisDetector->myDetectorType==JUNGFRAUCTB) {
if (thisDetector->myDetectorType==CHIPTESTBOARD) {
getTotalNumberOfChannels();
}
@ -885,7 +885,7 @@ std::string slsDetector::getDetectorType() {
int slsDetector::getTotalNumberOfChannels() {
FILE_LOG(logDEBUG1) << "Get total number of channels";
if (thisDetector->myDetectorType == JUNGFRAUCTB) {
if (thisDetector->myDetectorType == CHIPTESTBOARD) {
if (thisDetector->roFlags & DIGITAL_ONLY)
thisDetector->nChan[X] = 4;
else if (thisDetector->roFlags & ANALOG_AND_DIGITAL)
@ -1405,7 +1405,7 @@ int slsDetector::updateDetectorNoWait() {
n += controlSocket->ReceiveDataOnly(&i64, sizeof(i64));
thisDetector->timerValue[CYCLES_NUMBER] = i64;
if (thisDetector->myDetectorType == JUNGFRAUCTB) {
if (thisDetector->myDetectorType == CHIPTESTBOARD) {
n += controlSocket->ReceiveDataOnly(&i64, sizeof(i64));
if (i64 >= 0)
thisDetector->timerValue[SAMPLES_JCTB] = i64;
@ -1501,7 +1501,7 @@ int slsDetector::writeConfigurationFile(std::ofstream &outfile, multiSlsDetector
names.push_back("powerchip");
names.push_back("vhighvoltage");
break;
case JUNGFRAUCTB:
case CHIPTESTBOARD:
names.push_back("powerchip");
names.push_back("vhighvoltage");
break;
@ -2252,7 +2252,7 @@ int64_t slsDetector::setTimer(timerIndex index, int64_t t) {
// (a get can also change timer value, hence check difference)
if (oldtimer != thisDetector->timerValue[index]) {
// jctb: change samples, change databytes
if (thisDetector->myDetectorType == JUNGFRAUCTB) {
if (thisDetector->myDetectorType == CHIPTESTBOARD) {
if (index == SAMPLES_JCTB) {
setDynamicRange();
FILE_LOG(logINFO) << "Changing samples: data size = " << thisDetector->dataBytes;
@ -2438,7 +2438,7 @@ int slsDetector::setDynamicRange(int n) {
(thisDetector->nChip[Y] * thisDetector->nChan[Y] +
thisDetector->gappixels * thisDetector->nGappixels[Y]) *
retval / 8;
if (thisDetector->myDetectorType == JUNGFRAUCTB)
if (thisDetector->myDetectorType == CHIPTESTBOARD)
getTotalNumberOfChannels();
FILE_LOG(logDEBUG1) << "Data bytes " << thisDetector->dataBytes;
FILE_LOG(logDEBUG1) << "Data bytes including gap pixels" << thisDetector->dataBytesInclGapPixels;
@ -2480,9 +2480,6 @@ int slsDetector::getDataBytesInclGapPixels() {
int slsDetector::setDAC(int val, dacIndex index, int mV) {
if ((index == HV_NEW) && (thisDetector->myDetectorType == GOTTHARD))
index = HV_POT;
int fnum = F_SET_DAC;
int ret = FAIL;
int args[3] = {(int)index, mV, val};
@ -2991,7 +2988,7 @@ std::string slsDetector::setReceiver(std::string receiverIP) {
thisDetector->timerValue[SUBFRAME_ACQUISITION_TIME]);
setTimer(SUBFRAME_DEADTIME,thisDetector->timerValue[SUBFRAME_DEADTIME]);
}
if (thisDetector->myDetectorType == JUNGFRAUCTB)
if (thisDetector->myDetectorType == CHIPTESTBOARD)
setTimer(SAMPLES_JCTB,thisDetector->timerValue[SAMPLES_JCTB]);
setDynamicRange(thisDetector->dynamicRange);
if (thisDetector->myDetectorType == EIGER) {
@ -3503,7 +3500,7 @@ int slsDetector::setROI(int n,ROI roiLimits[]) {
}
int ret = sendROI(n,roiLimits);
if (thisDetector->myDetectorType == JUNGFRAUCTB)
if (thisDetector->myDetectorType == CHIPTESTBOARD)
getTotalNumberOfChannels();
return ret;
}
@ -3512,7 +3509,7 @@ int slsDetector::setROI(int n,ROI roiLimits[]) {
slsDetectorDefs::ROI* slsDetector::getROI(int &n) {
sendROI(-1,NULL);
n = thisDetector->nROI;
if (thisDetector->myDetectorType == JUNGFRAUCTB)
if (thisDetector->myDetectorType == CHIPTESTBOARD)
getTotalNumberOfChannels();
return thisDetector->roiLimits;
}
@ -3988,7 +3985,7 @@ int slsDetector::setStoragecellStart(int pos) {
int slsDetector::programFPGA(std::string fname) {
// only jungfrau implemented (client processing, so check now)
if (thisDetector->myDetectorType != JUNGFRAU && thisDetector->myDetectorType != JUNGFRAUCTB) {
if (thisDetector->myDetectorType != JUNGFRAU && thisDetector->myDetectorType != CHIPTESTBOARD) {
FILE_LOG(logERROR) << "Not implemented for this detector";
setErrorMask((getErrorMask())|(PROGRAMMING_ERROR));
return FAIL;

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