MY3.0:read and write Registers, frames, cycles, delay (#64)

* MY3.0:read and write Registers, frames, cycles, delay

* write pattern seems to work

* done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos)

* clk check for aquistition time

* clk check for aquistition time

* Update slsDetectorServer_defs.h

* Update slsDetectorFunctionList.c

slsDetectorServers/mythen3DetectorServer/CMakeLists.txt

@@ -3,11 +3,10 @@ add_executable(mythen3DetectorServer_virtual
     ../slsDetectorServer/src/slsDetectorServer.c
     ../slsDetectorServer/src/slsDetectorServer_funcs.c
     ../slsDetectorServer/src/communication_funcs.c
-    # ../slsDetectorServer/src/blackfin.c    
+    ../slsDetectorServer/src/nios.c    
-    ../slsDetectorServer/src/communication_funcs_UDP.c  
+    ../slsDetectorServer/src/communication_funcs_UDP.c        
     ../slsDetectorServer/src/DAC6571.c      
     ../slsDetectorServer/src/common.c 
-    ../slsDetectorServer/src/nios.c  
 )
 
 include_directories(

slsDetectorServers/mythen3DetectorServer/RegisterDefs.h

@@ -2,39 +2,159 @@
 #pragma once
 
 /* Definitions for FPGA*/
-#define MEM_MAP_SHIFT 1
+
+#define BASE_CONTROL                    (0x0)
+#define BASE_PATTERN_CONTROL            (0x200 )
+#define BASE_PATTERN_RAM                (0x10000 )
+
+/* Basic detector FPGA registers --------------------------------------------------*/
+/* FPGA Version register */
+#define FPGA_VERSION_REG                (0x04 + BASE_CONTROL)
+
+#define FPGA_COMPILATION_DATE_OFST		(0)
+#define FPGA_COMPILATION_DATE_MSK		(0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
+#define DETECTOR_TYPE_OFST   			(24)
+#define DETECTOR_TYPE_MSK   			(0x000000FF << DETECTOR_TYPE_OFST)
 
 
+/* Module Control Board Serial Number Register */
+#define MCB_SERIAL_NO_REG               (0x00 + BASE_CONTROL)
 
+/* API Version Register */
+#define API_VERSION_REG                 (0x08 + BASE_CONTROL)
+
+/* Fix pattern register */
+#define FIX_PATT_REG             	    (0x0C + BASE_CONTROL)
+#define FIX_PATT_VAL                    (0xACDC2019)
+
+/* Status register */
+#define STATUS_REG                      (0x10 + BASE_CONTROL)
 
 #ifdef VIRTUAL // until firmware is ready ----------------------------------
-/* Status register */
-#define STATUS_REG            			(0x01 << MEM_MAP_SHIFT)
-
 #define RUN_BUSY_OFST					(0)
 #define RUN_BUSY_MSK      				(0x00000001 << RUN_BUSY_OFST)
+#endif
 
-/* Set Cycles 64 bit register */
+/* Look at me register */
-#define SET_CYCLES_LSB_REG    			(0x02 << MEM_MAP_SHIFT)
+#define LOOK_AT_ME_REG          		(0x14 + BASE_CONTROL)	//Not used in firmware or software, good to play with
-#define SET_CYCLES_MSB_REG    			(0x03 << MEM_MAP_SHIFT)
 
-/* Set Frames 64 bit register */
-#define SET_FRAMES_LSB_REG   			(0x04 << MEM_MAP_SHIFT)
-#define SET_FRAMES_MSB_REG    			(0x05 << MEM_MAP_SHIFT)
 
-/* Set Period 64 bit register tT = T x 50 ns */
+/* Pattern Control FPGA registers --------------------------------------------------*/
-#define SET_PERIOD_LSB_REG    			(0x06 << MEM_MAP_SHIFT)
+/* Pattern status Register*/
-#define SET_PERIOD_MSB_REG    			(0x07 << MEM_MAP_SHIFT)
+#define PAT_STATUS_REG                  (0x00 + BASE_PATTERN_CONTROL)
 
-/* Set Exptime 64 bit register eEXP = Exp x 25 ns */
+/* Delay left 64bit Register */
-#define SET_EXPTIME_LSB_REG    			(0x08 << MEM_MAP_SHIFT)
+#define GET_DELAY_LSB_REG               (0x08 + BASE_PATTERN_CONTROL)
-#define SET_EXPTIME_MSB_REG    			(0x09 << MEM_MAP_SHIFT)
+#define GET_DELAY_MSB_REG               (0x0C + BASE_PATTERN_CONTROL)
 
-/* Get Cycles 64 bit register */
+/* Cycles left 64bit Register */
-#define GET_CYCLES_LSB_REG    			(0x0A << MEM_MAP_SHIFT)
+#define GET_CYCLES_LSB_REG              (0x10 + BASE_PATTERN_CONTROL)
-#define GET_CYCLES_MSB_REG    			(0x0B << MEM_MAP_SHIFT)
+#define GET_CYCLES_MSB_REG              (0x14 + BASE_PATTERN_CONTROL)
 
-/* Get Frames 64 bit register */
+/* Frames left 64bit Register */
-#define GET_FRAMES_LSB_REG   			(0x0C << MEM_MAP_SHIFT)
+#define GET_FRAMES_LSB_REG              (0x18 + BASE_PATTERN_CONTROL)
-#define GET_FRAMES_MSB_REG    			(0x0D << MEM_MAP_SHIFT)
+#define GET_FRAMES_MSB_REG              (0x1C + BASE_PATTERN_CONTROL)
-#endif
+
+/* Period left 64bit Register */
+#define GET_PERIOD_LSB_REG              (0x20 + BASE_PATTERN_CONTROL)
+#define GET_PERIOD_MSB_REG              (0x24 + BASE_PATTERN_CONTROL)
+
+
+/* Delay 64bit Write-register */
+#define SET_DELAY_LSB_REG               (0x88 + BASE_PATTERN_CONTROL)
+#define SET_DELAY_MSB_REG               (0x8C + BASE_PATTERN_CONTROL)
+
+/* Cylces 64bit Write-register */
+#define SET_CYCLES_LSB_REG              (0x90 + BASE_PATTERN_CONTROL)
+#define SET_CYCLES_MSB_REG              (0x94 + BASE_PATTERN_CONTROL)
+
+/* Frames 64bit Write-register */
+#define SET_FRAMES_LSB_REG              (0x98 + BASE_PATTERN_CONTROL)
+#define SET_FRAMES_MSB_REG              (0x9C + BASE_PATTERN_CONTROL)
+
+/* Period 64bit Write-register */
+#define SET_PERIOD_LSB_REG              (0xA0 + BASE_PATTERN_CONTROL)
+#define SET_PERIOD_MSB_REG              (0xA4 + BASE_PATTERN_CONTROL)
+
+
+/* Pattern Control FPGA registers --------------------------------------------------*/
+
+// /* Pattern IO Control 64 bit RW Register
+//  * Each bit configured as output(1)/ input(0) */
+// #define PATTERN_IO_CNTRL_LSB_REG        (0x88 + BASE_CONTROL)
+// #define PATTERN_IO_CNTRL_MSB_REG        (0x8C + BASE_CONTROL)
+
+/* Pattern Limit RW Register */
+#define PATTERN_LIMIT_REG               (0x100 + BASE_PATTERN_CONTROL)
+
+#define PATTERN_LIMIT_STRT_OFST       	(0)
+#define PATTERN_LIMIT_STRT_MSK        	(0x00001FFF << PATTERN_LIMIT_STRT_OFST)
+#define PATTERN_LIMIT_STP_OFST        	(16)
+#define PATTERN_LIMIT_STP_MSK         	(0x00001FFF << PATTERN_LIMIT_STP_OFST)
+
+/* Pattern Wait 0 RW Register*/
+#define PATTERN_WAIT_0_ADDR_REG         (0x188 + BASE_PATTERN_CONTROL)
+
+#define PATTERN_WAIT_0_ADDR_OFST        (0)
+#define PATTERN_WAIT_0_ADDR_MSK         (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
+
+/* Pattern Wait 1 RW Register*/
+#define PATTERN_WAIT_1_ADDR_REG         (0x19C + BASE_PATTERN_CONTROL)
+
+#define PATTERN_WAIT_1_ADDR_OFST        (0)
+#define PATTERN_WAIT_1_ADDR_MSK         (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
+
+/* Pattern Wait 2 RW Register*/
+#define PATTERN_WAIT_2_ADDR_REG         (0x1B0 + BASE_PATTERN_CONTROL)
+
+#define PATTERN_WAIT_2_ADDR_OFST        (0)
+#define PATTERN_WAIT_2_ADDR_MSK         (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
+
+/* Pattern Wait Timer 0 64bit RW Register */
+#define PATTERN_WAIT_TIMER_0_LSB_REG    (0x180 + BASE_PATTERN_CONTROL)
+#define PATTERN_WAIT_TIMER_0_MSB_REG    (0x184 + BASE_PATTERN_CONTROL)
+
+/* Pattern Wait Timer 1 64bit RW Register */
+#define PATTERN_WAIT_TIMER_1_LSB_REG    (0x194 + BASE_PATTERN_CONTROL)
+#define PATTERN_WAIT_TIMER_1_MSB_REG    (0x198 + BASE_PATTERN_CONTROL)
+
+/* Pattern Wait Timer 2 64bit RW Register */
+#define PATTERN_WAIT_TIMER_2_LSB_REG    (0x1A8 + BASE_PATTERN_CONTROL)
+#define PATTERN_WAIT_TIMER_2_MSB_REG    (0x1AC + BASE_PATTERN_CONTROL)
+
+/* Pattern Loop 0 Address RW Register */
+#define PATTERN_LOOP_0_ADDR_REG         (0x190 + BASE_PATTERN_CONTROL)
+
+#define PATTERN_LOOP_0_ADDR_STRT_OFST   (0)
+#define PATTERN_LOOP_0_ADDR_STRT_MSK    (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
+#define PATTERN_LOOP_0_ADDR_STP_OFST    (16)
+#define PATTERN_LOOP_0_ADDR_STP_MSK     (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
+
+/* Pattern Loop 1 Address RW Register */
+#define PATTERN_LOOP_1_ADDR_REG         (0x1A4 + BASE_PATTERN_CONTROL)
+
+#define PATTERN_LOOP_1_ADDR_STRT_OFST   (0)
+#define PATTERN_LOOP_1_ADDR_STRT_MSK    (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
+#define PATTERN_LOOP_1_ADDR_STP_OFST    (16)
+#define PATTERN_LOOP_1_ADDR_STP_MSK     (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
+
+/* Pattern Loop 0 Address RW Register */
+#define PATTERN_LOOP_2_ADDR_REG         (0x1B8 + BASE_PATTERN_CONTROL)
+
+#define PATTERN_LOOP_2_ADDR_STRT_OFST   (0)
+#define PATTERN_LOOP_2_ADDR_STRT_MSK    (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
+#define PATTERN_LOOP_2_ADDR_STP_OFST    (16)
+#define PATTERN_LOOP_2_ADDR_STP_MSK     (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
+
+/* Pattern Loop 0 Iteration RW Register */
+#define PATTERN_LOOP_0_ITERATION_REG    (0x18C + BASE_PATTERN_CONTROL) // patnloop
+
+/* Pattern Loop 1 Iteration RW Register */
+#define PATTERN_LOOP_1_ITERATION_REG    (0x1A0 + BASE_PATTERN_CONTROL) // patnloop
+
+/* Pattern Loop 2 Iteration RW Register */
+#define PATTERN_LOOP_2_ITERATION_REG    (0x1B4 + BASE_PATTERN_CONTROL) // patnloop
+
+/* Register of first word */
+#define PATTERN_STEP0_LSB_REG           (0x0 + BASE_PATTERN_RAM)
+#define PATTERN_STEP0_MSB_REG           (0x4 + BASE_PATTERN_RAM)

slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c

@@ -4,6 +4,8 @@
 #include "nios.h"
 #include "DAC6571.h"
 #include "common.h"
+#include "RegisterDefs.h"
+
 #ifdef VIRTUAL
 #include "communication_funcs_UDP.h"
 #endif
@@ -29,6 +31,9 @@ int virtual_status = 0;
 int virtual_stop = 0;
 #endif
 
+int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0};
+uint32_t clkDivider[NUM_CLOCKS] = {125, 20, 80};
+
 int highvoltage = 0;
 
 int isFirmwareCheckDone() {
@@ -57,12 +62,58 @@ void basictests() {
     firmware_check_done = 1;
     return;
 #else
-	// faking it
+	FILE_LOG(logINFOBLUE, ("******** Mythen3 Server: do the checks *****************\n"));
-    firmware_check_done = 1;
+	if (mapCSP0() == FAIL) {
+    	strcpy(firmware_message,
+				"Could not map to memory. Dangerous to continue.\n");
+		FILE_LOG(logERROR, ("%s\n\n", firmware_message));
+		firmware_compatibility = FAIL;
+		firmware_check_done = 1;
+		return;
+    }
+	// does check only if flag is 0 (by default), set by command line
+	if ((!debugflag) && ((testFpga() == FAIL))) {
+		strcpy(firmware_message,
+				"Could not pass basic tests of FPGA and bus. Dangerous to continue.\n");
+		FILE_LOG(logERROR, ("%s\n\n", firmware_message));
+		firmware_compatibility = FAIL;
+		firmware_check_done = 1;
+		return;
+	}
+
 #endif
 }
 
+int checkType() {
+#ifdef VIRTUAL
+    return OK;
+#endif
+	volatile u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
+	if (type != MYTHEN3){
+			FILE_LOG(logERROR, ("This is not a Mythen3 Server (read %d, expected %d)\n", type, MYTHEN3));
+			return FAIL;
+		}
 
+	return OK;
+}
+
+int testFpga() {
+#ifdef VIRTUAL
+    return OK;
+#endif
+	FILE_LOG(logINFO, ("Testing FPGA:\n"));
+
+	//fixed pattern
+	int ret = OK;
+	volatile u_int32_t val = bus_r(FIX_PATT_REG);
+	if (val == FIX_PATT_VAL) {
+		FILE_LOG(logINFO, ("Fixed pattern: successful match 0x%08x\n",val));
+	} else {
+		FILE_LOG(logERROR, ("Fixed pattern does not match! Read 0x%08x, expected 0x%08x\n", val, FIX_PATT_VAL));
+		ret = FAIL;
+	}
+	return ret;
+}
 
 /* Ids */
 
@@ -174,15 +225,26 @@ void initStopServer() {
 void setupDetector() {
     FILE_LOG(logINFO, ("This Server is for 1 Mythen3 module \n")); 
 
+	clkDivider[RUN_CLK] = DEFAULT_RUN_CLK;
+	clkDivider[TICK_CLK] = DEFAULT_TICK_CLK;
+	clkDivider[SAMPLING_CLK] = DEFAULT_SAMPLING_CLK;
+
+	highvoltage = 0;
+
+#ifndef VIRTUAL
 	// hv
-   DAC6571_SetDefines(HV_HARD_MAX_VOLTAGE, HV_DRIVER_FILE_NAME);
+   	DAC6571_SetDefines(HV_HARD_MAX_VOLTAGE, HV_DRIVER_FILE_NAME);
+#endif
     setHighVoltage(DEFAULT_HIGH_VOLTAGE);
 	
 	// Initialization of acquistion parameters
 	setTimer(FRAME_NUMBER, DEFAULT_NUM_FRAMES);
 	setTimer(CYCLES_NUMBER, DEFAULT_NUM_CYCLES);
+
 	setTimer(ACQUISITION_TIME, DEFAULT_EXPTIME);
 	setTimer(FRAME_PERIOD, DEFAULT_PERIOD);
+	setTimer(DELAY_AFTER_TRIGGER, DEFAULT_DELAY_AFTER_TRIGGER);
+
 }
 
 
@@ -206,7 +268,7 @@ int getSpeed(enum speedVariable ind) {
 int64_t setTimer(enum timerIndex ind, int64_t val) {
 
 	int64_t retval = -1;
-#ifdef VIRTUAL
+
 	switch(ind){
 
 	case FRAME_NUMBER: // defined in sls_detector_defs.h (general)
@@ -216,24 +278,36 @@ int64_t setTimer(enum timerIndex ind, int64_t val) {
 		retval = set64BitReg(val,  SET_FRAMES_LSB_REG, SET_FRAMES_MSB_REG); // defined in my RegisterDefs.h
 		FILE_LOG(logDEBUG1, ("Getting #frames: %lld\n", (long long int)retval));
 		break;
-
+	
 	case ACQUISITION_TIME:
 		if(val >= 0){
-			FILE_LOG(logINFO, ("Setting exptime: %lldns\n", (long long int)val));
+			FILE_LOG(logINFO, ("Setting exptime (pattern wait time level 0): %lldns\n",(long long int)val));
-			val *= (1E-3 * TEMP_CLK);
+			val *= (1E-3 * clkDivider[RUN_CLK]);
+			setPatternWaitTime(0, val);
 		}
-		retval = set64BitReg(val, SET_EXPTIME_LSB_REG, SET_EXPTIME_MSB_REG) / (1E-3 * TEMP_CLK); // CLK defined in slsDetectorServer_defs.h
+		retval = setPatternWaitTime(0, -1) / (1E-3 * clkDivider[RUN_CLK]);
-		FILE_LOG(logDEBUG1, ("Getting exptime: %lldns\n", (long long int)retval));
+		FILE_LOG(logINFO, ("\tGetting exptime (pattern wait time level 0): %lldns\n", (long long int)retval));
+		FILE_LOG(logDEBUG1, ("Getting exptime (pattern wait time level 0): %lldns\n", (long long int)retval));
 		break;
 
 	case FRAME_PERIOD:
 		if(val >= 0){
 			FILE_LOG(logINFO, ("Setting period: %lldns\n",(long long int)val));
-			val *= (1E-3 * TEMP_CLK);
+			val *= (1E-3 * TICK_CLK);
 		}
-		retval = set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG )/ (1E-3 * TEMP_CLK);
+		retval = set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG )/ (1E-3 * TICK_CLK);
 		FILE_LOG(logDEBUG1, ("Getting period: %lldns\n", (long long int)retval));
 		break;
+
+	case DELAY_AFTER_TRIGGER:
+		if(val >= 0){
+			FILE_LOG(logINFO, ("Setting delay: %lldns\n", (long long int)val));
+			val *= (1E-3 * clkDivider[TICK_CLK]);
+		}
+		retval = set64BitReg(val, GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) / (1E-3 * clkDivider[TICK_CLK]);
+		FILE_LOG(logINFO, ("\tGetting delay: %lldns\n", (long long int)retval));
+		break;
+
 	case CYCLES_NUMBER:
 		if(val >= 0) {
 			FILE_LOG(logINFO, ("Setting #cycles: %lld\n", (long long int)val));
@@ -246,7 +320,7 @@ int64_t setTimer(enum timerIndex ind, int64_t val) {
 		FILE_LOG(logERROR, ("Timer Index not implemented for this detector: %d\n", ind));
 		break;
 	}
-#endif
+
 	return retval;
 
 }
@@ -256,11 +330,19 @@ int validateTimer(enum timerIndex ind, int64_t val, int64_t retval) {
         return OK;
     switch(ind) {
     case ACQUISITION_TIME:
-    case FRAME_PERIOD:
 		// convert to freq
-        val *= (1E-3 * TEMP_CLK);
+        val *= (1E-3 * RUN_CLK);
         // convert back to timer
-        val = (val) / (1E-3 * TEMP_CLK);
+        val = (val) / (1E-3 * RUN_CLK);
+        if (val != retval)
+            return FAIL;
+        break;
+    case FRAME_PERIOD:
+	    case DELAY_AFTER_TRIGGER:
+		// convert to freq
+        val *= (1E-3 * TICK_CLK);
+        // convert back to timer
+        val = (val) / (1E-3 * TICK_CLK);
         if (val != retval)
             return FAIL;
         break;
@@ -294,7 +376,7 @@ int64_t getTimeLeft(enum timerIndex ind){
 		break;
 	}
 #endif
-	return -1;
+	return retval;
 }
 
 int setHighVoltage(int val){
@@ -333,6 +415,226 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t
 	return OK;
 }
 
+/* pattern */
+
+uint64_t readPatternWord(int addr) {
+    // error (handled in tcp)
+    if (addr < 0 || addr >= MAX_PATTERN_LENGTH) {
+        FILE_LOG(logERROR, ("Cannot get Pattern - Word. Invalid addr 0x%x. "
+                "Should be between 0 and 0x%x\n", addr, MAX_PATTERN_LENGTH));
+        return -1;
+    }
+
+    FILE_LOG(logINFORED, ("  Reading (Executing) Pattern Word (addr:0x%x)\n", addr));
+    uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr; // the first word in RAM as base plus the offset of the word to write (addr)
+	uint32_t reg_msb = PATTERN_STEP0_MSB_REG + addr;
+
+    // read value
+    uint64_t retval = get64BitReg(reg_lsb, reg_msb);
+    FILE_LOG(logDEBUG1, ("  Word(addr:0x%x) retval: 0x%llx\n", addr, (long long int) retval));
+
+    return retval;
+}
+
+uint64_t writePatternWord(int addr, uint64_t word) {
+    // get
+    if (word == -1)
+        return readPatternWord(addr);
+
+    // error (handled in tcp)
+    if (addr < 0 || addr >= MAX_PATTERN_LENGTH) {
+        FILE_LOG(logERROR, ("Cannot set Pattern - Word. Invalid addr 0x%x. "
+                "Should be between 0 and 0x%x\n", addr, MAX_PATTERN_LENGTH));
+        return -1;
+    }
+
+    FILE_LOG(logINFO, ("Setting Pattern Word (addr:0x%x, word:0x%llx)\n", addr, (long long int) word));
+    uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr; // the first word in RAM as base plus the offset of the word to write (addr)
+	uint32_t reg_msb = PATTERN_STEP0_MSB_REG + addr;
+
+    // write word
+    set64BitReg(word, reg_lsb, reg_msb);
+    FILE_LOG(logDEBUG1, ("  Wrote word. PatternIn Reg: 0x%llx\n", get64BitReg(reg_lsb, reg_msb)));
+
+    return readPatternWord(addr);
+}
+
+int setPatternWaitAddress(int level, int addr) {
+
+    // error (handled in tcp)
+    if (addr >= MAX_PATTERN_LENGTH) {
+        FILE_LOG(logERROR, ("Cannot set Pattern Wait Address. Invalid addr 0x%x. "
+                "Should be between 0 and 0x%x\n", addr, MAX_PATTERN_LENGTH));
+        return -1;
+    }
+
+    uint32_t reg = 0;
+    uint32_t offset = 0;
+    uint32_t mask = 0;
+
+    switch (level) {
+    case 0:
+        reg = PATTERN_WAIT_0_ADDR_REG;
+        offset = PATTERN_WAIT_0_ADDR_OFST;
+        mask = PATTERN_WAIT_0_ADDR_MSK;
+        break;
+	case 1:
+        reg = PATTERN_WAIT_1_ADDR_REG;
+        offset = PATTERN_WAIT_1_ADDR_OFST;
+        mask = PATTERN_WAIT_1_ADDR_MSK;
+        break;
+    case 2:
+        reg = PATTERN_WAIT_2_ADDR_REG;
+        offset = PATTERN_WAIT_2_ADDR_OFST;
+        mask = PATTERN_WAIT_2_ADDR_MSK;
+        break;
+    default:
+        FILE_LOG(logERROR, ("Cannot set Pattern Wait Address. Invalid level 0x%x. "
+                "Should be between 0 and 2.\n", level));
+        return -1;
+    }
+
+    // set
+    if (addr >= 0) {
+        FILE_LOG(logINFO, ("Setting Pattern Wait Address (level:%d, addr:0x%x)\n", level, addr));
+        bus_w(reg, ((addr << offset) & mask));
+    }
+
+    // get
+    uint32_t regval = bus_r((reg & mask) >> offset);
+    FILE_LOG(logDEBUG1, ("  Wait Address retval (level:%d, addr:0x%x)\n", level, regval));
+    return regval;
+}
+
+uint64_t setPatternWaitTime(int level, uint64_t t) {
+    uint32_t regl = 0;
+    uint32_t regm = 0;
+
+    switch (level) {
+    case 0:
+        regl = PATTERN_WAIT_TIMER_0_LSB_REG;
+        regm = PATTERN_WAIT_TIMER_0_MSB_REG;
+        break;
+	case 1:
+        regl = PATTERN_WAIT_TIMER_1_LSB_REG;
+        regm = PATTERN_WAIT_TIMER_1_MSB_REG;
+        break;
+    case 2:
+        regl = PATTERN_WAIT_TIMER_2_LSB_REG;
+        regm = PATTERN_WAIT_TIMER_2_MSB_REG;
+        break;
+    default:
+        FILE_LOG(logERROR, ("Cannot set Pattern Wait Time. Invalid level %d. "
+                "Should be between 0 and 2.\n", level));
+        return -1;
+    }
+
+    // set
+    if (t >= 0) {
+        FILE_LOG(logINFO, ("Setting Pattern Wait Time (level:%d, t:%lld)\n", level, (long long int)t));
+        set64BitReg(t, regl, regm);
+    }
+
+    // get
+    uint64_t regval = get64BitReg(regl, regm);
+    FILE_LOG(logDEBUG1, ("  Wait Time retval (level:%d, t:%lld)\n", level, (long long int)regval));
+    return regval;
+}
+
+void setPatternLoop(int level, int *startAddr, int *stopAddr, int *nLoop) {
+
+    // (checked at tcp)
+     if (*startAddr >= MAX_PATTERN_LENGTH || *stopAddr >= MAX_PATTERN_LENGTH) {
+        FILE_LOG(logERROR, ("Cannot set Pattern Loop, Address (startaddr:0x%x, stopaddr:0x%x) must be "
+                "less than 0x%x\n",
+                *startAddr, *stopAddr, MAX_PATTERN_LENGTH));
+    }
+
+    uint32_t addr = 0;
+    uint32_t nLoopReg = 0;
+    uint32_t startOffset = 0;
+    uint32_t startMask = 0;
+    uint32_t stopOffset = 0;
+    uint32_t stopMask = 0;
+
+    switch (level) {
+    case 0:
+        addr = PATTERN_LOOP_0_ADDR_REG;
+        nLoopReg = PATTERN_LOOP_0_ITERATION_REG;
+        startOffset = PATTERN_LOOP_0_ADDR_STRT_OFST;
+        startMask = PATTERN_LOOP_0_ADDR_STRT_MSK;
+        stopOffset = PATTERN_LOOP_0_ADDR_STP_OFST;
+        stopMask = PATTERN_LOOP_0_ADDR_STP_MSK;
+        break;
+    case 1:
+        addr = PATTERN_LOOP_1_ADDR_REG;
+        nLoopReg = PATTERN_LOOP_1_ITERATION_REG;
+        startOffset = PATTERN_LOOP_1_ADDR_STRT_OFST;
+        startMask = PATTERN_LOOP_1_ADDR_STRT_MSK;
+        stopOffset = PATTERN_LOOP_1_ADDR_STP_OFST;
+        stopMask = PATTERN_LOOP_1_ADDR_STP_MSK;
+        break;
+    case 2:
+        addr = PATTERN_LOOP_2_ADDR_REG;
+        nLoopReg = PATTERN_LOOP_2_ITERATION_REG;
+        startOffset = PATTERN_LOOP_2_ADDR_STRT_OFST;
+        startMask = PATTERN_LOOP_2_ADDR_STRT_MSK;
+        stopOffset = PATTERN_LOOP_2_ADDR_STP_OFST;
+        stopMask = PATTERN_LOOP_2_ADDR_STP_MSK;
+        break;
+    case -1:
+        // complete pattern
+        addr = PATTERN_LIMIT_REG;
+        nLoopReg = -1;
+        startOffset = PATTERN_LIMIT_STRT_OFST;
+        startMask = PATTERN_LIMIT_STRT_MSK;
+        stopOffset = PATTERN_LIMIT_STP_OFST;
+        stopMask = PATTERN_LIMIT_STP_MSK;
+        break;
+    default:
+        // already checked at tcp interface
+        FILE_LOG(logERROR, ("Cannot set Pattern loop. Invalid level %d. "
+                "Should be between -1 and 2.\n", level));
+        *startAddr = 0;
+        *stopAddr = 0;
+        *nLoop = 0;
+    }
+
+    // set iterations
+    if (level >= 0) {
+        // set iteration
+        if (*nLoop >= 0) {
+            FILE_LOG(logINFO, ("Setting Pattern Loop (level:%d, nLoop:%d)\n",
+                      level, *nLoop));
+            bus_w(nLoopReg, *nLoop);
+        }
+        *nLoop = bus_r(nLoopReg);
+    }
+
+    // set
+    if (*startAddr >= 0 && *stopAddr >= 0) {
+    	// writing start and stop addr
+    	FILE_LOG(logINFO, ("Setting Pattern Loop (level:%d, startaddr:0x%x, stopaddr:0x%x)\n",
+    			level, *startAddr, *stopAddr));
+    	bus_w(addr, ((*startAddr << startOffset) & startMask) | ((*stopAddr << stopOffset) & stopMask));
+    	FILE_LOG(logDEBUG1, ("Addr:0x%x, val:0x%x\n", addr, bus_r(addr)));
+    }
+
+    // get
+    else {
+    	*startAddr = ((bus_r(addr)  & startMask) >> startOffset);
+    	FILE_LOG(logDEBUG1, ("Getting Pattern Loop Start Address (level:%d, Read startAddr:0x%x)\n",
+    			level, *startAddr));
+
+    	*stopAddr = ((bus_r(addr) & stopMask) >> stopOffset);
+    	FILE_LOG(logDEBUG1, ("Getting Pattern Loop Stop Address (level:%d, Read stopAddr:0x%x)\n",
+    			level, *stopAddr));
+    }
+}
+
+
+
+/* aquisition */
 
 int startStateMachine(){
 #ifdef VIRTUAL
@@ -452,4 +754,4 @@ int calculateDataBytes(){
 int getTotalNumberOfChannels(){return  ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
 int getNumberOfChips(){return  NCHIP;}
 int getNumberOfDACs(){return  NDAC;}
-int getNumberOfChannelsPerChip(){return  NCHAN;}
+int getNumberOfChannelsPerChip(){return  NCHAN;}

slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h

@@ -1,6 +1,5 @@
 #pragma once
 #include "sls_detector_defs.h"
-#include "RegisterDefs.h"
 
 
 #define CTRL_SRVR_INIT_TIME_US      (300 * 1000)
@@ -9,20 +8,23 @@
 #define NCHAN 						(128)
 #define NCHIP 						(10)
 #define NDAC 						(16)
-#define TEMP_CLK					(20)	/* MHz */
 #define HV_SOFT_MAX_VOLTAGE         (200)
 #define HV_HARD_MAX_VOLTAGE         (530)
-#define HV_DRIVER_FILE_NAME         ("/root/devlinks/hvdac")
+#define HV_DRIVER_FILE_NAME         ("/etc/devlinks/hvdac")
 
 /** Default Parameters */
 #define DEFAULT_NUM_FRAMES			(1)
 #define DEFAULT_NUM_CYCLES			(1)
 #define DEFAULT_EXPTIME				(100*1000*1000)		//ns
 #define DEFAULT_PERIOD              (2*1000*1000)	    //ns 
+#define DEFAULT_DELAY_AFTER_TRIGGER (0)
 #define DEFAULT_HIGH_VOLTAGE        (0)
-
+#define DEFAULT_RUN_CLK             (125) 
+#define DEFAULT_TICK_CLK            (20) // will be fixed later. Not configurable
+#define DEFAULT_SAMPLING_CLK        (80)
 
 /* Enums */
+enum CLKINDEX   {RUN_CLK, TICK_CLK, SAMPLING_CLK, NUM_CLOCKS};
 enum DACINDEX   {VIBIASSH, VTRIM, VIPRE, VRFSHNPOL, VTH1, VIPREOUT, VRF, VTH2, CAS, CASSH, VPL, VDCSH, VICIN, VICINSH, VICBIAS, VPH, VTH3, VRFSH};
 #define DEFAULT_DAC_VALS    {1200,  /* vIbiasSh */  \
                             2300,   /* vTrim */     \
@@ -45,3 +47,5 @@ enum DACINDEX   {VIBIASSH, VTRIM, VIPRE, VRFSHNPOL, VTH1, VIPREOUT, VRF, VTH2, C
                             };
 
 
+/* Defines in the Firmware */
+#define MAX_PATTERN_LENGTH  		(0x8192) // maximum number of words (64bit)

slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h

@@ -19,9 +19,11 @@ enum interfaceType {OUTER, INNER};
 int			isFirmwareCheckDone();
 int			getFirmwareCheckResult(char** mess);
 void 		basictests();
-#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(GOTTHARD2D)
+#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
 int 		checkType();
 int 		testFpga();
+#endif
+#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
 int 		testBus();
 #endif
 
@@ -363,6 +365,13 @@ int 		setAllTrimbits(int val);
 int 		getAllTrimbits();
 int 		getBebFPGATemp();
 int 		activate(int enable);
+
+#elif MYTHEN3D
+uint64_t    readPatternWord(int addr);
+uint64_t    writePatternWord(int addr, uint64_t word);
+int         setPatternWaitAddress(int level, int addr);
+uint64_t    setPatternWaitTime(int level, uint64_t t);
+void        setPatternLoop(int level, int *startAddr, int *stopAddr, int *nLoop);
 #endif
 
 #if defined(JUNGFRAUD) || defined(EIGERD)

slsDetectorServers/slsDetectorServer/src/nios.c

@@ -9,7 +9,7 @@
 
 /* global variables */
 u_int32_t* csp0base = 0;
-#define CSP0 0x18000000
+#define CSP0 0x18060000
 #define MEM_SIZE 0x100000
 
 
@@ -21,7 +21,7 @@ void bus_w(u_int32_t offset, u_int32_t data) {
 
 u_int32_t bus_r(u_int32_t offset) {
 	volatile u_int32_t  *ptr1;
-	ptr1=(u_int32_t*)(csp0base + offset/(sizeof(u_int32_t)));
+	ptr1=(u_int32_t*)(csp0base + offset/(sizeof(u_int32_t))); 
 	return *ptr1;
 }
 

slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c

@@ -1660,7 +1660,7 @@ int set_timer(int file_des) {
 	    case ANALOG_SAMPLES:
 		case DIGITAL_SAMPLES:
 #endif
-#if !defined(EIGERD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
+#if !defined(EIGERD) && !defined(GOTTHARD2D)
 	    case DELAY_AFTER_TRIGGER:
 #endif
 	        retval = setTimer(ind, tns);
@@ -2608,7 +2608,7 @@ int set_pattern_word(int file_des) {
 
     if (receiveData(file_des, args, sizeof(args), INT64) < 0)
         return printSocketReadError();
-#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD)
+#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
     functionNotImplemented();
 #else
 	int addr = (int)args[0];
@@ -2644,7 +2644,7 @@ int set_pattern_loop(int file_des) {
 
     if (receiveData(file_des, args, sizeof(args), INT32) < 0)
         return printSocketReadError();
-#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD)
+#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
     functionNotImplemented();
 #else
     int loopLevel = args[0];
@@ -2695,7 +2695,7 @@ int set_pattern_wait_addr(int file_des) {
 
     if (receiveData(file_des, args, sizeof(args), INT32) < 0)
         return printSocketReadError();
-#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD)
+#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
     functionNotImplemented();
 #else
     int loopLevel = args[0];
@@ -2737,7 +2737,7 @@ int set_pattern_wait_time(int file_des) {
 
     if (receiveData(file_des, args, sizeof(args), INT32) < 0)
         return printSocketReadError();
-#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD)
+#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
     functionNotImplemented();
 #else
     int loopLevel = (int)args[0];

slsSupportLib/include/versionAPI.h

@@ -8,5 +8,5 @@
 #define APIGOTTHARD 0x190902
 #define APIJUNGFRAU 0x190902
 #define APIEIGER 0x190902
-#define APIMYTHEN3 0x190903
 #define APIGOTTHARD2 0x190927
+#define APIMYTHEN3 0x190930