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ctb & moench server: reset phase when changing clock
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@ -1744,6 +1744,12 @@ void configureFrequency(enum CLKINDEX ind, int val) {
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return;
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return;
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}
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}
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// reset phase
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if (ind == ADC_CLK || ind == DBIT_CLK) {
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FILE_LOG(logDEBUG1, ("Reseting phase of %s\n", clock_names[ind]));
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configurePhase(ind, 0, 0);
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}
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// Calculate and set output frequency
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// Calculate and set output frequency
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clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
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clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
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FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind]));
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FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind]));
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@ -1380,6 +1380,12 @@ void configureFrequency(enum CLKINDEX ind, int val) {
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return;
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return;
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}
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}
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// reset phase
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if (ind == ADC_CLK || ind == DBIT_CLK) {
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FILE_LOG(logDEBUG1, ("Reseting phase of %s\n", clock_names[ind]));
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configurePhase(ind, 0, 0);
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}
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// Calculate and set output frequency
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// Calculate and set output frequency
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clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
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clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
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FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind]));
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FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind]));
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