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ctb & moench server: reset phase when changing clock

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This commit is contained in:
maliakal_d
2019-03-27 15:48:55 +01:00
parent 2ccd03a3b0
commit 5a4122ae7c
2 changed files with 12 additions and 0 deletions
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6
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
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@ -1744,6 +1744,12 @@ void configureFrequency(enum CLKINDEX ind, int val) {
return; return;
} }
// reset phase
if (ind == ADC_CLK || ind == DBIT_CLK) {
FILE_LOG(logDEBUG1, ("Reseting phase of %s\n", clock_names[ind]));
configurePhase(ind, 0, 0);
}
// Calculate and set output frequency // Calculate and set output frequency
clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val); clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind])); FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind]));

6
slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
View File

@ -1380,6 +1380,12 @@ void configureFrequency(enum CLKINDEX ind, int val) {
return; return;
} }
// reset phase
if (ind == ADC_CLK || ind == DBIT_CLK) {
FILE_LOG(logDEBUG1, ("Reseting phase of %s\n", clock_names[ind]));
configurePhase(ind, 0, 0);
}
// Calculate and set output frequency // Calculate and set output frequency
clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val); clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind])); FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind]));