diff --git a/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
index c865bbdf8..2939ff28c 100644
--- a/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
+++ b/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
@@ -1744,6 +1744,12 @@ void configureFrequency(enum CLKINDEX ind, int val) {
         return;
     }
 
+    // reset phase
+    if (ind == ADC_CLK || ind == DBIT_CLK) {
+    	FILE_LOG(logDEBUG1, ("Reseting phase of %s\n", clock_names[ind]));
+    	configurePhase(ind, 0, 0);
+    }
+
     // Calculate and set output frequency
     clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
     FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind]));
diff --git a/slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
index a213d9360..fcddc04ed 100644
--- a/slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
+++ b/slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
@@ -1380,6 +1380,12 @@ void configureFrequency(enum CLKINDEX ind, int val) {
         return;
     }
 
+    // reset phase
+    if (ind == ADC_CLK || ind == DBIT_CLK) {
+    	FILE_LOG(logDEBUG1, ("Reseting phase of %s\n", clock_names[ind]));
+    	configurePhase(ind, 0, 0);
+    }
+
     // Calculate and set output frequency
     clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
     FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind]));