detectors/slsDetectorPackage
25
0
Fork 0
mirror of https://github.com/slsdetectorgroup/slsDetectorPackage.git synced 2025-06-07 10:30:41 +02:00
Code Issues Actions Packages Releases Activity

ctb & moench server: reset phase when changing clock

Browse Source
This commit is contained in:
maliakal_d 2019-03-27 15:48:55 +01:00
parent 2ccd03a3b0
commit 5a4122ae7c
2 changed files with 12 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
View File

@ -1744,6 +1744,12 @@ void configureFrequency(enum CLKINDEX ind, int val) {
return;
}
// reset phase
if (ind == ADC_CLK || ind == DBIT_CLK) {
FILE_LOG(logDEBUG1, ("Reseting phase of %s\n", clock_names[ind]));
configurePhase(ind, 0, 0);
}
// Calculate and set output frequency
clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind]));

6
slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
View File

@ -1380,6 +1380,12 @@ void configureFrequency(enum CLKINDEX ind, int val) {
return;
}
// reset phase
if (ind == ADC_CLK || ind == DBIT_CLK) {
FILE_LOG(logDEBUG1, ("Reseting phase of %s\n", clock_names[ind]));
configurePhase(ind, 0, 0);
}
// Calculate and set output frequency
clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind]));