 ritt
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118ded9ac0
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Added optional histogram output in chip test
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2016-12-05 14:03:06 +01:00 |
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ritt
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bcc7e30369
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Implemented measurement of leakage currents
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2016-12-01 16:16:37 +01:00 |
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ritt
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dfe33dc32d
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Made chip test work with normal V5 board
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2016-12-01 12:25:02 +01:00 |
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ritt
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50964d81ca
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Updated examples to new project structure
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2016-12-01 09:31:25 +01:00 |
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ritt
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8d814a6705
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Switch EXT properly when entering / exiting transparent mode
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2016-12-01 08:50:23 +01:00 |
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ritt
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fab70c5365
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Fixed problem when no trigger channel is selected
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2016-11-30 17:38:23 +01:00 |
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ritt
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8906b39e7d
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Fixed trigger display if no channel is selected
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2016-11-30 17:34:59 +01:00 |
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ritt
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8004cfb357
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Fixed color of trigger level display at bottom of screen
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2016-11-30 17:22:34 +01:00 |
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ritt
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51134fb2db
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Re-arranged trigger source configuration
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2016-11-30 17:14:46 +01:00 |
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ritt
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5ab32c3921
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Made transparent trigger mode wok in multi-board configuration
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2016-11-28 16:57:50 +01:00 |
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ritt
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403dc702fb
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Implemented readout delay
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2016-11-24 17:19:27 +01:00 |
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ritt
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bdd6b7fcad
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Align cell #0 of each channel instead of 700. Same result, but less confusing.
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2016-11-24 14:40:27 +01:00 |
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ritt
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7bca3829fa
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Copied files over from SVN repositories
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2016-11-14 15:38:40 +01:00 |
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