 ritt
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0e0df37791
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Fixed time and waveform points in rec->Branch
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2023-02-06 13:58:42 +01:00 |
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ritt
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80b3af753e
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Replaced strncpy by strlcpy
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2023-02-06 13:27:31 +01:00 |
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ritt
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be55a5ed0c
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Replaced sprintf by snprintf
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2023-02-06 13:25:16 +01:00 |
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ritt
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6eb2304605
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Added explicit file name extensions
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2022-04-25 09:18:21 +02:00 |
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ritt
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45c5755882
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Fixed issue with channel depth in 2048 bin mode
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2021-08-10 15:30:01 +02:00 |
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ritt
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7a630c5f70
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Added missing -DUSE_DRS_MUTEX
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2021-08-10 13:28:25 +02:00 |
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ritt
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f77c85ad65
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Moved temperature readout into Osci thread
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2021-08-10 13:14:08 +02:00 |
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ritt
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ef759a59f8
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Fixed alignment errors
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2021-08-10 13:13:03 +02:00 |
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ritt
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592497bb5a
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Updated mxml
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2021-08-10 10:42:42 +02:00 |
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ritt
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5edb5cf4b7
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Added CMake project, removed obsolete libusb function
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2021-08-10 10:42:29 +02:00 |
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ritt
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cefd496089
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Ignore .idea
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2020-09-03 15:11:42 +02:00 |
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ritt
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6b7f0c83ef
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Fixed install dir
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2019-06-20 18:05:10 +02:00 |
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ritt
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235024cf76
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Fixed error in CMakeLists.txt
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2019-06-20 17:33:44 +02:00 |
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ritt
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96b1076ec4
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Added mxml as subproject. CMake still gives errors.
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2019-06-20 17:20:00 +02:00 |
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ritt
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e579e22cbf
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Added initial Cmake file for drsosc
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2019-06-19 18:05:35 +02:00 |
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ritt
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e0035fd963
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Created initial CMakeLists.txt
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2019-06-17 22:14:03 +02:00 |
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ritt
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725294e96a
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Made read_binary.C work with current data format
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2019-05-27 17:15:08 +02:00 |
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ritt
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8f8c01897a
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Added missiong wxT()
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2019-01-14 08:44:31 +01:00 |
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ritt
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ce588a1b6d
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Merge branch 'master' of bitbucket.org:ritt/drs4eb
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2019-01-09 10:57:42 +01:00 |
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ritt
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9418b346bc
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Switched to libc++ in Makefile, fixed casting error in wxMessageBox
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2019-01-09 10:57:28 +01:00 |
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ritt
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53ec6a7558
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Ignore some windows files
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2018-12-11 17:53:33 +01:00 |
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ritt
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6b57df374f
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Added drs_exam_2018.cpp
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2017-12-13 11:16:21 +01:00 |
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ritt
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426776ab0c
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Changed comment
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2017-12-12 14:03:06 +01:00 |
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ritt
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aded8e478f
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Fixed code for external trigger
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2017-12-12 13:58:01 +01:00 |
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ritt
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4fc3bab402
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Updated XCode project file
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2017-11-07 14:10:27 +01:00 |
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ritt
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c4b903e540
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Merge branch 'master' of bitbucket.org:ritt/drs4eb
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2017-10-11 11:03:40 +02:00 |
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ritt
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a0019cc7da
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Fixed a few issues in chip test routine
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2017-10-11 11:03:28 +02:00 |
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ritt
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7916c5dbab
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Compiled drscl.exe
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2017-10-11 10:03:20 +02:00 |
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ritt
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ed441935a7
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Optimized chip tests for good new chips with lower leakage current
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2017-10-10 17:36:34 +02:00 |
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ritt
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9df66d5c96
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Implemented “-l” option to check USB
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2017-04-12 10:26:50 +02:00 |
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ritt
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8c916cab22
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Updated Visual Studio project file
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2017-01-13 13:49:05 +01:00 |
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ritt
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9e6aa0e059
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Recompiled under Windows
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2017-01-09 17:06:59 +01:00 |
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ritt
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8461281a67
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Optimized chip test for new test board, implemented leakage current limit of 100 pA
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2017-01-09 16:54:01 +01:00 |
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ritt
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118ded9ac0
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Added optional histogram output in chip test
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2016-12-05 14:03:06 +01:00 |
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ritt
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bcc7e30369
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Implemented measurement of leakage currents
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2016-12-01 16:16:37 +01:00 |
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ritt
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dfe33dc32d
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Made chip test work with normal V5 board
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2016-12-01 12:25:02 +01:00 |
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ritt
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50964d81ca
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Updated examples to new project structure
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2016-12-01 09:31:25 +01:00 |
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ritt
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8d814a6705
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Switch EXT properly when entering / exiting transparent mode
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2016-12-01 08:50:23 +01:00 |
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ritt
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fab70c5365
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Fixed problem when no trigger channel is selected
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2016-11-30 17:38:23 +01:00 |
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ritt
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8906b39e7d
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Fixed trigger display if no channel is selected
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2016-11-30 17:34:59 +01:00 |
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ritt
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8004cfb357
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Fixed color of trigger level display at bottom of screen
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2016-11-30 17:22:34 +01:00 |
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ritt
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51134fb2db
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Re-arranged trigger source configuration
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2016-11-30 17:14:46 +01:00 |
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ritt
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5ab32c3921
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Made transparent trigger mode wok in multi-board configuration
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2016-11-28 16:57:50 +01:00 |
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ritt
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403dc702fb
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Implemented readout delay
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2016-11-24 17:19:27 +01:00 |
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ritt
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bdd6b7fcad
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Align cell #0 of each channel instead of 700. Same result, but less confusing.
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2016-11-24 14:40:27 +01:00 |
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ritt
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7bca3829fa
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Copied files over from SVN repositories
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2016-11-14 15:38:40 +01:00 |
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