AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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merge into: AEK_8220_Libraries:feature/se32
Branches Tags
AEK_8220_Libraries:master AEK_8220_Libraries:feature/se32 AEK_8220_Libraries:6-interrupts-not-reliably-generated-when-window-is-switched AEK_8220_Libraries:feature/timeout_ctrl AEK_8220_Libraries:feature/1024bus AEK_8220_Libraries:develop AEK_8220_Libraries:PreGitHub
AEK_8220_Libraries:2.0.0 AEK_8220_Libraries:1.2.3 AEK_8220_Libraries:1.2.2 AEK_8220_Libraries:1.2.1 AEK_8220_Libraries:1.2.0 AEK_8220_Libraries:1.1.0 AEK_8220_Libraries:1.0.0 AEK_8220_Libraries:0.9.0 AEK_8220_Libraries:0.2.0 AEK_8220_Libraries:0.1.0
...
pull from: AEK_8220_Libraries:master
Branches Tags
AEK_8220_Libraries:master AEK_8220_Libraries:feature/se32 AEK_8220_Libraries:6-interrupts-not-reliably-generated-when-window-is-switched AEK_8220_Libraries:feature/timeout_ctrl AEK_8220_Libraries:feature/1024bus AEK_8220_Libraries:develop AEK_8220_Libraries:PreGitHub
AEK_8220_Libraries:2.0.0 AEK_8220_Libraries:1.2.3 AEK_8220_Libraries:1.2.2 AEK_8220_Libraries:1.2.1 AEK_8220_Libraries:1.2.0 AEK_8220_Libraries:1.1.0 AEK_8220_Libraries:1.0.0 AEK_8220_Libraries:0.9.0 AEK_8220_Libraries:0.2.0 AEK_8220_Libraries:0.1.0

3 Commits
feature/se ... master

Author SHA1 Message Date
Waldemar Koprek
f4c0185f31 Merge pull request #8 from paulscherrerinstitute/feature/se32 
New features in branch feature/se32
 2024-08-08 12:41:58 +02:00
Waldemar Koprek
0dfa3ef76b Merge pull request #7 from paulscherrerinstitute/6-interrupts-not-reliably-generated-when-window-is-switched 
Adapt interrupt generation logic to solve problem with missing interr…
 2024-07-30 08:47:23 +02:00
Elmar Schmid
3957ce32b5 Adapt interrupt generation logic to solve problem with missing interrupts. 2024-07-25 15:39:24 +02:00
1 changed files with 6 additions and 5 deletions
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11
hdl/psi_ms_daq_daq_sm.vhd
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@@ -576,11 +576,12 @@ begin
if (unsigned(r.TfDoneCnt) /= 0) and (IrqFifoEmpty = '0') then
v.IrqFifoRead := '1';
v.TfDoneCnt := std_logic_vector(unsigned(v.TfDoneCnt) - 1);
-- Generate IRQ if required
if IrqFifoGenIrq = '1' then
v.StrIrq(to_integer(unsigned(IrqFifoStream))) := '1';
v.StrLastWin(to_integer(unsigned(IrqFifoStream))) := std_logic_vector(resize(unsigned(IrqLastWinNr), 5));
end if;
end if;
-- Generate IRQ if required
if IrqFifoGenIrq = '1' and r.IrqFifoRead = '1' then
v.StrIrq(to_integer(unsigned(IrqFifoStream))) := '1';
v.StrLastWin(to_integer(unsigned(IrqFifoStream))) := std_logic_vector(resize(unsigned(IrqLastWinNr), 5));
end if;
-- *** Assign to signal ***