DOC: Updated Changelog.md

Changelog.md

@@ -1,3 +1,19 @@
+## 1.2.3
+* Doc
+  * Changed repository mantainer
+
+## 1.2.2
+* Bugfixes
+  * Workaround for ISE tools implementing memory as FFs in case of 1 stream
+
+## 1.2.1
+* Bugfixes
+  * Optimized timing between input FIFO and DMA
+  * Fix data unwrapping in driver
+  * Corrected several issues in documentation
+  * Made driver C++ tolerant
+  * Made code working for only one streamgit 
+
 ## 1.2.0
 * First Open Source Release (older versions not kept in history)
 * Added license and copyright headers

README.md

@@ -1,7 +1,10 @@
 # General Information
 
 ## Maintainer
-Oliver Bründler [oliver.bruendler@psi.ch]
+Daniele Felici [daniele.felici@psi.ch]
+
+## Author
+Oliver Bründler [oli.bruendler@gmx.ch]
 
 ## License
 This library is published under [PSI HDL Library License](License.txt), which is [LGPL](LGPL2_1.txt) plus some additional exceptions to clarify the LGPL terms in the context of firmware development.

hdl/psi_ms_daq_axi.vhd

@@ -398,7 +398,7 @@ begin
 			AxiDataWidth_g			=> AxiDataWidth_g,
 			AxiMaxBeats_g			=> AxiMaxBurstBeats_g,
 			AxiMaxOpenTrasactions_g	=> AxiMaxOpenTrasactions_g,
-			MaxOpenCommands_g		=> Streams_g,
+			MaxOpenCommands_g		=> max(2, Streams_g), -- ISE tools implement memory as FFs for one stream. Reason is unkown, so we always implement two streams for resource optimization reasons.
 			DataFifoDepth_g			=> 1024,
 			AxiFifoDepth_g			=> AxiFifoDepth_g,
 			RamBehavior_g			=> "RBW" -- Okay for Xilinx chips