AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
11 Commits 7 Branches 10 Tags
develop
Commit Graph
3 Commits
Author SHA1 Message Date
Oliver Bruendler df29e19f6d TIMING: Optimized timing on critical path between input FIFO and DMA 
Added pipeline stage after FIFO to reduce requirements of fall-through interface
 2019-11-07 07:46:37 +01:00
Oliver Bruendler 7f22ec9050 BUGFIX: Made design working for 1 stream 2019-10-30 11:02:11 +01:00
Oliver Bruendler d455112276 DEVEL: First open source release 2019-08-02 10:03:58 +02:00