208 lines
8.1 KiB
VHDL
208 lines
8.1 KiB
VHDL
------------------------------------------------------------------------------
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-- Paul Scherrer Institute (PSI)
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------------------------------------------------------------------------------
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-- Unit : v6vlx_gtxe1_pkg.vhd
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-- Author : Goran Marinkovic, Section Diagnostic
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-- : Waldemar Koprek, Section Diagnostic
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-- : Patric Bucher, Section DSV
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-- Version : $Revision: 1.1 $
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------------------------------------------------------------------------------
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-- Copyright© PSI, Section Diagnostic
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------------------------------------------------------------------------------
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-- Comment :
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package v6vlx_gtxe1_pkg is
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---------------------------------------------------------------------------
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-- Types
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---------------------------------------------------------------------------
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type gtxe_ctrl_in_type is record
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GTXRESET : std_ulogic;
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LOOPBACK : std_logic_vector( 2 downto 0);
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CLKIN : std_ulogic;
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PLLRXRESET : std_ulogic;
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PLLTXRESET : std_ulogic;
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end record gtxe_ctrl_in_type;
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type gtxe_ctrl_out_type is record
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RXPLLLKDET : std_ulogic;
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RXRESETDONE : std_ulogic;
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TXPLLLKDET : std_ulogic;
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TXRESETDONE : std_ulogic;
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REFCLKOUT : std_ulogic;
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end record gtxe_ctrl_out_type;
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-- type mgt_drp_in_type is record
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-- -- Dynamic Reconfiguration Port (DRP)
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-- DCLK : std_ulogic;
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-- DEN : std_ulogic;
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-- DWE : std_ulogic;
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-- DADDR : std_logic_vector( 6 downto 0);
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-- DI : std_logic_vector(15 downto 0);
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-- end record mgt_drp_in_type;
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--
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-- type mgt_drp_out_type is record
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-- -- Dynamic Reconfiguration Port (DRP)
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-- DO : std_logic_vector(15 downto 0);
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-- DRDY : std_ulogic;
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-- end record mgt_drp_out_type;
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type gtxe_rx_in_type is record
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-- Comma Detection and Alignment ------------------------
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RXENMCOMMAALIGN : std_ulogic;
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RXENPCOMMAALIGN : std_ulogic;
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-- RX resets
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RXRESET : std_ulogic;
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RXCDRRESET : std_ulogic;
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-- RX user clocks
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RXUSRCLK : std_ulogic;
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RXUSRCLK2 : std_ulogic;
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-- RX serial ports
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RXP : std_ulogic;
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RXN : std_ulogic;
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-- RX Elastic Buffer and Phase Alignment Ports
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RXDLYALIGNDISABLE : std_logic;
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RXDLYALIGNMONENB : std_logic;
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RXDLYALIGNOVERRIDE : std_logic;
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RXDLYALIGNRESET : std_logic;
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RXENPMAPHASEALIGN : std_logic;
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RXPMASETPHASE : std_logic;
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RXSLIDE : std_logic;
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end record gtxe_rx_in_type;
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type gtxe_rx_out_type is record
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-- RX 8b10b Decoder
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RXCHARISCOMMA : std_logic_vector( 3 downto 0);
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RXCHARISK : std_logic_vector( 3 downto 0);
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RXDISPERR : std_logic_vector( 3 downto 0);
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RXNOTINTABLE : std_logic_vector( 3 downto 0);
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RXRUNDISP : std_logic_vector( 3 downto 0);
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-- Comma Detection and Alignment
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RXBYTEISALIGNED : std_ulogic;
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RXBYTEREALIGN : std_ulogic;
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RXCOMMADET : std_ulogic;
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-- RX data ports
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RXDATA : std_logic_vector(31 downto 0);
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-- RX user clocks
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RXRECCLK : std_ulogic;
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-- RX Out Of Band (OOB)
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RXELECIDLE : std_ulogic;
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-- RX Elastic Buffer and Phase Alignment Ports
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RXDLYALIGNMONITOR : std_logic_vector(7 downto 0);
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-- RX loss of sync fsm
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RXLOSSOFSYNC : std_logic_vector( 1 downto 0);
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end record gtxe_rx_out_type;
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type gtxe_tx_in_type is record
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-- 8b10b Encoder Control Ports
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TXBYPASS8B10B : std_logic_vector( 3 downto 0);
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TXCHARDISPMODE : std_logic_vector( 3 downto 0);
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TXCHARDISPVAL : std_logic_vector( 3 downto 0);
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TXCHARISK : std_logic_vector( 3 downto 0);
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-- TX data ports
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TXDATA : std_logic_vector(31 downto 0);
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-- TX resets
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TXRESET : std_ulogic;
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-- TX user clocks
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TXUSRCLK : std_ulogic;
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TXUSRCLK2 : std_ulogic;
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-- TX driver
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TXDIFFCTRL : std_logic_vector( 3 downto 0);
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TXPOSTEMPHASIS : std_logic_vector( 4 downto 0);
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TXPREEMPHASIS : std_logic_vector( 3 downto 0);
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end record gtxe_tx_in_type;
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type gtxe_tx_out_type is record
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-- TX serial ports
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TXP : std_ulogic;
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TXN : std_ulogic;
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-- TX 8b10b encoder
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TXKERR : std_logic_vector( 3 downto 0);
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TXRUNDISP : std_logic_vector( 3 downto 0);
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-- TX user clocks
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TXOUTCLK : std_ulogic;
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end record gtxe_tx_out_type;
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type gtxe_in_type is record
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ctrl : gtxe_ctrl_in_type;
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--drp : mgt_drp_in_type;
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rx : gtxe_rx_in_type;
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tx : gtxe_tx_in_type;
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end record gtxe_in_type;
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type gtxe_out_type is record
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ctrl : gtxe_ctrl_out_type;
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--drp : mgt_drp_out_type;
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rx : gtxe_rx_out_type;
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tx : gtxe_tx_out_type;
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end record gtxe_out_type;
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---------------------------------------------------------------------------
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-- Components
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---------------------------------------------------------------------------
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component v6vlx_gtxe1_142MHz8_2Gbps856
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generic(
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g_MGT_LOCATION : string
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);
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port
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(
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i_mgt : in gtxe_in_type;
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o_mgt : out gtxe_out_type
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);
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end component;
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component v6vlx_gtxe1_101MHz27_1Gbps0127
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generic(
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g_MGT_LOCATION : string
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);
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port
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(
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i_mgt : in gtxe_in_type;
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o_mgt : out gtxe_out_type
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);
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end component;
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component v6vlx_gtxe1_sync is
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port
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(
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RXENPMAPHASEALIGN : out std_logic;
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RXPMASETPHASE : out std_logic;
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RXDLYALIGNDISABLE : out std_logic;
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RXDLYALIGNOVERRIDE : out std_logic;
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RXDLYALIGNRESET : out std_logic;
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SYNC_DONE : out std_logic;
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USER_CLK : in std_logic;
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RESET : in std_logic
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);
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end component;
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component v6vlx_gtxe1_wrapper is
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generic(
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g_MGT_LOCATION : string;
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g_USE_MMCM : boolean := false
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);
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port
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(
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-- MGT serial interface
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i_mgt_refclk : in std_logic;
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o_mgt_refclk : out std_logic;
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i_mgt_rx_p : in std_logic;
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i_mgt_rx_n : in std_logic;
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o_mgt_tx_p : out std_logic;
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o_mgt_tx_n : out std_logic;
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-- MGT parallel interface
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o_mgt_status : out std_logic_vector(31 downto 0); -- see lines 134-139 for details
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i_mgt_control : in std_logic_vector(31 downto 0); -- see lines 127-131 for details
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o_mgt_recclk : out std_logic;
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o_mgt_rx_data : out std_logic_vector(15 downto 0);
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o_mgt_rx_charisk : out std_logic_vector( 1 downto 0)
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);
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end component;
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end package v6vlx_gtxe1_pkg;
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