------------------------------------------------------------------------------ -- Paul Scherrer Institute (PSI) ------------------------------------------------------------------------------ -- Unit : v6vlx_gtxe1_pkg.vhd -- Author : Goran Marinkovic, Section Diagnostic -- : Waldemar Koprek, Section Diagnostic -- : Patric Bucher, Section DSV -- Version : $Revision: 1.1 $ ------------------------------------------------------------------------------ -- Copyright© PSI, Section Diagnostic ------------------------------------------------------------------------------ -- Comment : ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; package v6vlx_gtxe1_pkg is --------------------------------------------------------------------------- -- Types --------------------------------------------------------------------------- type gtxe_ctrl_in_type is record GTXRESET : std_ulogic; LOOPBACK : std_logic_vector( 2 downto 0); CLKIN : std_ulogic; PLLRXRESET : std_ulogic; PLLTXRESET : std_ulogic; end record gtxe_ctrl_in_type; type gtxe_ctrl_out_type is record RXPLLLKDET : std_ulogic; RXRESETDONE : std_ulogic; TXPLLLKDET : std_ulogic; TXRESETDONE : std_ulogic; REFCLKOUT : std_ulogic; end record gtxe_ctrl_out_type; -- type mgt_drp_in_type is record -- -- Dynamic Reconfiguration Port (DRP) -- DCLK : std_ulogic; -- DEN : std_ulogic; -- DWE : std_ulogic; -- DADDR : std_logic_vector( 6 downto 0); -- DI : std_logic_vector(15 downto 0); -- end record mgt_drp_in_type; -- -- type mgt_drp_out_type is record -- -- Dynamic Reconfiguration Port (DRP) -- DO : std_logic_vector(15 downto 0); -- DRDY : std_ulogic; -- end record mgt_drp_out_type; type gtxe_rx_in_type is record -- Comma Detection and Alignment ------------------------ RXENMCOMMAALIGN : std_ulogic; RXENPCOMMAALIGN : std_ulogic; -- RX resets RXRESET : std_ulogic; RXCDRRESET : std_ulogic; -- RX user clocks RXUSRCLK : std_ulogic; RXUSRCLK2 : std_ulogic; -- RX serial ports RXP : std_ulogic; RXN : std_ulogic; -- RX Elastic Buffer and Phase Alignment Ports RXDLYALIGNDISABLE : std_logic; RXDLYALIGNMONENB : std_logic; RXDLYALIGNOVERRIDE : std_logic; RXDLYALIGNRESET : std_logic; RXENPMAPHASEALIGN : std_logic; RXPMASETPHASE : std_logic; RXSLIDE : std_logic; end record gtxe_rx_in_type; type gtxe_rx_out_type is record -- RX 8b10b Decoder RXCHARISCOMMA : std_logic_vector( 3 downto 0); RXCHARISK : std_logic_vector( 3 downto 0); RXDISPERR : std_logic_vector( 3 downto 0); RXNOTINTABLE : std_logic_vector( 3 downto 0); RXRUNDISP : std_logic_vector( 3 downto 0); -- Comma Detection and Alignment RXBYTEISALIGNED : std_ulogic; RXBYTEREALIGN : std_ulogic; RXCOMMADET : std_ulogic; -- RX data ports RXDATA : std_logic_vector(31 downto 0); -- RX user clocks RXRECCLK : std_ulogic; -- RX Out Of Band (OOB) RXELECIDLE : std_ulogic; -- RX Elastic Buffer and Phase Alignment Ports RXDLYALIGNMONITOR : std_logic_vector(7 downto 0); -- RX loss of sync fsm RXLOSSOFSYNC : std_logic_vector( 1 downto 0); end record gtxe_rx_out_type; type gtxe_tx_in_type is record -- 8b10b Encoder Control Ports TXBYPASS8B10B : std_logic_vector( 3 downto 0); TXCHARDISPMODE : std_logic_vector( 3 downto 0); TXCHARDISPVAL : std_logic_vector( 3 downto 0); TXCHARISK : std_logic_vector( 3 downto 0); -- TX data ports TXDATA : std_logic_vector(31 downto 0); -- TX resets TXRESET : std_ulogic; -- TX user clocks TXUSRCLK : std_ulogic; TXUSRCLK2 : std_ulogic; -- TX driver TXDIFFCTRL : std_logic_vector( 3 downto 0); TXPOSTEMPHASIS : std_logic_vector( 4 downto 0); TXPREEMPHASIS : std_logic_vector( 3 downto 0); end record gtxe_tx_in_type; type gtxe_tx_out_type is record -- TX serial ports TXP : std_ulogic; TXN : std_ulogic; -- TX 8b10b encoder TXKERR : std_logic_vector( 3 downto 0); TXRUNDISP : std_logic_vector( 3 downto 0); -- TX user clocks TXOUTCLK : std_ulogic; end record gtxe_tx_out_type; type gtxe_in_type is record ctrl : gtxe_ctrl_in_type; --drp : mgt_drp_in_type; rx : gtxe_rx_in_type; tx : gtxe_tx_in_type; end record gtxe_in_type; type gtxe_out_type is record ctrl : gtxe_ctrl_out_type; --drp : mgt_drp_out_type; rx : gtxe_rx_out_type; tx : gtxe_tx_out_type; end record gtxe_out_type; --------------------------------------------------------------------------- -- Components --------------------------------------------------------------------------- component v6vlx_gtxe1_142MHz8_2Gbps856 generic( g_MGT_LOCATION : string ); port ( i_mgt : in gtxe_in_type; o_mgt : out gtxe_out_type ); end component; component v6vlx_gtxe1_101MHz27_1Gbps0127 generic( g_MGT_LOCATION : string ); port ( i_mgt : in gtxe_in_type; o_mgt : out gtxe_out_type ); end component; component v6vlx_gtxe1_sync is port ( RXENPMAPHASEALIGN : out std_logic; RXPMASETPHASE : out std_logic; RXDLYALIGNDISABLE : out std_logic; RXDLYALIGNOVERRIDE : out std_logic; RXDLYALIGNRESET : out std_logic; SYNC_DONE : out std_logic; USER_CLK : in std_logic; RESET : in std_logic ); end component; component v6vlx_gtxe1_wrapper is generic( g_MGT_LOCATION : string; g_USE_MMCM : boolean := false ); port ( -- MGT serial interface i_mgt_refclk : in std_logic; o_mgt_refclk : out std_logic; i_mgt_rx_p : in std_logic; i_mgt_rx_n : in std_logic; o_mgt_tx_p : out std_logic; o_mgt_tx_n : out std_logic; -- MGT parallel interface o_mgt_status : out std_logic_vector(31 downto 0); -- see lines 134-139 for details i_mgt_control : in std_logic_vector(31 downto 0); -- see lines 127-131 for details o_mgt_recclk : out std_logic; o_mgt_rx_data : out std_logic_vector(15 downto 0); o_mgt_rx_charisk : out std_logic_vector( 1 downto 0) ); end component; end package v6vlx_gtxe1_pkg;