firmware_vhdl_evr320/README.md

General Information

The EVR320 Embedded Event Receiver (EEVR) is able to connect with a MRF Timing System. Mainly the EEVR is used to decode configurable events and use them in firmware as triggers.

Maintainer

Patric Bucher [patric.bucher@psi.ch] Jonas Purtschert [jonas.purtschert@psi.ch]

Authors

Waldemar Koprek [waldemar.koprek@psi.ch]
Goran Marinkovic [goran.marinkovic@psi.ch]
Patric Bucher [patric.bucher@psi.ch]
Jonas Purtschert [jonas.purtschert@psi.ch]

Documentation

See EVR320 Documentation

Changelog

See Changelog

What belongs into this Library

All components and wrappers to connect various buses (AXI4, TOSCA-II, ..) and to use on different Xilinx FPGA's.

Examples for things that belong into this library:

• Event Decoder / Core Functionality
• Different MGT types

Examples for things that do not belong into this library:

• Vivado IP Packager related files -> belong to separate git repo

Dependencies

Synthesis

• Libraries/Firmware/VHDL/psi_common (https://github.com/paulscherrerinstitute/psi_common)

Simulation

• Libraries/Firmware/TCL/PsiSim
• Libraries/Firmware/VHDL/psi_common (https://github.com/paulscherrerinstitute/psi_common)
• Libraries/Firmware/VHDL/UVVM (https://github.com/UVVM/UVVM)

with IFC1210 Bindings

• Libraries/BoardSupport/IFC1210/tosca2