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AEK_8220_Libraries:master AEK_8220_Libraries:latency_measure AEK_8220_Libraries:hipa_debug AEK_8220_Libraries:latfix AEK_8220_Libraries:develop AEK_8220_Libraries:version3
AEK_8220_Libraries:2.3 AEK_8220_Libraries:2.2 AEK_8220_Libraries:2.1
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compare: AEK_8220_Libraries:develop
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AEK_8220_Libraries:master AEK_8220_Libraries:latency_measure AEK_8220_Libraries:hipa_debug AEK_8220_Libraries:latfix AEK_8220_Libraries:develop AEK_8220_Libraries:version3
AEK_8220_Libraries:2.3 AEK_8220_Libraries:2.2 AEK_8220_Libraries:2.1

4 Commits
version3 ... develop

Author SHA1 Message Date
stef_b
a482d8dc31 BUGFIX: for ISE 2019-10-02 16:49:53 +02:00
stef_b
b0c2476978 CLEANUP: getting rid of std_logic_unsigned library when unnecessary + sigasi project added 2019-10-02 16:24:19 +02:00
stef_b
7a1d49eb2f LIB: use only necessary libraries 2019-10-02 09:20:12 +02:00
stef_b
36a4dcb761 BUGFIX: UVVM adaptations pkg removed & unused library from wrapper, MTI_SE 10.6... 2019-10-01 16:45:10 +02:00
18 changed files with 29357 additions and 34308 deletions
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5
Changelog.md
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@@ -1,8 +1,3 @@
## 3.0
* Added Simulation
* Added Decoder streaming output
* Changed Register and Memory Address Map
## 2.2
* Added Features

14
Sigasi/.library_mapping.xml Normal file
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@@ -0,0 +1,14 @@
<?xml version="1.0" encoding="UTF-8"?>
<com.sigasi.hdt.shared.librarymapping.model:LibraryMappings xmlns:com.sigasi.hdt.shared.librarymapping.model="com.sigasi.hdt.vhdl.scoping.librarymapping" Version="2">
<Mappings Location="Common Libraries/IEEE" Library="ieee"/>
<Mappings Location="Common Libraries" Library="not mapped"/>
<Mappings Location="Common Libraries/psi_common/generators" Library="not mapped"/>
<Mappings Location="Common Libraries/unisim/primitive" Library="not mapped"/>
<Mappings Location="Common Libraries/unisim/secureip" Library="not mapped"/>
<Mappings Location="Common Libraries/STD" Library="std"/>
<Mappings Location="Common Libraries/tosca2" Library="tosca2"/>
<Mappings Location="Common Libraries/unisim" Library="unisim"/>
<Mappings Location="Common Libraries/UVVM" Library="uvvm_util"/>
<Mappings Location="" Library="work"/>
<Mappings Location="Common Libraries/psi_common" Library="work"/>
</com.sigasi.hdt.shared.librarymapping.model:LibraryMappings>

75
Sigasi/.project Normal file
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@@ -0,0 +1,75 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>evr320</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.sigasi.hdt.vhdl.ui.vhdlNature</nature>
<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
</natures>
<linkedResources>
<link>
<name>Common Libraries</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>hdl</name>
<type>2</type>
<locationURI>PARENT-1-PROJECT_LOC/hdl</locationURI>
</link>
<link>
<name>tb</name>
<type>2</type>
<locationURI>PARENT-1-PROJECT_LOC/tb</locationURI>
</link>
<link>
<name>Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt</name>
<type>1</type>
<locationURI>sigasiresource:/vhdl/readme2.txt</locationURI>
</link>
<link>
<name>Common Libraries/IEEE</name>
<type>2</type>
<locationURI>sigasiresource:/vhdl/2008/IEEE</locationURI>
</link>
<link>
<name>Common Libraries/STD</name>
<type>2</type>
<locationURI>sigasiresource:/vhdl/2008/STD</locationURI>
</link>
<link>
<name>Common Libraries/UVVM</name>
<type>2</type>
<locationURI>PARENT-2-PROJECT_LOC/UVVM</locationURI>
</link>
<link>
<name>Common Libraries/psi_common</name>
<type>2</type>
<locationURI>PARENT-2-PROJECT_LOC/psi_common</locationURI>
</link>
<link>
<name>Common Libraries/tosca2</name>
<type>2</type>
<locationURI>PARENT-4-PROJECT_LOC/BoardSupport/IFC1210/tosca2</locationURI>
</link>
<link>
<name>Common Libraries/unisim</name>
<type>2</type>
<locationURI>SIGASI_TOOLCHAIN_XILINX_ISE/vhdl/src/unisims</locationURI>
</link>
<link>
<name>Common Libraries/IEEE/Synopsys</name>
<type>2</type>
<locationURI>sigasiresource:/vhdl/2008/IEEE%20Synopsys</locationURI>
</link>
</linkedResources>
</projectDescription>

1
Sigasi/.settings/com.sigasi.hdt.vhdl.version.prefs Normal file
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@@ -0,0 +1 @@
<project>=2008

5
Sigasi/.settings/org.eclipse.core.resources.prefs Normal file
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@@ -0,0 +1,5 @@
eclipse.preferences.version=1
encoding//Common\ Libraries/IEEE=utf-8
encoding//Common\ Libraries/IEEE/Synopsys=utf-8
encoding//Common\ Libraries/STD=utf-8
encoding/Common\ Libraries=utf-8

62719
doc/evr320.rtf
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doc/evr320.vsd
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doc/evr_register_mapping.xlsx
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63
hdl/evr320_buffer.vhd
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@@ -4,14 +4,15 @@
-- Unit : evr320_buffer.vhd
-- Author : Waldemar Koprek, Section Diagnostic
-- Goran Marinkovic, Section Diagnostic
-- Benoît Stef, Section DSP
--------------------------------------------------------------------------------
-- Copyright© PSI, Section Diagnostic
--------------------------------------------------------------------------------
-- Comment :
-- Comment : modif 02.10.2019 - numeric_std instead of std_logic_unsigned
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
@@ -89,20 +90,28 @@ begin
if rising_edge(clka) then
if (ena = '1') then
if (wea = '1') then
RAM(conv_integer(page_addr_clka & addra)) := dia;
RAM(to_integer(unsigned(page_addr_clka & addra))) := dia;
end if;
end if;
end if;
end process;
process (clkb)
variable concat7to0_v : std_logic_vector(addrb'high+3 downto 0);
variable concat15to8_v : std_logic_vector(addrb'high+3 downto 0);
variable concat23to16_v : std_logic_vector(addrb'high+3 downto 0);
variable concat31to24_v : std_logic_vector(addrb'high+3 downto 0);
begin
if rising_edge(clkb) then
if (enb = '1') then
dob( 7 downto 0) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "00"));
dob(15 downto 8) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "01"));
dob(23 downto 16) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "10"));
dob(31 downto 24) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "11"));
if (enb = '1') then
concat7to0_v := page_addr_clkb( 3) & addrb & "00";
concat15to8_v := page_addr_clkb( 3) & addrb & "01";
concat23to16_v := page_addr_clkb( 3) & addrb & "10";
concat31to24_v := page_addr_clkb( 3) & addrb & "11";
dob( 7 downto 0) <= RAM(to_integer(unsigned( concat7to0_v)));
dob(15 downto 8) <= RAM(to_integer(unsigned( concat15to8_v)));
dob(23 downto 16) <= RAM(to_integer(unsigned(concat23to16_v)));
dob(31 downto 24) <= RAM(to_integer(unsigned(concat31to24_v)));
end if;
end if;
end process;
@@ -117,9 +126,9 @@ begin
if (ena = '1') then
if (wea = '1') then
if (addra(0) = '1') then
RAM_ODD (conv_integer(page_addr_clka & addra(addra'high downto 1))) := dia;
RAM_ODD (to_integer(unsigned(page_addr_clka & addra(addra'high downto 1)))) := dia;
else
RAM_EVEN(conv_integer(page_addr_clka & addra(addra'high downto 1))) := dia;
RAM_EVEN(to_integer(unsigned((page_addr_clka & addra(addra'high downto 1))))) := dia;
end if;
end if;
end if;
@@ -127,17 +136,33 @@ begin
end process;
process (clkb)
variable concat7to0_v : std_logic_vector(addrb'high+3 downto 0);
variable concat15to8_v : std_logic_vector(addrb'high+3 downto 0);
variable concat23to16_v : std_logic_vector(addrb'high+3 downto 0);
variable concat31to24_v : std_logic_vector(addrb'high+3 downto 0);
variable concat39to32_v : std_logic_vector(addrb'high+3 downto 0);
variable concat47to40_v : std_logic_vector(addrb'high+3 downto 0);
variable concat55to48_v : std_logic_vector(addrb'high+3 downto 0);
variable concat63to56_v : std_logic_vector(addrb'high+3 downto 0);
begin
if rising_edge(clkb) then
if (enb = '1') then
dob( 7 downto 0) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "00"));
dob(15 downto 8) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "00"));
dob(23 downto 16) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "01"));
dob(31 downto 24) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "01"));
dob(39 downto 32) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "10"));
dob(47 downto 40) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "10"));
dob(55 downto 48) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "11"));
dob(63 downto 56) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "11"));
if (enb = '1') then
concat7to0_v := page_addr_clkb( 3) & addrb & "00";
concat15to8_v := page_addr_clkb( 3) & addrb & "00";
concat23to16_v := page_addr_clkb( 3) & addrb & "01";
concat31to24_v := page_addr_clkb( 3) & addrb & "01";
concat39to32_v := page_addr_clkb( 3) & addrb & "10";
concat47to40_v := page_addr_clkb( 3) & addrb & "10";
concat55to48_v := page_addr_clkb( 3) & addrb & "11";
concat63to56_v := page_addr_clkb( 3) & addrb & "11";
dob( 7 downto 0) <= RAM_EVEN(to_integer(unsigned(concat7to0_v )));
dob(15 downto 8) <= RAM_ODD (to_integer(unsigned(concat15to8_v )));
dob(23 downto 16) <= RAM_EVEN(to_integer(unsigned(concat23to16_v )));
dob(31 downto 24) <= RAM_ODD (to_integer(unsigned(concat31to24_v )));
dob(39 downto 32) <= RAM_EVEN(to_integer(unsigned(concat39to32_v )));
dob(47 downto 40) <= RAM_ODD (to_integer(unsigned(concat47to40_v )));
dob(55 downto 48) <= RAM_EVEN(to_integer(unsigned(concat55to48_v )));
dob(63 downto 56) <= RAM_ODD (to_integer(unsigned(concat63to56_v )));
end if;
end if;
end process;

3
hdl/evr320_data_filter.vhd
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@@ -8,9 +8,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
entity evr320_data_filter is
generic (

207
hdl/evr320_decoder.vhd
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@@ -5,20 +5,19 @@
-- Author : Waldemar Koprek, Section Diagnostic
-- Goran Marinkovic, Section Diagnostic
-- Patric Bucher, Section DSV
-- Benoît Stef, Section DSP
--------------------------------------------------------------------------------
-- Copyright© PSI, Section Diagnostic
--------------------------------------------------------------------------------
-- Comment :
-- Comment : Rewrite code to be complient with numeric_std
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.evr320_pkg.all;
entity evr320_decoder is
@@ -48,7 +47,7 @@ entity evr320_decoder is
i_evr_params : in typ_evr320_params;
o_event_recorder_stat : out typ_evt_rec_status;
i_event_recorder_ctrl : in typ_evt_rec_ctrl;
i_mem_addr : in std_logic_vector(13 downto 0);
i_mem_addr : in std_logic_vector(11 downto 0);
o_mem_data : out std_logic_vector(MEM_DATA_WIDTH - 1 downto 0);
--------------------------------------------------------------------------
-- User stream interface User clock
@@ -80,39 +79,14 @@ architecture behavioral of evr320_decoder is
-- Framing
constant C_KCHAR_START : std_logic_vector( 7 downto 0) := X"5C";
constant C_KCHAR_END : std_logic_vector( 7 downto 0) := X"3C";
-- system events
constant C_EVENT_NULL : std_logic_vector( 7 downto 0) := X"00";
constant C_EVENT_SEC_0 : std_logic_vector( 7 downto 0) := X"70";
constant C_EVENT_SEC_1 : std_logic_vector( 7 downto 0) := X"71";
constant C_EVENT_STOP_LOG : std_logic_vector( 7 downto 0) := X"79";
constant C_EVENT_HEARTBEAT : std_logic_vector( 7 downto 0) := X"7A";
constant C_EVENT_SYNC_PRESCA : std_logic_vector( 7 downto 0) := X"7B";
constant C_EVENT_TIM_CNT_INC : std_logic_vector( 7 downto 0) := X"7C";
constant C_EVENT_TIM_CNT_RST : std_logic_vector( 7 downto 0) := X"7D";
constant C_EVENT_BEACON : std_logic_vector( 7 downto 0) := X"7E";
constant C_EVENT_END_OF_SEQ : std_logic_vector( 7 downto 0) := X"7F";
-- Events received
type usr_events_type is array (0 to 3) of std_logic_vector( 3 downto 0);
signal usr_events : usr_events_type := (others => (others => '0'));
signal cs_timeout_cnt : std_logic_vector(23 downto 0) := (others => '0');
signal cs_min_cnt : std_logic_vector(31 downto 0) := (others => '0');
signal cs_min_time : std_logic_vector(31 downto 0) := (others => '0');
signal cs_timeout_cnt : unsigned(23 downto 0) := (others => '0');
signal cs_min_cnt : unsigned(31 downto 0) := (others => '0');
signal cs_min_time : unsigned(31 downto 0) := (others => '0');
signal evr_stable : std_logic := '0';
-- Frame fsm
-- type frame_fsm_type is
-- (
-- frame_idle,
-- frame_addr_gap,
-- frame_addr,
-- frame_data_gap,
-- frame_data,
-- frame_chk1_gap,
-- frame_chk1,
-- frame_chk2_gap,
-- frame_chk2
-- );
-- signal frame_fsm : frame_fsm_type;
-- signal frame_fsm : frame_fsm_type;
constant frame_idle : std_logic_vector( 3 downto 0) := "0000";
constant frame_addr_gap : std_logic_vector( 3 downto 0) := "0001";
constant frame_addr : std_logic_vector( 3 downto 0) := "0010";
@@ -172,13 +146,17 @@ architecture behavioral of evr320_decoder is
constant mem_ctrl_rd : std_logic_vector( 1 downto 0) := "11";
signal mem_fsm : std_logic_vector( 1 downto 0) := "00";
-- Data memory address
signal mem_addr : std_logic_vector(13 downto 0);
signal mem_addr : std_logic_vector(11 downto 0);
-- Data memory write
signal mem_data_wren : std_logic := '0';
signal mem_data_wr_addr : std_logic_vector(10 downto 0) := (others => '0');
signal mem_data_wr_byte : std_logic_vector( 7 downto 0) := (others => '0');
-- Data memory read
signal mem_data_dpram : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
signal mem_data_event0 : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
signal mem_data_event1 : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
signal mem_data_event2 : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
signal mem_data_event3 : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
-- Event Recorder
signal sos_event : std_logic_vector( 3 downto 0) := (others => '0');
signal usr_events_save : std_logic := '0';
@@ -268,7 +246,7 @@ begin
-- Address Alignment for 32/64-bit Data Width
-----------------------------------------------------------------------------
gen_addr_align64: if MEM_DATA_WIDTH = 64 generate
mem_addr <= i_mem_addr(12 downto 0) & '0';
mem_addr <= i_mem_addr(10 downto 0) & '0';
end generate gen_addr_align64;
gen_addr_align32: if MEM_DATA_WIDTH = 32 generate
@@ -289,7 +267,7 @@ begin
if (i_mgt_rst = '1') then
evr_stable <= '0';
else
if ((cs_min_cnt > i_evr_params.cs_min_cnt) and (cs_min_time > i_evr_params.cs_min_time) and (cs_timeout_cnt < X"15CA20")) then
if ((cs_min_cnt > unsigned(i_evr_params.cs_min_cnt)) and (cs_min_time > unsigned(i_evr_params.cs_min_time)) and (cs_timeout_cnt < X"15CA20")) then
evr_stable <= '1';
else
evr_stable <= '0';
@@ -337,7 +315,7 @@ begin
cs_timeout_cnt <= X"000000";
else
if (cs_timeout_cnt /= X"FFFFFF") then
cs_timeout_cnt <= cs_timeout_cnt + X"000001";
cs_timeout_cnt <= cs_timeout_cnt + 1;--X"000001";
end if;
end if;
end if;
@@ -356,7 +334,7 @@ begin
if (frame_ctrl_wren = '1') then
if (frame_chk_ok = '1') then
if (cs_min_cnt /= X"FFFFFFFF") then
cs_min_cnt <= cs_min_cnt + X"00000001";
cs_min_cnt <= cs_min_cnt + 1;--X"00000001";
end if;
else
cs_min_cnt <= X"00000000";
@@ -450,7 +428,7 @@ begin
when frame_idle =>
frame_data_wr_addr_cnt <= (others => '0');
when frame_addr =>
frame_data_wr_id <= frame_data_wr_id + X"01";
frame_data_wr_id <= std_logic_vector(unsigned(frame_data_wr_id) + 1);
frame_data_wr_addr_cnt <= "0000" & i_mgt_rx_data(15 downto 8) & "0000";
segment_addr_wren <= '1';
when frame_data =>
@@ -459,7 +437,7 @@ begin
frame_data_wren <= '0';
else
frame_data_wren <= not frame_data_full;
frame_data_wr_addr_cnt <= frame_data_wr_addr_cnt + X"0001";
frame_data_wr_addr_cnt <= std_logic_vector(unsigned(frame_data_wr_addr_cnt) + 1);
frame_data_wr_addr <= frame_data_wr_addr_cnt(10 downto 0);
frame_data_wr_byte <= i_mgt_rx_data(15 downto 8);
end if;
@@ -481,7 +459,7 @@ begin
frame_chk <= X"FFFF";
when frame_addr | frame_data =>
if (i_mgt_rx_charisk = "00") then
frame_chk <= frame_chk - (X"00" & i_mgt_rx_data(15 downto 8));
frame_chk <= std_logic_vector(unsigned(frame_chk) - unsigned(i_mgt_rx_data(15 downto 8)));
end if;
when others =>
null;
@@ -703,12 +681,12 @@ begin
-----------------------------------------------------------------------------
-- Data memory selector
-----------------------------------------------------------------------------
-- Memory Map (byte-address):
-- * Segmented Data Buffer: 0x9000 - 0x97FF
-- * Event Recorder: 0xB000 - 0xBFFF
o_mem_data <= mem_data_dpram when (mem_addr(13 downto 9) = "10010") else
mem_data_event_recorder when (mem_addr(13 downto 10) = "1011") else
x"DEADC0DE";
o_mem_data <= mem_data_dpram when (mem_addr(11 downto 9) = "000") else
mem_data_event0 when (mem_addr(11 downto 9) = "001") else
mem_data_event1 when (mem_addr(11 downto 9) = "010") else
mem_data_event2 when (mem_addr(11 downto 9) = "011") else
mem_data_event3 when (mem_addr(11 downto 9) = "100") else
mem_data_event_recorder;
-----------------------------------------------------------------------------
-- Data Memory
@@ -736,6 +714,99 @@ begin
dob => mem_data_dpram
);
-----------------------------------------------------------------------------
-- Data Memory
-- write port - timing decoder
-- read port - usr domain
-----------------------------------------------------------------------------
evr320_event0_inst: entity work.evr320_buffer
generic map
(
MEM_SIZE_BYTE => 2048,
MEM_DOB_WIDTH => MEM_DATA_WIDTH
)
port map
(
-- port a
clka => i_mgt_rx_clk,
ena => HIGH,
wea => mem_data_wren,
addra => mem_data_wr_addr,
dia => mem_data_wr_byte,
page => usr_events( 0)( 3),
-- port b
clkb => i_usr_clk,
enb => HIGH,
addrb => mem_addr( 8 downto MEM_ADDR_LSB),
dob => mem_data_event0
);
evr320_event1_inst: entity work.evr320_buffer
generic map
(
MEM_SIZE_BYTE => 2048,
MEM_DOB_WIDTH => MEM_DATA_WIDTH
)
port map
(
-- port a
clka => i_mgt_rx_clk,
ena => HIGH,
wea => mem_data_wren,
addra => mem_data_wr_addr,
dia => mem_data_wr_byte,
page => usr_events( 1)( 3),
-- port b
clkb => i_usr_clk,
enb => HIGH,
addrb => mem_addr( 8 downto MEM_ADDR_LSB),
dob => mem_data_event1
);
evr320_event2_inst: entity work.evr320_buffer
generic map
(
MEM_SIZE_BYTE => 2048,
MEM_DOB_WIDTH => MEM_DATA_WIDTH
)
port map
(
-- port a
clka => i_mgt_rx_clk,
ena => HIGH,
wea => mem_data_wren,
addra => mem_data_wr_addr,
dia => mem_data_wr_byte,
page => usr_events( 2)( 3),
-- port b
clkb => i_usr_clk,
enb => HIGH,
addrb => mem_addr( 8 downto MEM_ADDR_LSB),
dob => mem_data_event2
);
evr320_event3_inst: entity work.evr320_buffer
generic map
(
MEM_SIZE_BYTE => 2048,
MEM_DOB_WIDTH => MEM_DATA_WIDTH
)
port map
(
-- port a
clka => i_mgt_rx_clk,
ena => HIGH,
wea => mem_data_wren,
addra => mem_data_wr_addr,
dia => mem_data_wr_byte,
page => usr_events( 3)( 3),
-- port b
clkb => i_usr_clk,
enb => HIGH,
addrb => mem_addr( 8 downto MEM_ADDR_LSB),
dob => mem_data_event3
);
-------------------------------------------------------------------------
-- async fifo for streaming interface
-------------------------------------------------------------------------
@@ -817,36 +888,25 @@ begin
-- timestamp for event and segement tagging
if (timestamp_cnt /= X"FFFF_FFFF") then
timestamp_cnt <= timestamp_cnt + X"0000_0001";
timestamp_cnt <= std_logic_vector(unsigned(timestamp_cnt) + 1);
end if;
-- only run event recorder when stable operation
if ( (i_event_recorder_ctrl.event_enable = '1') and (i_mgt_rx_charisk( 0) = '0') and (evr_stable = '1')) then
-- filter standard events (user events = 0x01-0x6F, 0x72-0x78, 0x80-0xFF)
if ( or_reduce(i_mgt_rx_data(7 downto 0)) = '1' and (i_mgt_rx_data(7 downto 4) /= X"7")) then
-- if ( i_mgt_rx_data(7 downto 0) /= C_EVENT_NULL and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_SEC_0 and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_SEC_1 and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_STOP_LOG and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_HEARTBEAT and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_SYNC_PRESCA and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_TIM_CNT_INC and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_TIM_CNT_RST and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_BEACON and
-- i_mgt_rx_data(7 downto 0) /= C_EVENT_END_OF_SEQ ) then
if unsigned(i_mgt_rx_data(7 downto 0)) /= 0 and i_mgt_rx_data(7 downto 4) /= X"7" then
usr_events_nr <= i_mgt_rx_data(7 downto 0);
-- write event nr memory
if (usr_events_addr /= X"FF") then
usr_events_save <= '1';
usr_events_addr <= usr_events_addr + X"01";
usr_events_addr <= std_logic_vector(unsigned(usr_events_addr) + 1);
end if;
-- count all user events
if (usr_events_cnt /= X"FFFF_FFFF") then
usr_events_cnt <= usr_events_cnt + X"0000_0001";
usr_events_cnt <= std_logic_vector(unsigned(usr_events_cnt) + 1);
end if;
-- start-of-sequence, trigger event for event recorder
@@ -863,7 +923,7 @@ begin
end if;
-- set flag for appeared event
all_events_flags(conv_integer(i_mgt_rx_data(7 downto 0))) <= '1';
all_events_flags(to_integer(unsigned(i_mgt_rx_data(7 downto 0)))) <= '1';
end if;
end if;
@@ -927,11 +987,11 @@ begin
--------------------------------------------------------------------------
-- Memory Selector Event Recorder
--------------------------------------------------------------------------
mem_data_event_recorder <= mem_data_dpram_sos when (mem_addr(13 downto 9) = B"1011_0") else -- 2K
mem_data_event_nr_timestamp when (mem_addr(13 downto 8) = B"1011_10") else -- 1K
mem_data_segment_timestamp when (mem_addr(13 downto 7) = B"1011_110") else -- 512B
mem_data_event_nr when (mem_addr(13 downto 6) = B"1011_1110") else -- 256B
mem_data_event_flag when (mem_addr(13 downto 6) = B"1011_1111") else -- 256B
mem_data_event_recorder <= mem_data_dpram_sos when (mem_addr(11 downto 9) = B"101") else -- 2K
mem_data_event_nr_timestamp when (mem_addr(11 downto 8) = B"1100") else -- 1K
mem_data_segment_timestamp when (mem_addr(11 downto 7) = B"1101_0") else -- 512B
mem_data_event_nr when (mem_addr(11 downto 6) = B"1101_10") else -- 256B
mem_data_event_flag when (mem_addr(11 downto 6) = B"1101_11") else -- 256B
(others => '0');
@@ -1042,7 +1102,8 @@ begin
-- Event Flags of all Events
--------------------------------------------------------------------------
prc_event_flags: process(i_usr_clk)
variable v_addr : integer range 0 to 255;
variable v_addr : integer range 0 to 255;
variable v_addr_slv : std_logic_vector(7 downto 0);
begin
if (i_usr_clk'event and (i_usr_clk = '1')) then
-- sync to usr clk
@@ -1050,9 +1111,11 @@ begin
all_events_flags_sync2 <= all_events_flags_sync1;
-- address fragment of vector / expand bit to bytes for data read
v_addr := conv_integer(mem_addr(5 downto MEM_ADDR_LSB) & LOW_slv(1 + MEM_ADDR_LSB downto 0));
v_addr_slv := mem_addr(5 downto MEM_ADDR_LSB) & LOW_slv(1 + MEM_ADDR_LSB downto 0);
v_addr := to_integer(unsigned(v_addr_slv));
mem_data_event_flag <= bit2byte(all_events_flags_sync2(v_addr + MEM_DATA_BYTES - 1 downto v_addr));
end if;
end if;
end process;

65
hdl/evr320_dpram.vhd
View File

@@ -4,14 +4,15 @@
-- Unit : evr320_dpram.vhd
-- Author : Waldemar Koprek, Section Diagnostic
-- Goran Marinkovic, Section Diagnostic
-- Benoit Stef, Section DSP
--------------------------------------------------------------------------------
-- Copyright© PSI, Section Diagnostic
--------------------------------------------------------------------------------
-- Comment :
-- Comment : modif 02.10.2019 - numeric_std instead std_logic_unsigned
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity evr320_dpram is
@@ -59,20 +60,29 @@ begin
if rising_edge(clka) then
if (ena = '1') then
if (wea = '1') then
RAM(conv_integer(addra)) := dia;
RAM(to_integer(unsigned(addra))) := dia;
end if;
end if;
end if;
end process;
process (clkb)
variable concat7to0_v : std_logic_vector(addrb'high+2 downto 0);
variable concat15to8_v : std_logic_vector(addrb'high+2 downto 0);
variable concat23to16_v : std_logic_vector(addrb'high+2 downto 0);
variable concat31to24_v : std_logic_vector(addrb'high+2 downto 0);
begin
if rising_edge(clkb) then
if (enb = '1') then
dob( 7 downto 0) <= RAM(conv_integer(addrb & "00"));
dob(15 downto 8) <= RAM(conv_integer(addrb & "01"));
dob(23 downto 16) <= RAM(conv_integer(addrb & "10"));
dob(31 downto 24) <= RAM(conv_integer(addrb & "11"));
if (enb = '1') then
concat7to0_v := addrb & "00";
concat15to8_v := addrb & "01";
concat23to16_v := addrb & "10";
concat31to24_v := addrb & "11";
--
dob( 7 downto 0) <= RAM(to_integer(unsigned( concat7to0_v)));
dob(15 downto 8) <= RAM(to_integer(unsigned( concat15to8_v)));
dob(23 downto 16) <= RAM(to_integer(unsigned(concat23to16_v)));
dob(31 downto 24) <= RAM(to_integer(unsigned(concat31to24_v)));
end if;
end if;
end process;
@@ -87,9 +97,9 @@ begin
if (ena = '1') then
if (wea = '1') then
if (addra(0) = '1') then
RAM_ODD (conv_integer(addra(addra'high downto 1))) := dia;
RAM_ODD (to_integer(unsigned(addra(addra'high downto 1)))) := dia;
else
RAM_EVEN(conv_integer(addra(addra'high downto 1))) := dia;
RAM_EVEN(to_integer(unsigned(addra(addra'high downto 1)))) := dia;
end if;
end if;
end if;
@@ -97,17 +107,34 @@ begin
end process;
process (clkb)
variable concat7to0_v : std_logic_vector(addrb'high+2 downto 0);
variable concat15to8_v : std_logic_vector(addrb'high+2 downto 0);
variable concat23to16_v : std_logic_vector(addrb'high+2 downto 0);
variable concat31to24_v : std_logic_vector(addrb'high+2 downto 0);
variable concat39to32_v : std_logic_vector(addrb'high+2 downto 0);
variable concat47to40_v : std_logic_vector(addrb'high+2 downto 0);
variable concat55to48_v : std_logic_vector(addrb'high+2 downto 0);
variable concat63to56_v : std_logic_vector(addrb'high+2 downto 0);
begin
if rising_edge(clkb) then
if (enb = '1') then
dob( 7 downto 0) <= RAM_EVEN(conv_integer(addrb & "00"));
dob(15 downto 8) <= RAM_ODD (conv_integer(addrb & "00"));
dob(23 downto 16) <= RAM_EVEN(conv_integer(addrb & "01"));
dob(31 downto 24) <= RAM_ODD (conv_integer(addrb & "01"));
dob(39 downto 32) <= RAM_EVEN(conv_integer(addrb & "10"));
dob(47 downto 40) <= RAM_ODD (conv_integer(addrb & "10"));
dob(55 downto 48) <= RAM_EVEN(conv_integer(addrb & "11"));
dob(63 downto 56) <= RAM_ODD (conv_integer(addrb & "11"));
if (enb = '1') then
concat7to0_v :=addrb & "00";
concat15to8_v :=addrb & "00";
concat23to16_v :=addrb & "01";
concat31to24_v :=addrb & "01";
concat39to32_v :=addrb & "10";
concat47to40_v :=addrb & "10";
concat55to48_v :=addrb & "11";
concat63to56_v :=addrb & "11";
--
dob( 7 downto 0) <= RAM_EVEN(to_integer(unsigned(concat7to0_v )));
dob(15 downto 8) <= RAM_ODD (to_integer(unsigned(concat15to8_v )));
dob(23 downto 16) <= RAM_EVEN(to_integer(unsigned(concat23to16_v)));
dob(31 downto 24) <= RAM_ODD (to_integer(unsigned(concat31to24_v)));
dob(39 downto 32) <= RAM_EVEN(to_integer(unsigned(concat39to32_v)));
dob(47 downto 40) <= RAM_ODD (to_integer(unsigned(concat47to40_v)));
dob(55 downto 48) <= RAM_EVEN(to_integer(unsigned(concat55to48_v)));
dob(63 downto 56) <= RAM_ODD (to_integer(unsigned(concat63to56_v)));
end if;
end if;
end process;

78
hdl/evr320_ifc1210_wrapper.vhd
View File

@@ -10,8 +10,7 @@
-- ---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library tosca2;
use tosca2.tosca2_glb_pkg.all;
@@ -22,65 +21,66 @@ use work.v6vlx_gtxe1_pkg.all;
entity evr320_ifc1210_wrapper is
generic(
g_MGT_LOCATION : string := "GTXE1_X0Y16"; -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY : string := "SFEL"; -- "HIPA" | "SFEL"
g_EVENT_RECORDER : boolean := false; -- enable/disable Event Recorder functionality
g_XUSER_CLK_FREQ : natural := 125000000 -- Xuser Clk Frequency in Hz
g_MGT_LOCATION : string := "GTXE1_X0Y16"; -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY : string := "SFEL"; -- "HIPA" | "SFEL"
g_EVENT_RECORDER : boolean := false; -- enable/disable Event Recorder functionality
g_XUSER_CLK_FREQ : natural := 125000000 -- Xuser Clk Frequency in Hz
);
port(
tick1sec_i : in std_logic;
port(
-- ------------------------------------------------------------------------
-- Debug interface
-- ------------------------------------------------------------------------
debug_clk : out std_logic;
debug : out std_logic_vector(127 downto 0);
debug_clk : out std_logic;
debug : out std_logic_vector(127 downto 0);
-- ------------------------------------------------------------------------
-- TOSCA2 TMEM Interface (xuser clock domain, 100-250MHz)
-- ------------------------------------------------------------------------
xuser_CLK: in std_logic;
xuser_RESET: in std_logic;
xuser_TMEM_ENA: in std_logic;
xuser_TMEM_WE: in std_logic_vector( 7 downto 0);
xuser_TMEM_ADD: in std_logic_vector(15 downto 3);
xuser_TMEM_DATW: in std_logic_vector(63 downto 0);
xuser_TMEM_DATR: out std_logic_vector(63 downto 0);
xuser_CLK : in std_logic;
xuser_RESET : in std_logic;
xuser_TMEM_ENA : in std_logic;
xuser_TMEM_WE : in std_logic_vector( 7 downto 0);
xuser_TMEM_ADD : in std_logic_vector(13 downto 3);
xuser_TMEM_DATW : in std_logic_vector(63 downto 0);
xuser_TMEM_DATR : out std_logic_vector(63 downto 0);
-- ------------------------------------------------------------------------
-- MGT Interface
-- ------------------------------------------------------------------------
mgt_refclk_i : in std_logic; -- MGT Reference Clock
mgt_sfp_los_i : in std_logic; -- SFP Loss of Signal (light on receiver)
mgt_rx_n : in std_logic; -- MGT RX N
mgt_rx_p : in std_logic; -- MGT RX P
mgt_tx_n : out std_logic; -- MGT TX N
mgt_tx_p : out std_logic; -- MGT TX P
mgt_status_o : out std_logic_vector(31 downto 0); -- MGT Status
mgt_control_i : in std_logic_vector(31 downto 0); -- MGT Control
mgt_refclk_i : in std_logic; -- MGT Reference Clock
mgt_sfp_los_i : in std_logic; -- SFP Loss of Signal (light on receiver)
mgt_rx_n : in std_logic; -- MGT RX N
mgt_rx_p : in std_logic; -- MGT RX P
mgt_tx_n : out std_logic; -- MGT TX N
mgt_tx_p : out std_logic; -- MGT TX P
mgt_status_o : out std_logic_vector(31 downto 0); -- MGT Status
mgt_control_i : in std_logic_vector(31 downto 0); -- MGT Control
---------------------------------------------------------------------------
-- User interface MGT clock
---------------------------------------------------------------------------
clk_evr_o : out std_logic; -- Recovered parallel clock from MGT
usr_events_o : out std_logic_vector( 3 downto 0); -- User defined event pulses with one clock cycle length
usr_events_ext_o : out std_logic_vector( 3 downto 0); -- User defined event pulses with four clock cycle length
sos_event_o : out std_logic; -- Start-of-Sequence Event
clk_evr_o : out std_logic; -- Recovered parallel clock from MGT
usr_events_o : out std_logic_vector( 3 downto 0); -- User defined event pulses with one clock cycle length
usr_events_ext_o : out std_logic_vector( 3 downto 0); -- User defined event pulses with four clock cycle length
sos_event_o : out std_logic; -- Start-of-Sequence Event
--------------------------------------------------------------------------
-- Decoder axi stream interface, User clock
--------------------------------------------------------------------------
stream_clk_i : in std_logic := '0';
stream_data_o : out std_logic_vector(7 downto 0);
stream_addr_o : out std_logic_vector(10 downto 0);
stream_valid_o : out std_logic
stream_clk_i : in std_logic := '0';
stream_data_o : out std_logic_vector(7 downto 0);
stream_addr_o : out std_logic_vector(10 downto 0);
stream_valid_o : out std_logic
);
end evr320_ifc1210_wrapper;
architecture rtl of evr320_ifc1210_wrapper is
-- --------------------------------------------------------------------------
-- Parameters
-- --------------------------------------------------------------------------
constant c_TOSCA2_DATA_WIDTH : integer := 64;
constant c_EVR_REG64_COUNT : integer := 16; -- unused, only documentation
constant c_EVR_MEM_SIZE : integer := 16384; -- unused, only documentation
-- constant c_EVR_REG64_COUNT : integer := 16; -- unused, only documentation
-- constant c_EVR_MEM_SIZE : integer := 16384; -- unused, only documentation
-- --------------------------------------------------------------------------
@@ -99,8 +99,8 @@ architecture rtl of evr320_ifc1210_wrapper is
signal mgt_reset_tmem_evr : std_logic; -- for legacy reasons, ifc1210 mgt control is in tmem_psi_generic part
signal mem_clk : std_logic;
signal mem_addr_evr : std_logic_vector(13 downto 0);
signal mem_addr_tosca : std_logic_vector(12 downto 0);
signal mem_addr_evr : std_logic_vector(11 downto 0);
signal mem_addr_tosca : std_logic_vector(10 downto 0);
signal mem_data : std_logic_vector(c_TOSCA2_DATA_WIDTH-1 downto 0);
signal evr_params : typ_evr320_params;
@@ -267,9 +267,7 @@ begin
clk_evr_o <= clk_evr;
mgt_status_o <= mgt_status;
debug <= debug_data;
end rtl;
-- ----------------------------------------------------------------------------
-- ////////////////////////////////////////////////////////////////////////////

102
hdl/evr320_timestamp.vhd
View File

@@ -4,17 +4,17 @@
-- Unit : evr320_timestamp.vhd
-- Author : Patric Bucher, Section DSV
-- Goran Marinkovic, Section Diagnostic
-- Benoît Stef, Section DSP
--------------------------------------------------------------------------------
-- Copyright© PSI, Section Diagnostic
--------------------------------------------------------------------------------
-- Comment :
-- Comment : modif 02.10.2019 - numeric_std instead of std_logic_unsigned
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity evr320_timestamp is
generic
(
@@ -90,28 +90,46 @@ begin
-----------------------------------------------------------------------------
dob_32bit: if MEM_DOB_WIDTH = 32 generate
-----------------------------------------------------------------------------
process (clka)
process (clka)
variable concat7to0_v : std_logic_vector(addra'high+3 downto 0);
variable concat15to8_v : std_logic_vector(addra'high+3 downto 0);
variable concat23to16_v : std_logic_vector(addra'high+3 downto 0);
variable concat31to24_v : std_logic_vector(addra'high+3 downto 0);
begin
if rising_edge(clka) then
if (ena = '1') then
if (wea = '1') then
RAM(conv_integer(page_addr_clka & addra & "00")) := dia( 7 downto 0);
RAM(conv_integer(page_addr_clka & addra & "01")) := dia(15 downto 8);
RAM(conv_integer(page_addr_clka & addra & "10")) := dia(23 downto 16);
RAM(conv_integer(page_addr_clka & addra & "11")) := dia(31 downto 24);
if (wea = '1') then
concat7to0_v := page_addr_clka & addra & "00";
concat15to8_v := page_addr_clka & addra & "01";
concat23to16_v := page_addr_clka & addra & "10";
concat31to24_v := page_addr_clka & addra & "11";
--
RAM(to_integer(unsigned( concat7to0_v))) := dia( 7 downto 0);
RAM(to_integer(unsigned( concat15to8_v))) := dia(15 downto 8);
RAM(to_integer(unsigned(concat23to16_v))) := dia(23 downto 16);
RAM(to_integer(unsigned(concat31to24_v))) := dia(31 downto 24);
end if;
end if;
end if;
end process;
process (clkb)
variable concat7to0_v : std_logic_vector(addrb'high+3 downto 0);
variable concat15to8_v : std_logic_vector(addrb'high+3 downto 0);
variable concat23to16_v : std_logic_vector(addrb'high+3 downto 0);
variable concat31to24_v : std_logic_vector(addrb'high+3 downto 0);
begin
if rising_edge(clkb) then
if (enb = '1') then
dob( 7 downto 0) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "00"));
dob(15 downto 8) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "01"));
dob(23 downto 16) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "10"));
dob(31 downto 24) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "11"));
if (enb = '1') then
concat7to0_v := page_addr_clkb( 3) & addrb & "00";
concat15to8_v := page_addr_clkb( 3) & addrb & "01";
concat23to16_v := page_addr_clkb( 3) & addrb & "10";
concat31to24_v := page_addr_clkb( 3) & addrb & "11";
--
dob( 7 downto 0) <= RAM(to_integer(unsigned(concat7to0_v)));
dob(15 downto 8) <= RAM(to_integer(unsigned(concat15to8_v )));
dob(23 downto 16) <= RAM(to_integer(unsigned(concat23to16_v)));
dob(31 downto 24) <= RAM(to_integer(unsigned(concat31to24_v)));
end if;
end if;
end process;
@@ -120,32 +138,58 @@ begin
-----------------------------------------------------------------------------
dob_64bit: if MEM_DOB_WIDTH = 64 generate
-----------------------------------------------------------------------------
process (clka)
process (clka)
variable concat7to0_v : std_logic_vector(addra'high+2 downto 0);
variable concat15to8_v : std_logic_vector(addra'high+2 downto 0);
variable concat23to16_v : std_logic_vector(addra'high+2 downto 0);
variable concat31to24_v : std_logic_vector(addra'high+2 downto 0);
begin
if rising_edge(clka) then
if (ena = '1') then
if (wea = '1') then
RAM_EVEN(conv_integer(page_addr_clka & addra & '0')) := dia( 7 downto 0);
RAM_ODD (conv_integer(page_addr_clka & addra & '0')) := dia(15 downto 8);
RAM_EVEN(conv_integer(page_addr_clka & addra & '1')) := dia(23 downto 16);
RAM_ODD (conv_integer(page_addr_clka & addra & '1')) := dia(31 downto 24);
if (wea = '1') then
concat7to0_v := page_addr_clka & addra & '0';
concat15to8_v := page_addr_clka & addra & '0';
concat23to16_v := page_addr_clka & addra & '1';
concat31to24_v := page_addr_clka & addra & '1';
--
RAM_EVEN(to_integer(unsigned(concat7to0_v ))) := dia( 7 downto 0);
RAM_ODD (to_integer(unsigned(concat15to8_v ))) := dia(15 downto 8);
RAM_EVEN(to_integer(unsigned(concat23to16_v ))) := dia(23 downto 16);
RAM_ODD (to_integer(unsigned(concat31to24_v ))) := dia(31 downto 24);
end if;
end if;
end if;
end process;
process (clkb)
variable concat7to0_v : std_logic_vector(addrb'high+3 downto 0);
variable concat15to8_v : std_logic_vector(addrb'high+3 downto 0);
variable concat23to16_v : std_logic_vector(addrb'high+3 downto 0);
variable concat31to24_v : std_logic_vector(addrb'high+3 downto 0);
variable concat39to32_v : std_logic_vector(addrb'high+3 downto 0);
variable concat47to40_v : std_logic_vector(addrb'high+3 downto 0);
variable concat55to48_v : std_logic_vector(addrb'high+3 downto 0);
variable concat63to56_v : std_logic_vector(addrb'high+3 downto 0);
begin
if rising_edge(clkb) then
if (enb = '1') then
dob( 7 downto 0) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "00"));
dob(15 downto 8) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "00"));
dob(23 downto 16) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "01"));
dob(31 downto 24) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "01"));
dob(39 downto 32) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "10"));
dob(47 downto 40) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "10"));
dob(55 downto 48) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "11"));
dob(63 downto 56) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "11"));
if (enb = '1') then
concat7to0_v := page_addr_clkb( 3) & addrb & "00";
concat15to8_v := page_addr_clkb( 3) & addrb & "00";
concat23to16_v := page_addr_clkb( 3) & addrb & "01";
concat31to24_v := page_addr_clkb( 3) & addrb & "01";
concat39to32_v := page_addr_clkb( 3) & addrb & "10";
concat47to40_v := page_addr_clkb( 3) & addrb & "10";
concat55to48_v := page_addr_clkb( 3) & addrb & "11";
concat63to56_v := page_addr_clkb( 3) & addrb & "11";
--
dob( 7 downto 0) <= RAM_EVEN(to_integer(unsigned( concat7to0_v)));
dob(15 downto 8) <= RAM_ODD (to_integer(unsigned( concat15to8_v)));
dob(23 downto 16) <= RAM_EVEN(to_integer(unsigned( concat23to16_v)));
dob(31 downto 24) <= RAM_ODD (to_integer(unsigned( concat31to24_v)));
dob(39 downto 32) <= RAM_EVEN(to_integer(unsigned( concat39to32_v)));
dob(47 downto 40) <= RAM_ODD (to_integer(unsigned( concat47to40_v)));
dob(55 downto 48) <= RAM_EVEN(to_integer(unsigned( concat55to48_v)));
dob(63 downto 56) <= RAM_ODD (to_integer(unsigned( concat63to56_v)));
end if;
end if;
end process;

18
hdl/evr320_tmem.vhd
View File

@@ -3,14 +3,15 @@
-- ---------------------------------------------------------------------------
-- Unit : evr320_tmem.vhd
-- Author : Patric Bucher
-- Benoît Stef
-- ---------------------------------------------------------------------------
-- Copyright© PSI, Section DSV
-- ---------------------------------------------------------------------------
-- Comment : TMEM address decoding for register and memory access to evr320.
-- modif 02.10.2019 - numeric_std only
-- ---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
@@ -29,7 +30,7 @@ entity evr320_tmem is
xuser_RESET : in std_logic;
xuser_TMEM_ENA : in std_logic;
xuser_TMEM_WE : in std_logic_vector( 7 downto 0);
xuser_TMEM_ADD : in std_logic_vector(15 downto 3);
xuser_TMEM_ADD : in std_logic_vector(13 downto 3);
xuser_TMEM_DATW : in std_logic_vector(63 downto 0);
xuser_TMEM_DATR : out std_logic_vector(63 downto 0);
---------------------------------------------------------------------------
@@ -42,7 +43,7 @@ entity evr320_tmem is
mgt_status_i : in std_logic_vector(31 downto 0);
mgt_reset_o : out std_logic;
mem_clk_o : out std_logic;
mem_addr_o : out std_logic_vector(12 downto 0);
mem_addr_o : out std_logic_vector(10 downto 0);
mem_data_i : in std_logic_vector(63 downto 0)
);
end evr320_tmem;
@@ -58,6 +59,7 @@ architecture rtl of evr320_tmem is
constant TMEM_ADDR_LSB : integer := 3; -- 64 bit
constant REG_ADDR_WIDTH : integer := integer(ceil(log2(real(NUM_REG64)))) + TMEM_ADDR_LSB;
constant REG_ADDR_MSB : integer := REG_ADDR_WIDTH - 1;
constant MEM_ADDR_START : std_logic_vector(7 downto 0) := X"10";
@@ -67,7 +69,7 @@ architecture rtl of evr320_tmem is
-- xuser tmem signals
signal xuser_TMEM_WE_reg : std_logic_vector( 7 downto 0) := (others => '0');
signal xuser_TMEM_ENA_reg : std_logic := '0';
signal xuser_TMEM_ADD_reg : std_logic_vector(15 downto 3) := (others => '0');
signal xuser_TMEM_ADD_reg : std_logic_vector(13 downto 3) := (others => '0');
signal xuser_TMEM_DATW_reg : std_logic_vector(63 downto 0) := (others => '0');
-- evr params
@@ -145,7 +147,7 @@ begin
begin
if (rising_edge(xuser_CLK)) then
if (xuser_TMEM_ENA_reg = '1') then
if (xuser_TMEM_ADD_reg(15 downto REG_ADDR_WIDTH) = 0) then
if (unsigned(xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH)) = 0) then
case xuser_TMEM_ADD_reg(REG_ADDR_MSB downto TMEM_ADDR_LSB) is
when X"0" => xuser_TMEM_DATR <= event_numbers_concat & X"0000" & mgt_status_evr; -- 64bit / ByteAddr 000
when X"1" => xuser_TMEM_DATR <= reserved(63 downto 32) & X"0000_00" & bit2byte(mgt_reset); -- 64bit / ByteAddr 008 --> 0x00C = not implemented in ifc1210
@@ -179,7 +181,7 @@ begin
er_error_ack <= er_error_ack(2 downto 0) & '0';
if (xuser_TMEM_ENA_reg = '1' and xuser_TMEM_ADD_reg(15 downto REG_ADDR_WIDTH) = 0) then
if (xuser_TMEM_ENA_reg = '1' and unsigned(xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH)) = 0) then
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"0" then --ByteAddr 000
-- if xuser_TMEM_WE_reg(0) = '1' then -read only- <= xuser_TMEM_DATW_reg( 7 downto 0); end if;
@@ -245,7 +247,7 @@ begin
-- Port mapping
-- --------------------------------------------------------------------------
mem_clk_o <= xuser_CLK;
mem_addr_o <= xuser_TMEM_ADD;
mem_addr_o <= std_logic_vector(unsigned(xuser_TMEM_ADD) - unsigned(MEM_ADDR_START));
evr_params_o <= (event_numbers, event_enable, cs_min_cnt, cs_min_time);
evr_evt_rec_control_o <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
mgt_reset_o <= mgt_reset;
@@ -255,4 +257,4 @@ begin
end rtl;
-- ----------------------------------------------------------------------------
-- ////////////////////////////////////////////////////////////////////////////
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------

14
sim/run.tcl
View File

@@ -5,9 +5,10 @@ set LibPath "../../../.."
# -------------------------------------------------------
set uvvm_lib $LibPath/Firmware/VHDL/UVVM/uvvm_util/sim/uvvm_util/
# compile lib if folder not exist:
#if {![file isdirectory $uvvm_lib]} {
#if {![file isdirectory $uvvm_lib]} {
# copy adapted pkg:
file copy -force ../tb/adaptations_pkg.vhd $LibPath/Firmware/VHDL/UVVM/uvvm_util/src/
# comment the line after because adaptation pkg is in uvvm_util lib already... stef.b
#file copy -force ../tb/adaptations_pkg.vhd $LibPath/Firmware/VHDL/UVVM/uvvm_util/src/
set last_dir [pwd]
cd $LibPath/Firmware/VHDL/UVVM/uvvm_util/script/
do compile_src.do
@@ -30,9 +31,12 @@ if {$jenkins == 1} {
vmap xilinxcorelib /home/modelsim/xilinx_libs/13.4/xilinxcorelib
vmap secureip /home/modelsim/xilinx_libs/13.4/secureip
} else {
vmap unisim C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/unisim
vmap xilinxcorelib C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/xilinxcorelib
vmap secureip C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/unisim
#vmap unisim C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/unisim
vmap unisim C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.6/nt/unisim
#vmap xilinxcorelib C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/xilinxcorelib
vmap xilinxcorelib C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.6/nt/xilinxcorelib
#vmap secureip C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/unisim
vmap secureip C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.6/nt/unisim
}
#Load dependencies TODO

290
tb/adaptations_pkg.vhd
View File

@@ -1,290 +0,0 @@
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
package adaptations_pkg is
constant C_ALERT_FILE_NAME : string := "_Alert.txt";
constant C_LOG_FILE_NAME : string := "_Log.txt";
constant C_SHOW_UVVM_UTILITY_LIBRARY_INFO : boolean := false; -- Set this to false when you no longer need the initial info
constant C_SHOW_UVVM_UTILITY_LIBRARY_RELEASE_INFO : boolean := false; -- Set this to false when you no longer need the release info
-------------------------------------------------------------------------------
-- Log format
-------------------------------------------------------------------------------
--UVVM: [<ID>] <time> <Scope> Msg
--PPPPPPPPIIIIII TTTTTTTT SSSSSSSSSSSSSS MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM
constant C_LOG_PREFIX : string := "UVVM: "; -- Note: ': ' is recommended as final characters
constant C_LOG_PREFIX_WIDTH : natural := C_LOG_PREFIX'length;
constant C_LOG_MSG_ID_WIDTH : natural := 18;
constant C_LOG_TIME_WIDTH : natural := 14; -- 3 chars used for unit eg. " ns"
constant C_LOG_TIME_BASE : time := ns; -- Unit in which time is shown in log (ns | ps)
constant C_LOG_TIME_DECIMALS : natural := 1; -- Decimals to show for given C_LOG_TIME_BASE
constant C_LOG_SCOPE_WIDTH : natural := 16;
constant C_LOG_LINE_WIDTH : natural := 200;
constant C_LOG_INFO_WIDTH : natural := C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH;
constant C_USE_BACKSLASH_N_AS_LF : boolean := true; -- If true interprets '\n' as Line feed
constant C_USE_BACKSLASH_R_AS_LF : boolean := true; -- If true, inserts an empty line if '\r'
-- is the first character of the string.
-- All others '\r' will be printed as is.
constant C_SINGLE_LINE_ALERT : boolean := false; -- If true prints alerts on a single line.
constant C_SINGLE_LINE_LOG : boolean := false; -- If true prints log messages on a single line.
constant C_TB_SCOPE_DEFAULT : string := "TB_SCOPE"; -- Default scope in test sequencer
constant C_LOG_TIME_TRUNC_WARNING : boolean := false; -- Yields a single TB_WARNING if time stamp truncated. Otherwise none
constant C_SHOW_LOG_ID : boolean := true; -- This constant has replaced the global_show_log_id
constant C_SHOW_LOG_SCOPE : boolean := true; -- This constant has replaced the global_show_log_scope
constant C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME : boolean := false;
constant C_USE_STD_STOP_ON_ALERT_STOP_LIMIT : boolean := true; -- true: break using std.env.stop, false: break using failure
shared variable shared_default_log_destination : t_log_destination := CONSOLE_AND_LOG;
-------------------------------------------------------------------------------
-- Verbosity control
-- NOTE: Do not enter new IDs without proper evaluation:
-- 1. Is it - or could it be covered by an existing ID
-- 2. Could it be combined with other needs for a more general new ID
-- Feel free to suggest new ID for future versions of UVVM Utility Library (support@bitvis.no)
-------------------------------------------------------------------------------
type t_msg_id is (
-- Bitvis utility methods
NO_ID, -- Used as default prior to setting actual ID when transfering ID as a field in a record
ID_UTIL_BURIED, -- Used for buried log messages where msg and scope cannot be modified from outside
ID_BITVIS_DEBUG, -- Bitvis internal ID used for UVVM debugging
ID_UTIL_SETUP, -- Used for Utility setup
ID_LOG_MSG_CTRL, -- Used inside Utility library only - when enabling/disabling msg IDs.
ID_ALERT_CTRL, -- Used inside Utility library only - when setting IGNORE or REGARD on various alerts.
ID_NEVER, -- Used for avoiding log entry. Cannot be enabled.
ID_FINISH_OR_STOP, -- Used when terminating the complete simulation - independent of why
ID_CLOCK_GEN, -- Used for logging when clock generators are enabled or disabled
ID_GEN_PULSE, -- Used for logging when a gen_pulse procedure starts pulsing a signal
ID_BLOCKING, -- Used for logging when using synchronisation flags
-- General
ID_POS_ACK, -- To write a positive acknowledge on a check
-- Directly inside test sequencers
ID_LOG_HDR, -- ONLY allowed in test sequencer, Log section headers
ID_LOG_HDR_LARGE, -- ONLY allowed in test sequencer, Large log section headers
ID_LOG_HDR_XL, -- ONLY allowed in test sequencer, Extra large log section headers
ID_SEQUENCER, -- ONLY allowed in test sequencer, Normal log (not log headers)
ID_SEQUENCER_SUB, -- ONLY allowed in test sequencer, Subprograms defined in sequencer
-- BFMs
ID_BFM, -- Used inside a BFM (to log BFM access)
ID_BFM_WAIT, -- Used inside a BFM to indicate that it is waiting for something (e.g. for ready)
ID_BFM_POLL, -- Used inside a BFM when polling until reading a given value. I.e. to show all reads until expected value found (e.g. for sbi_poll_until())
ID_BFM_POLL_SUMMARY, -- Used inside a BFM when showing the summary of data that has been received while waiting for expected data.
ID_TERMINATE_CMD, -- Typically used inside a loop in a procedure to end the loop (e.g. for sbi_poll_until() or any looped generation of random stimuli
-- Packet related data Ids with three levels of granularity, for differentiating between frames, packets and segments.
-- Segment Ids, finest granularity of packet data
ID_SEGMENT_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_SEGMENT_COMPLETE, -- Notify that a packet has been transmitted or received
ID_SEGMENT_HDR, -- AS ID_SEGMENT_COMPLETE, but also writes header info
ID_SEGMENT_DATA, -- AS ID_SEGMENT_COMPLETE, but also writes packet data (could be huge)
-- Packet Ids, medium granularity of packet data
ID_PACKET_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_PACKET_COMPLETE, -- Notify that a packet has been transmitted or received
ID_PACKET_HDR, -- AS ID_PACKET_COMPLETED, but also writes header info
ID_PACKET_DATA, -- AS ID_PACKET_COMPLETED, but also writes packet data (could be huge)
-- Frame Ids, roughest granularity of packet data
ID_FRAME_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_FRAME_COMPLETE, -- Notify that a packet has been transmitted or received
ID_FRAME_HDR, -- AS ID_FRAME_COMPLETE, but also writes header info
ID_FRAME_DATA, -- AS ID_FRAME_COMPLETE, but also writes packet data (could be huge)
-- OSVVM Ids
ID_COVERAGE_MAKEBIN, -- Log messages from MakeBin (IllegalBin/GenBin/IgnoreBin)
ID_COVERAGE_ADDBIN, -- Log messages from AddBin/AddCross
ID_COVERAGE_ICOVER, -- ICover logging, NB: Very low level debugging. Can result in large amount of data.
ID_COVERAGE_CONFIG, -- Logging of configuration in the coverage package
ID_COVERAGE_SUMMARY, -- Report logging : Summary of coverage, with both covered bins and holes
ID_COVERAGE_HOLES, -- Report logging : Holes only
-- Distributed command systems
ID_UVVM_SEND_CMD,
ID_UVVM_CMD_ACK,
ID_UVVM_CMD_RESULT,
ID_CMD_INTERPRETER, -- Message from VVC interpreter about correctly received and queued/issued command
ID_CMD_INTERPRETER_WAIT, -- Message from VVC interpreter that it is actively waiting for a command
ID_IMMEDIATE_CMD, -- Message from VVC interpreter that an IMMEDIATE command has been executed
ID_IMMEDIATE_CMD_WAIT, -- Message from VVC interpreter that an IMMEDIATE command is waiting for command to complete
ID_CMD_EXECUTOR, -- Message from VVC executor about correctly received command - prior to actual execution
ID_CMD_EXECUTOR_WAIT, -- Message from VVC executor that it is actively waiting for a command
ID_INSERTED_DELAY, -- Message from VVC executor that it is waiting a given delay
-- Distributed data
ID_UVVM_DATA_QUEUE, -- Information about UVVM data FIFO/stack (initialization, put, get, etc)
-- VVC system
ID_CONSTRUCTOR, -- Constructor message from VVCs (or other components/process when needed)
ID_CONSTRUCTOR_SUB, -- Constructor message for lower level constructor messages (like Queue-information and other limitations)
-- SB package
ID_DATA,
ID_CTRL,
-- Special purpose - Not really IDs
ALL_MESSAGES -- Applies to ALL message ID apart from ID_NEVER
);
type t_msg_id_panel is array (t_msg_id'left to t_msg_id'right) of t_enabled;
constant C_TB_MSG_ID_DEFAULT : t_msg_id := ID_SEQUENCER; -- msg ID used when calling the log method without any msg ID switch.
-- Default message Id panel to be used for all message Id panels, except:
-- - VVC message Id panels, see constant C_VVC_MSG_ID_PANEL_DEFAULT
constant C_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_NEVER => DISABLED,
ID_UTIL_BURIED => DISABLED,
ID_BITVIS_DEBUG => DISABLED,
ID_COVERAGE_MAKEBIN => DISABLED,
ID_COVERAGE_ADDBIN => DISABLED,
ID_COVERAGE_ICOVER => DISABLED,
others => ENABLED
);
-- If false, OSVVM uses the default message id panel. If true, it uses a separate message id panel.
constant C_USE_LOCAL_OSVVM_MSG_ID_PANELS : boolean := TRUE;
type t_msg_id_indent is array (t_msg_id'left to t_msg_id'right) of string(1 to 4);
constant C_MSG_ID_INDENT : t_msg_id_indent := (
ID_IMMEDIATE_CMD_WAIT => " ..",
ID_CMD_INTERPRETER => " " & NUL & NUL,
ID_CMD_INTERPRETER_WAIT => " ..",
ID_CMD_EXECUTOR => " " & NUL & NUL,
ID_CMD_EXECUTOR_WAIT => " ..",
ID_UVVM_SEND_CMD => "->" & NUL & NUL,
ID_UVVM_CMD_ACK => " ",
others => "" & NUL & NUL & NUL & NUL
);
constant C_MSG_DELIMITER : character := ''';
-------------------------------------------------------------------------
-- Alert counters
-------------------------------------------------------------------------
-- Default values. These can be overwritten in each sequencer by using
-- set_alert_attention or set_alert_stop_limit (see quick ref).
constant C_DEFAULT_ALERT_ATTENTION : t_alert_attention := (others => REGARD);
-- 0 = Never stop
constant C_DEFAULT_STOP_LIMIT : t_alert_counters := (note to manual_check => 0,
others => 1);
-------------------------------------------------------------------------
-- Hierarchical alerts
-------------------------------------------------------------------------
constant C_ENABLE_HIERARCHICAL_ALERTS : boolean := false;
constant C_BASE_HIERARCHY_LEVEL : string(1 to 5) := "Total";
constant C_EMPTY_NODE : t_hierarchy_node := (" ",
(others => (others => 0)),
(others => 0),
(others => true));
-------------------------------------------------------------------------
-- Deprecate
-------------------------------------------------------------------------
-- These values are used to indicate outdated sub-programs
constant C_DEPRECATE_SETTING : t_deprecate_setting := DEPRECATE_ONCE;
shared variable deprecated_subprogram_list : t_deprecate_list := (others=>(others => ' '));
------------------------------------------------------------------------
-- UVVM VVC Framework adaptations
------------------------------------------------------------------------
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT & "(uvvm)";
signal global_show_msg_for_uvvm_cmd : boolean := true;
constant C_CMD_QUEUE_COUNT_MAX : natural := 20; -- (VVC Command queue) May be overwritten for dedicated VVC
constant C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
constant C_CMD_QUEUE_COUNT_THRESHOLD : natural := 18;
constant C_RESULT_QUEUE_COUNT_MAX : natural := 20; -- (VVC Result queue) May be overwritten for dedicated VVC
constant C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
constant C_RESULT_QUEUE_COUNT_THRESHOLD : natural := 18;
constant C_MAX_VVC_INSTANCE_NUM : natural := 20;
constant C_MAX_NUM_SEQUENCERS : natural := 10; -- Max number of sequencers
-- Maximum allowed length of VVC names
constant C_MAX_VVC_NAME_LENGTH : positive := 20;
-- Minimum width of vvc name and channel displayed in scope.
-- These combined + the length of instance + 2 (commas), cannot exceed C_LOG_SCOPE_WIDTH.
constant C_MINIMUM_CHANNEL_SCOPE_WIDTH : natural := 10;
constant C_MINIMUM_VVC_NAME_SCOPE_WIDTH : natural := 10;
constant C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER : natural := 2048;
constant C_NUMBER_OF_DATA_BUFFERS : natural := 10;
-- Default message Id panel intended for use in the VVCs
constant C_VVC_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_NEVER => DISABLED,
ID_UTIL_BURIED => DISABLED,
others => ENABLED
);
type t_data_source is ( -- May add more types of random ++ later
NA,
FROM_BUFFER,
RANDOM,
RANDOM_TO_BUFFER
);
type t_error_injection is ( -- May add more controlled error injection later
NA,
RANDOM_BIT_ERROR,
RANDOM_DATA_ERROR,
RANDOM_ADDRESS_ERROR
);
constant C_CMD_IDX_PREFIX : string := " [";
constant C_CMD_IDX_SUFFIX : string := "]";
type t_channel is ( -- NOTE: Add more types of channels when needed for a VVC
NA, -- When channel is not relevant
ALL_CHANNELS, -- When command shall be received by all channels
RX,
TX);
constant C_VVCT_ALL_INSTANCES, ALL_INSTANCES : integer := -2;
constant ALL_ENABLED_INSTANCES : integer := -3;
constant C_NUM_SEMAPHORE_LOCK_TRIES : natural := 500;
------------------------------------------------------------------------
-- Scoreboard adaptations
------------------------------------------------------------------------
constant C_MAX_QUEUE_INSTANCE_NUM : positive := 100; -- Maximum number of instances
constant C_SB_TAG_WIDTH : positive := 128; -- Number of characters in SB tag
constant C_SB_SOURCE_WIDTH : positive := 128; -- Number of characters in SB source element
constant C_SB_SLV_WIDTH : positive := 8; -- Width of the SLV in the predefined SLV SB
-- Default message Id panel intended for use in SB
constant C_SB_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_CTRL => ENABLED,
ID_DATA => DISABLED,
others => DISABLED
);
end package adaptations_pkg;
package body adaptations_pkg is
end package body adaptations_pkg;

6
tb/evr320_decoder_tb.vhd
View File

@@ -68,7 +68,7 @@ architecture testbench of evr320_decoder_tb is
signal usr_clk : std_logic := '0';
signal evr_params : typ_evr320_params;
signal mem_addr : std_logic_vector(13 downto 0) := (others => '0');
signal mem_addr : std_logic_vector(11 downto 0) := (others => '0');
signal mem_data : std_logic_vector(31 downto 0) := (others => '0');
-- Decoder stream:
type dec_stream_type is record
@@ -341,7 +341,7 @@ begin
evr_params.event_numbers( 3)<= X"00";
evr_params.cs_min_cnt <= X"00000000";
evr_params.cs_min_time <= X"00000000";
mem_addr <= (others=>'0');
mem_addr <= x"000";
await_value(rxlos, '0', 0 ns, 10 us, FAILURE, "wait for release RX LOS");
--wait until (rxlos = '0');
@@ -393,7 +393,7 @@ begin
-- print 16 words from dpram data buffer:
for offset in 0 to segment_length/4-1 loop
mem_base := to_integer(unsigned(segment_addr));
mem_addr <= std_logic_vector(to_unsigned(4*mem_base + offset , 14));
mem_addr <= std_logic_vector(to_unsigned(4*mem_base + offset , 12));
wait until rising_edge(usr_clk);
wait until rising_edge(usr_clk);
wait until rising_edge(usr_clk);