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Code Issues Pull Requests Actions 1 Packages Projects Releases 38 Wiki Activity
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e4ac3e8b088af8df6fd78ccdff628d06294d571f
Jungfraujoch/fpga/scripts
History
Filip Leonarski 79df7cf7d5 FPGA: Add extra AXI-Stream register slices
2023-10-17 19:40:55 +02:00
..
bd_pcie.tcl
FPGA: integration results are reduced to cover two bins per 512-bit
2023-09-29 22:07:52 +02:00
build_pcie_design.tcl
Remove open source license (for now)
2023-09-15 10:47:21 +02:00
check_hls.sh
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
hbm_u55c.tcl
FPGA: frame generator reads from HBM (work in progress)
2023-09-26 13:14:43 +02:00
jfjoch.tcl
FPGA: Add extra AXI-Stream register slices
2023-10-17 19:40:55 +02:00
mac_100g_pcie.tcl
Remove open source license (for now)
2023-09-15 10:47:21 +02:00
network_stack.tcl
Remove open source license (for now)
2023-09-15 10:47:21 +02:00
pcie_dma.tcl
Remove open source license (for now)
2023-09-15 10:47:21 +02:00
setup_action.sh
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
synth_and_impl.tcl
Remove open source license (for now)
2023-09-15 10:47:21 +02:00
synth_hls_function.tcl
Remove open source license (for now)
2023-09-15 10:47:21 +02:00
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