leonarski_fandClaude Opus 5
46930142dd
Nothing said what is in a release or what it needs of the machine it lands on: that the Linux binaries are built -march=x86-64-v3 and the Windows ones /arch:AVX, so each has a CPU floor; that the portable .tgz is built on RHEL 8 for its glibc; that the Windows installer is MSVC (Visual Studio 2026), CUDA 13.3, Qt 6.11 and carries the Qt runtime; and above all what the CUDA variants need. Only cuFFT is linked dynamically, and it has no link-time dependency on the driver library, so a CUDA build starts on a machine with no NVIDIA GPU at all and falls back to the CPU path - as long as cuFFT can be loaded, which the .tgz and the installer arrange by shipping it and the distribution packages arrange through the distribution's own CUDA packages. Collected into a new page rather than scattered over the install instructions. The repository page had the RHEL 9 rows pointing at el8 paths under the wrong slsdet number, no rows at all for the two slsdet9 repositories the pipeline uploads, a driver package named jfjoch-driver where it is jfjoch-driver-dkms, and a note that RPMs are unsigned from before the pipeline started uploading them with sign=true. The FPGA page had a paragraph that stopped mid-sentence, in the middle of a link, and a section describing a firmware build triggered by commit message. The firmware is stable and carried from version to version now. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
82 lines
3.7 KiB
Markdown
82 lines
3.7 KiB
Markdown
# FPGA smartNIC
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See separate document for [installation instructions](DEPLOYMENT.md).
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## Hardware
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Currently supported FPGA is only **Xilinx Alveo U55C**.
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See AMD/Xilinx webpage for [card user guide (UG1469)](https://docs.xilinx.com/r/en-US/ug1469-alveo-u55c).
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According to the user guide:
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```
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Alveo data center accelerator cards are designed to be installed into a data center server, where controlled air flow provides direct cooling.
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```
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Card needs to be placed in PCI Express (PCIe) Gen4 x8 slot, though mechanically slot has to accommodate x16 card.
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There is no need to connect additional power cable, as power of the card is not exceeding 75 W load available from PCIe edge connector.
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Current power estimation is about 30 W when idle and 45 W in operation. The card has built-in protection, which will cut power to the card if HBM temperature is above 120°C.
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Two variants of the card are available:
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* `100g` - this variant operates one port in 100 Gbit/s mode and should be used when connecting detector via a switch.
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* `8x10g` - this variant operates both QSFP ports at 4x10 Gbit/s. QSFP+ (40 Gbit/s) transceivers and MTO/MTP harness cables
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are necessary. It is designed for detector directly connected to the Jungfraujoch server, without switch.
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See [network documentation](FPGA_NETWORK.md) for details of network.
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## Building firmware
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The firmware build targets are generated by CMake only when `vivado` and `vitis_hls` are detected in
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the path, and the Vivado version has to match the one below precisely.
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### Xilinx Vivado
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The following procedures require having AMD (Xilinx) Vivado and Vitis HLS toolsets version **2022.2** installed on the machine.
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Due to the nature of TCL scripts used to generate board designs Vivado version has to exactly match one provided above -
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specifically newer versions of Vivado will not work.
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In additional to Intellectual Property (IP) cores included in Vivado, two additional licenses are necessary:
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* Non-cost license for Ultrascale+ 100G core has to be requested from AMD/Xilinx website, see [Xilinx website](https://www.xilinx.com/products/intellectual-property/cmac_usplus.html), to build `100g` design.
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* Paid 10G/25G Subsystem for Ultrascale+ to build `8x10g` design.
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PSI received non-cost licenses from Xilinx University Program for the latter cores. Therefore, usage of bitstreams
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generated by PSI continuous integration pipeline for `8x10g` is only allowed for non-commercial use.
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### HLS compilation
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Make HLS routines:
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```
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mkdir build
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cd build
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cmake ..
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make hls
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```
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### Synthesis
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Create PCIe `100g` bitstream with the following command:
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```
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mkdir build
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cd build
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cmake ..
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make pcie_100g
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```
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and `8x10g`:
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```
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mkdir build
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cd build
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cmake ..
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make pcie_8x10g
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```
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### When Vivado is not present
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During CMake execution, the following executables: `vivado` and `vitis_hls` must be present in the path.
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If not, build targets will not be generated, and such or similar error message will show up:
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```
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$ make pcie_100g
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make: *** No rule to make target 'pcie_100g'. Stop.
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```
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### Firmware releases
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The firmware is stable and is carried from version to version: the MCS files attached to a release
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are normally the ones from the release before it (see [Release contents](RELEASE_CONTENTS.md)). When
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it does need to change, it is rebuilt with the targets above on a machine with Vivado.
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### Frame generator
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Jungfraujoch card is equipped with frame generator. It allows to simulate JUNGFRAU detector without having access to such system.
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It is placed in parallel to Ethernet MAC - so it is placed before the network stack and before any processing happening on the card.
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In the future a redirection will be possible to send the simulated stream through the 100G TX network link.
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Frame generator is written in HLS and controlled with AXI-Lite. |