Files
Jungfraujoch/fpga/hls/adu_histo.cpp

71 lines
2.3 KiB
C++

// Copyright (2019-2023) Paul Scherrer Institute
#include "hls_jfjoch.h"
void adu_histo(STREAM_512 &data_in,
STREAM_512 &data_out,
hls::stream<ap_uint<512>> &result_out,
hls::stream<axis_completion > &s_axis_completion,
hls::stream<axis_completion > &m_axis_completion) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE register both axis port=data_in
#pragma HLS INTERFACE register both axis port=data_out
#pragma HLS INTERFACE register both axis port=result_out
#pragma HLS INTERFACE register both axis port=m_axis_completion
#pragma HLS INTERFACE register both axis port=s_axis_completion
ap_uint<14> count[64][ADU_HISTO_BIN_COUNT]; // log2(512*1024/64) = 13
#pragma HLS BIND_STORAGE variable=count type=ram_t2p impl=bram
#pragma HLS ARRAY_PARTITION variable=count type=complete dim=1
for (int j = 0; j < ADU_HISTO_BIN_COUNT; j++) {
#pragma HLS PIPELINE II=1
for (int i = 0; i < 64; i++)
count[i][j] = 0;
}
ap_uint<16> in_val[32];
ap_uint<256> bins_0, bins_1;
packet_512_t packet_in;
data_in >> packet_in;
data_out << packet_in;
axis_completion cmpl;
s_axis_completion >> cmpl;
while (!cmpl.last) {
m_axis_completion << cmpl;
for (int i = 0; i < RAW_MODULE_SIZE / (32 * 2); i++) {
#pragma HLS PIPELINE II=2
for (int k = 0; k < 2; k++) {
data_in >> packet_in;
data_out << packet_in;
unpack32(packet_in.data, in_val);
for (int j = 0; j < 32; j++)
count[k * 32 + j][in_val[j] / ADU_HISTO_BIN_WIDTH] += (cmpl.packet_mask[i / 64] ? 1 : 0);
}
}
for (int i = 0; i < ADU_HISTO_BIN_COUNT / 16; i++) {
#pragma HLS PIPELINE II=1
ap_uint<512> val = 0;
for (int k = 0; k < 16; k++) {
ap_uint<32> tmp = 0;
for (int j = 0; j < 64; j++) {
tmp += count[j][i * 16 + k];
count[j][i * 16 + k] = 0;
}
val(k * 32 + 31, k * 32) = tmp;
}
result_out << val;
}
s_axis_completion >> cmpl;
}
m_axis_completion << cmpl;
data_in >> packet_in;
data_out << packet_in;
}