110 lines
3.3 KiB
C++
110 lines
3.3 KiB
C++
// Copyright (2019-2023) Paul Scherrer Institute
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#include <iostream>
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#include <catch2/catch.hpp>
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#include "../fpga/hls/hls_jfjoch.h"
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#include "../fpga/hls/spot_finder.h"
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TEST_CASE("Pack32_Unpack32","[FPGA][SpotFinder]") {
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ap_int<16> value[32];
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for (int i = 0; i < 32; i++)
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value[i] = i;
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ap_int<512> packed = pack32(value);
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ap_int<16> restore[32];
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unpack32(packed, restore);
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for (int i = 0; i < 32; i++) {
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REQUIRE(value[i] == restore[i]);
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}
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}
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TEST_CASE("Pack32_Unpack32_36","[FPGA][SpotFinder]") {
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ap_int<36> value[32];
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for (int i = 0; i < 32; i++)
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value[i] = i;
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ap_int<36*32> packed = pack32(value);
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ap_int<36> restore[32];
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unpack32(packed, restore);
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for (int i = 0; i < 32; i++) {
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REQUIRE(value[i] == restore[i]);
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}
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}
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TEST_CASE("FPGA_calc_sum","[FPGA][SpotFinder]") {
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ap_int<16> old_value[32];
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ap_int<16> new_value[32];
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ap_int<SUM_BITWIDTH> new_sum[32];
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ap_int<SUM2_BITWIDTH> new_sum2[32];
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for (int i = 0; i < 32; i++) {
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old_value[i] = i;
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new_value[i] = 2;
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}
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ap_uint<SUM_BITWIDTH*32> diff_sum;
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ap_uint<SUM2_BITWIDTH*32> diff_sum2;
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calc_sum(diff_sum, pack32(old_value), pack32(new_value));
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calc_sum2(diff_sum2, pack32(old_value), pack32(new_value));
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unpack32(diff_sum, new_sum);
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unpack32(diff_sum2, new_sum2);
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for (int i = 0; i < 32; i++) {
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REQUIRE(new_sum[i] == 2-i);
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REQUIRE(new_sum2[i] == 4-i*i);
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}
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}
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TEST_CASE("FPGA_update_sum" , "[FPGA][SpotFinder]") {
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ap_int<SUM2_BITWIDTH> arr_val1[32], arr_val2[32], arr_out[32];
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for (int i = 0; i < 32; i++) {
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arr_val1[i] = 5 * i;
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arr_val2[i] = 3 * i + 2;
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}
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ap_uint<SUM2_BITWIDTH*32> val1 = pack32(arr_val1);
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ap_uint<SUM2_BITWIDTH*32> val2 = pack32(arr_val2);
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update_sum<SUM2_BITWIDTH>(val1, val2);
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unpack32(val1, arr_out);
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for (int i = 0; i < 32; i++)
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REQUIRE(arr_out[i] == 8 * i + 2);
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}
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bool Isigma_cpu(double val, double sum, double sum2, float threshold) {
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double mean = sum / ((2*FPGA_NBX+1) * (2*FPGA_NBX+1));
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double mean2 = sum2 / ((2*FPGA_NBX+1) * (2*FPGA_NBX+1));
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double variance = mean2 - mean * mean;
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double sigma = sqrt(variance);
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double i_over_sigma = (val - mean) / sigma;
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return (i_over_sigma > threshold);
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}
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bool Isigma_fpga(ap_int<16> val, ap_int<SUM_BITWIDTH> sum, ap_uint<SUM2_BITWIDTH> sum2, float threshold) {
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return check_threshold(val, sum, sum2, fpga_strong_pixel_threshold(threshold), -1);
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}
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TEST_CASE("FPGA_spot_check_threshold","[FPGA][SpotFinder]") {
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std::vector<float> threshold_values = {1.0, 3.0, 6.0};
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for (auto threshold: threshold_values) {
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uint32_t uniform_val = 10;
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uint32_t diff = 0;
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for (int16_t val = -100; val < INT16_MAX; val++) {
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uint32_t sum = val + ((2 * FPGA_NBX + 1) * (2 * FPGA_NBX + 1) - 1) * uniform_val;
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uint32_t sum2 = val * val + ((2 * FPGA_NBX + 1) * (2 * FPGA_NBX + 1) - 1) * uniform_val * uniform_val;
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bool cpu = Isigma_cpu(val, sum, sum2, threshold);
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bool fpga = Isigma_fpga(val, sum, sum2, threshold);
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if (cpu != fpga) {
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std::cout << "WRONG!!! " << threshold << " " << val << " " << sum << " " << sum2 << " CPU: " << cpu << " FPGA: " << fpga << std::endl;
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diff++;
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}
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}
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REQUIRE(diff == 0);
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}
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}
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