Filip Leonarski 001a7d86fc FPGA: For totally unknown reason making UDP metadata stream narrower results in timing not met

2023-04-17 08:02:24 +02:00

..

arp.cpp

Initial commit

2023-04-06 11:17:59 +02:00

CMakeLists.txt

Initial commit

2023-04-06 11:17:59 +02:00

data_collection_fsm.cpp

Initial commit

2023-04-06 11:17:59 +02:00

ethernet.cpp

Initial commit

2023-04-06 11:17:59 +02:00

hls_jfjoch.h

FPGA: For totally unknown reason making UDP metadata stream narrower results in timing not met

2023-04-17 08:02:24 +02:00

host_writer.cpp

Initial commit

2023-04-06 11:17:59 +02:00

icmp.cpp

Initial commit

2023-04-06 11:17:59 +02:00

internal_packet_generator.cpp

Initial commit

2023-04-06 11:17:59 +02:00

ip_header_checksum.h

Initial commit

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ipv4.cpp

Initial commit

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jf_conversion.cpp

Initial commit

2023-04-06 11:17:59 +02:00

load_calibration.cpp

Initial commit

2023-04-06 11:17:59 +02:00

sls_detector.cpp

FPGA + receiver + detector: Use column ID to decode detector half-module number

2023-04-15 11:08:32 +02:00

timer.cpp

Initial commit

2023-04-06 11:17:59 +02:00

udp.cpp

FPGA: Minor clean-up of UDP processing

2023-04-15 19:33:34 +02:00