222 lines
7.4 KiB
C++
222 lines
7.4 KiB
C++
// Copyright (2019-2024) Paul Scherrer Institute
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#include <catch2/catch_all.hpp>
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#include <random>
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#include "../fpga/hls_simulation/hls_cores.h"
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TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
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DataCollectionConfig act_reg;
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STREAM_512 raw0;
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STREAM_512 raw1;
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hls::stream<axis_addr> addr0;
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hls::stream<axis_addr> addr1;
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ap_uint<1> run_data_collection = 0;
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ap_uint<1> cancel_data_collection = 0;
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ap_uint<1> idle_data_collection;
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uint32_t save_data_collection_counter;
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act_reg.mode = MODE_CONV;
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// state = WAIT_FOR_START
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volatile rcv_state_t state;
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data_collection_fsm(raw0, raw1,
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addr0, addr1,
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run_data_collection,
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cancel_data_collection,
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idle_data_collection,
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act_reg.mode,
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act_reg.energy_kev,
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act_reg.nframes,
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act_reg.nmodules,
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act_reg.nstorage_cells,
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act_reg.nsummation,
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act_reg.sqrtmult,
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act_reg.pxlthreshold,
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state);
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REQUIRE(idle_data_collection == 1);
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REQUIRE(addr1.empty());
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REQUIRE(raw1.empty());
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REQUIRE( state == RCV_WAIT_FOR_START);
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run_data_collection = 1;
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// state = WAIT_FOR_START
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data_collection_fsm(raw0, raw1,
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addr0, addr1,
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run_data_collection,
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cancel_data_collection,
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idle_data_collection,
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act_reg.mode,
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act_reg.energy_kev,
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act_reg.nframes,
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act_reg.nmodules,
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act_reg.nstorage_cells,
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act_reg.nsummation,
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act_reg.sqrtmult,
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act_reg.pxlthreshold,
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state);
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REQUIRE(idle_data_collection == 0);
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REQUIRE(addr1.empty());
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REQUIRE(raw1.empty());
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REQUIRE( state == RCV_WAIT_FOR_START_LOW);
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// state = WAIT_FOR_START_LOW
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data_collection_fsm(raw0, raw1,
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addr0, addr1,
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run_data_collection,
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cancel_data_collection,
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idle_data_collection,
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act_reg.mode,
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act_reg.energy_kev,
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act_reg.nframes,
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act_reg.nmodules,
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act_reg.nstorage_cells,
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act_reg.nsummation,
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act_reg.sqrtmult,
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act_reg.pxlthreshold,
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state);
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REQUIRE(idle_data_collection == 0);
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REQUIRE(addr1.empty());
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REQUIRE(raw1.empty());
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REQUIRE( state == RCV_WAIT_FOR_START_LOW);
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// state = WAIT_FOR_START_LOW
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run_data_collection = 0;
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data_collection_fsm(raw0, raw1,
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addr0, addr1,
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run_data_collection,
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cancel_data_collection,
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idle_data_collection,
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act_reg.mode,
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act_reg.energy_kev,
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act_reg.nframes,
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act_reg.nmodules,
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act_reg.nstorage_cells,
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act_reg.nsummation,
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act_reg.sqrtmult,
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act_reg.pxlthreshold,
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state);
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REQUIRE(idle_data_collection == 0);
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REQUIRE(addr1.empty());
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REQUIRE(raw1.empty());
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REQUIRE( state == RCV_START);
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// state = START
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data_collection_fsm(raw0, raw1,
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addr0, addr1,
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run_data_collection,
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cancel_data_collection,
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idle_data_collection,
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act_reg.mode,
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act_reg.energy_kev,
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act_reg.nframes,
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act_reg.nmodules,
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act_reg.nstorage_cells,
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act_reg.nsummation,
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act_reg.sqrtmult,
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act_reg.pxlthreshold,
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state);
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REQUIRE(idle_data_collection == 0);
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REQUIRE(raw1.size() == 1);
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REQUIRE( state == RCV_INIT);
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// state = INIT
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data_collection_fsm(raw0, raw1,
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addr0, addr1,
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run_data_collection,
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cancel_data_collection,
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idle_data_collection,
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act_reg.mode,
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act_reg.energy_kev,
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act_reg.nframes,
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act_reg.nmodules,
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act_reg.nstorage_cells,
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act_reg.nsummation,
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act_reg.sqrtmult,
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act_reg.pxlthreshold,
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state);
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REQUIRE(idle_data_collection == 0);
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REQUIRE(raw1.size() == 1);
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REQUIRE( state == RCV_INIT);
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// state = INIT
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cancel_data_collection = 1;
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data_collection_fsm(raw0, raw1,
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addr0, addr1,
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run_data_collection,
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cancel_data_collection,
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idle_data_collection,
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act_reg.mode,
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act_reg.energy_kev,
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act_reg.nframes,
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act_reg.nmodules,
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act_reg.nstorage_cells,
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act_reg.nsummation,
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act_reg.sqrtmult,
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act_reg.pxlthreshold,
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state);
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REQUIRE(idle_data_collection == 0);
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REQUIRE(raw1.size() == 1);
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// state = LAST
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REQUIRE( state == RCV_LAST);
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data_collection_fsm(raw0, raw1,
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addr0, addr1,
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run_data_collection,
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cancel_data_collection,
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idle_data_collection,
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act_reg.mode,
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act_reg.energy_kev,
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act_reg.nframes,
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act_reg.nmodules,
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act_reg.nstorage_cells,
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act_reg.nsummation,
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act_reg.sqrtmult,
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act_reg.pxlthreshold,
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state);
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REQUIRE(idle_data_collection == 0);
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REQUIRE(addr1.size() == 1);
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REQUIRE(raw1.size() == 2);
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REQUIRE( state == RCV_WAIT_FOR_START);
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// state = WAIT_FOR_START
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data_collection_fsm(raw0, raw1,
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addr0, addr1,
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run_data_collection,
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cancel_data_collection,
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idle_data_collection,
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act_reg.mode,
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act_reg.energy_kev,
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act_reg.nframes,
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act_reg.nmodules,
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act_reg.nstorage_cells,
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act_reg.nsummation,
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act_reg.sqrtmult,
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act_reg.pxlthreshold,
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state);
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REQUIRE( state == RCV_WAIT_FOR_START);
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REQUIRE(idle_data_collection == 1);
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REQUIRE(addr1.size() == 1);
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REQUIRE(raw1.size() == 2);
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auto packet = raw1.read();
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REQUIRE(packet.last == 1);
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REQUIRE(packet.dest == 0);
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packet = raw1.read();
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REQUIRE(packet.last);
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REQUIRE(packet.dest == 0);
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auto addr = addr1.read();
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REQUIRE(addr.last);
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}
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