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mx/Jungfraujoch
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Code Issues Pull Requests Actions 2 Packages Projects Releases 67 Wiki Activity
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9178bbd689edcbfdfc7d016d93faa4399b62bd5c
Jungfraujoch/receiver/hls
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History
leonarski_f 8ac012ae99 FPGA: Use upper 16-bits of mode as data_collection_id
2023-05-31 11:38:17 +02:00
..
arp.cpp
Initial commit
2023-04-06 11:17:59 +02:00
CMakeLists.txt
Initial commit
2023-04-06 11:17:59 +02:00
data_collection_fsm.cpp
FPGA: Remove data collection counter
2023-05-30 20:13:54 +02:00
ethernet.cpp
Initial commit
2023-04-06 11:17:59 +02:00
hls_jfjoch.h
FPGA: Minor improvements to internal_packet_generator - should now better break in case of cancellation
2023-05-31 11:08:28 +02:00
host_writer.cpp
FPGA: Use upper 16-bits of mode as data_collection_id
2023-05-31 11:38:17 +02:00
icmp.cpp
Initial commit
2023-04-06 11:17:59 +02:00
internal_packet_generator.cpp
FPGA: Minor improvements to internal_packet_generator - should now better break in case of cancellation
2023-05-31 11:08:28 +02:00
ip_header_checksum.h
Initial commit
2023-04-06 11:17:59 +02:00
ipv4.cpp
Initial commit
2023-04-06 11:17:59 +02:00
jf_conversion.cpp
Initial commit
2023-04-06 11:17:59 +02:00
load_calibration.cpp
Initial commit
2023-04-06 11:17:59 +02:00
sls_detector.cpp
FPGA: Save full JF timestamp and exptime
2023-05-17 21:30:42 +02:00
timer.cpp
Initial commit
2023-04-06 11:17:59 +02:00
udp.cpp
FPGA: Minor clean-up of UDP processing
2023-04-15 19:33:34 +02:00
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