leonarski_fandClaude Fable 5
70c4d871b6
- Capitalize Rugnux as a proper noun throughout the prose; the command stays lowercase `rugnux` in code font. RUGNUX_OVERVIEW.md is retitled "What Rugnux does". - ACKNOWLEDGEMENT.md cites the raw-data repositories only: dataset counts and DOI prefixes moved out (EXTERNAL_TEST_DATA.md owns them), the ESRF data portal gains its citation (Dimper et al. 2019), and MXRDR remains name + link - it has no canonical citation paper. - RUGNUX_FORMATS.md: the CCD formats (marCCD, SMV) are supported as-is with very limited scope, and per-panel XFEL data is not read. - Fix wrong facts a reader would act on: nonexistent `make jfjoch` targets, invalid udev rules, PUSH sockets documented as PULL, swapped writer width/height, underload semantics, the transposed pixel-mask numpy example (the server checks width and height separately), the Durin/Neggia mask-bit table, FPGA threshold register addresses and the mailbox bit field, the I2C core's document number (PG090), an inverted MODEL_FIT_SIGMA formula, a self-inconsistent worked report example, and 11 cross-page anchors whose slugs carry MyST section numbers. - Unify CC1/2 spelling in prose; math notation and report keys unchanged. - Sweep grammar, typos and editing residue across the FPGA, deployment, streaming and analysis pages, including historical CHANGELOG typos. - rugnux_cli.cpp: the -S usage/error examples pair 96 with P43212; 92 names a different group. - Root THIRD_PARTY_NOTICES.md: scope the GPL-compatibility claim (CUDA EULA) and the vendored-table intro (traccc); the docs copy regenerates via update_version.sh. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
22 lines
1.1 KiB
Markdown
22 lines
1.1 KiB
Markdown
# FPGA data flow
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The following steps are performed on FPGA (in the order of operation):
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1. UDP header decoding
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2. SLS detector header decoding
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3. State machine that controls data acquisition (start/stop/cancel)
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4. High-bandwidth memory cache to buffer network packets and reorder them to form full modules
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5. ADU histogram for JUNGFRAU
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6. Mask pixels from missing packets with special value
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7. Reorder lines for EIGER to form a proper module
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8. Mask pixels based on provided pixel mask
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9. JUNGFRAU conversion with gain and pedestal corrections
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10. Threshold: pixel values below a set minimum are zeroed, values above a set maximum saturated
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11. Frame summation (up to 256 frames)
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12. Integration according to predefined map (e.g., 1D azimuthal integration)
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13. Spot finding
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14. ROI calculation
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15. Image lossy compression using N*sqrt(pixel) values
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16. Send images, analysis results and metadata to host memory via PCI Express
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Each step has a dedicated core, written in high-level synthesis. Exact operation of cores for data analysis is explained in dedicated [document](FPGA_DATA_ANALYSIS.md). |