The profile is the MEAN of each bin, so a few strong reflections landing in a bin lift it exactly as a smooth powder ring does. That is the wrong quantity whenever the profile is wanted as a background rather than as a measurement of what is in the bin - the ice score being the case in point, where reading a plain profile INVERTED the metric: over 37 rotation crystals the two highest-scoring crystals had no ice at all. The adaptive spot finder already computes the right thing, a sigma-clipped per-resolution-ring background, as a byproduct of its own threshold. Where it runs, the ice score uses that. Where it does not - --no-adaptive-spots, --azint-only, and anything reading the profile the broker wrote - there was no way to get it. This adds one: azim_int_settings.sigma_clip (rugnux --azim-sigma-clip), 0 = off, minimum 2 because a tighter clip rejects a large part of a clean Gaussian bin and biases the estimate low rather than removing outliers. Two clip passes follow the plain one, matching the finder's recipe - the first pass's standard deviation is itself inflated by the peaks being removed, so one pass leaves a threshold that is still too generous. A bin with fewer than eight pixels is left alone: at the detector edge and behind the beam stop there is no spread to clip on. Both engines do it. On the GPU the accept range is computed by a small kernel and stays resident, so a clip pass is one more read of the same pixels and no round trip; the two accumulation kernels take the range as a pointer that is null on the plain pass. Measured on a JUNGFRAU rotation dataset, non-adaptive path: azimuthal integration 0.02 -> 0.06 ms per image, exactly the 3x the extra passes predict, against a 0.34 ms per-image total. Note what the result IS: the smooth background under the peaks, not the bin mean. It should not be switched on where a ring's integrated intensity is wanted - the powder-ring geometry fit reads ring peaks, and those are what a clip is designed to remove. Off by default, so nothing changes unless it is asked for. Not exposed over the REST API - that needs the generated model regenerated, which is a separate step. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
197 lines
7.7 KiB
Plaintext
197 lines
7.7 KiB
Plaintext
// SPDX-FileCopyrightText: 2025 Filip Leonarski, Paul Scherrer Institute <filip.leonarski@psi.ch>
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// SPDX-License-Identifier: GPL-3.0-only
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#include "AzIntEngineGPU.h"
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inline void cuda_err(cudaError_t val) {
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if (val != cudaSuccess)
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throw JFJochException(JFJochExceptionCategory::GPUCUDAError, cudaGetErrorString(val));
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}
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__global__
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void gpu_azim_shared(
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const uint16_t *__restrict__ pixel_to_bin,
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const float *__restrict__ corrections,
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const int32_t *__restrict__ input_buffer,
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float *__restrict__ azint_sum,
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float *__restrict__ azint_sum2,
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uint32_t *__restrict__ azint_count,
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const float *__restrict__ clip_lo,
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const float *__restrict__ clip_hi,
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size_t num_pixels,
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int azint_bins) {
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extern __shared__ float shared[];
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float *s_sum = shared;
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float *s_sum2 = &s_sum[azint_bins];
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uint32_t *s_count = (uint32_t *) &s_sum2[azint_bins];
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// Initialize shared memory
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for (int i = threadIdx.x; i < azint_bins; i += blockDim.x) {
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s_sum[i] = 0.0f;
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s_sum2[i] = 0.0f;
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s_count[i] = 0;
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}
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__syncthreads();
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for (size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
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idx < num_pixels;
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idx += blockDim.x * gridDim.x) {
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uint16_t bin = pixel_to_bin[idx];
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int32_t v = input_buffer[idx];
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bool valid = (v != INT32_MIN) & (v != INT32_MAX);
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if (bin < azint_bins && valid) {
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const float val = static_cast<float>(v) * corrections[idx];
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// clip_lo is null on the plain pass; on a clip pass it is the previous pass's
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// mean +- n sigma for this bin.
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if (clip_lo == nullptr || (val >= clip_lo[bin] && val <= clip_hi[bin])) {
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const float val2 = val * val;
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atomicAdd(&s_sum[bin], val);
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atomicAdd(&s_sum2[bin], val2);
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atomicAdd(&s_count[bin], 1);
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}
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}
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}
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__syncthreads();
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// Merge to global memory
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for (unsigned int i = threadIdx.x; i < azint_bins; i += blockDim.x) {
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atomicAdd(&azint_sum[i], s_sum[i]);
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atomicAdd(&azint_sum2[i], s_sum2[i]);
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atomicAdd(&azint_count[i], s_count[i]);
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}
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}
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__global__
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void gpu_azim(
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const uint16_t *__restrict__ pixel_to_bin,
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const float *__restrict__ corrections,
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const int32_t *__restrict__ input_buffer,
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float *__restrict__ azint_sum,
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float *__restrict__ azint_sum2,
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uint32_t *__restrict__ azint_count,
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const float *__restrict__ clip_lo,
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const float *__restrict__ clip_hi,
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size_t num_pixels,
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int azint_bins) {
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for (size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
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idx < num_pixels;
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idx += blockDim.x * gridDim.x) {
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uint16_t bin = pixel_to_bin[idx];
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int32_t v = input_buffer[idx];
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bool valid = (v != INT32_MIN) & (v != INT32_MAX);
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if (bin < azint_bins && valid) {
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const float val = static_cast<float>(v) * corrections[idx];
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if (clip_lo == nullptr || (val >= clip_lo[bin] && val <= clip_hi[bin])) {
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const float val2 = val * val;
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atomicAdd(&azint_sum[bin], val);
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atomicAdd(&azint_sum2[bin], val2);
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atomicAdd(&azint_count[bin], 1);
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}
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}
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}
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}
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AzIntEngineGPU::AzIntEngineGPU(const AzimuthalIntegrationMapping &integration, std::shared_ptr<CudaStream> stream)
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: AzIntEngine(integration),
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stream(stream),
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gpu_sum(azint_bins),
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gpu_sum2(azint_bins),
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gpu_count(azint_bins),
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gpu_clip_lo(clip_nsigma > 0.0f ? azint_bins : 0),
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gpu_clip_hi(clip_nsigma > 0.0f ? azint_bins : 0),
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cpu_sum_reg(azint_sum),
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cpu_sum2_reg(azint_sum2),
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cpu_count_reg(azint_count) {
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int device = 0;
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cuda_err(cudaGetDevice(&device)); // this worker's GPU, not necessarily 0
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cudaDeviceProp prop{};
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cuda_err(cudaGetDeviceProperties(&prop, device));
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threads = 128;
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blocks = 4 * prop.multiProcessorCount;
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shared_size = prop.sharedMemPerBlock;
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shared_needed = azint_bins * (2 * sizeof(float) + sizeof(uint32_t));
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// Geometry-only, so shared per GPU: the first engine on this device uploads them, the rest reuse
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// them. Keyed by the mapping's own vectors, which outlive every engine built from it.
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gpu_azint_correction = SharedDeviceTable(integration.Corrections().data(), npixel,
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integration.Corrections().data(), *stream);
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gpu_pixel_to_bin = SharedDeviceTable(integration.GetPixelToBin().data(), npixel,
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integration.GetPixelToBin().data(), *stream);
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}
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// Per-bin accept range from the accumulators of the pass just finished; mirrors
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// AzIntEngine::UpdateClipLimits, kept on the device so a clip pass costs no round trip.
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__global__
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void gpu_azim_clip_limits(
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const float *__restrict__ azint_sum,
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const float *__restrict__ azint_sum2,
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const uint32_t *__restrict__ azint_count,
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float *__restrict__ clip_lo,
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float *__restrict__ clip_hi,
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int azint_bins,
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float nsigma) {
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for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < azint_bins; i += blockDim.x * gridDim.x) {
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const uint32_t n = azint_count[i];
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if (n < 8) {
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clip_lo[i] = -INFINITY;
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clip_hi[i] = INFINITY;
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continue;
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}
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const double dn = n;
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const double mean = azint_sum[i] / dn;
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const double sd = sqrt(fmax(0.0, azint_sum2[i] / dn - mean * mean));
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clip_lo[i] = static_cast<float>(mean - nsigma * sd);
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clip_hi[i] = static_cast<float>(mean + nsigma * sd);
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}
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}
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void AzIntEngineGPU::Run(const ImagePreprocessorBuffer &image, AzimuthalIntegrationProfile &profile) {
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if (image.size() != integration.GetPixelToBin().size())
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throw std::runtime_error("ImageSpotFinder::AzimIntegration: Mismatch in size");
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// Pass 0 accumulates every valid pixel; each later pass repeats it with the accept range the pass
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// before measured, so only the last pass's accumulators reach the profile. The limits stay on the
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// device between passes - a clip pass is one more read of the same pixels and nothing else.
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const int passes = PassCount();
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for (int pass = 0; pass < passes; ++pass) {
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if (pass > 0)
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gpu_azim_clip_limits<<<blocks, threads, 0, *stream>>>(
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gpu_sum, gpu_sum2, gpu_count, gpu_clip_lo, gpu_clip_hi, azint_bins, clip_nsigma);
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const float *lo = pass > 0 ? gpu_clip_lo.get() : nullptr;
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const float *hi = pass > 0 ? gpu_clip_hi.get() : nullptr;
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cuda_err(cudaMemsetAsync(gpu_sum, 0, sizeof(float) * azint_bins, *stream));
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cuda_err(cudaMemsetAsync(gpu_sum2, 0, sizeof(float) * azint_bins, *stream));
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cuda_err(cudaMemsetAsync(gpu_count, 0, sizeof(uint32_t) * azint_bins, *stream));
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if (shared_needed < shared_size) {
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gpu_azim_shared<<<blocks, threads, shared_needed, *stream>>>(
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gpu_pixel_to_bin->get(),gpu_azint_correction->get(),image.getGPUBuffer(), gpu_sum, gpu_sum2,
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gpu_count, lo, hi, npixel, azint_bins
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);
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} else {
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gpu_azim<<<blocks, threads, 0, *stream>>>(
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gpu_pixel_to_bin->get(),gpu_azint_correction->get(),image.getGPUBuffer(), gpu_sum, gpu_sum2,
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gpu_count, lo, hi, npixel, azint_bins
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);
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}
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}
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cudaMemcpyAsync(azint_sum.data(), gpu_sum, sizeof(float) * azint_bins, cudaMemcpyDeviceToHost, *stream);
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cudaMemcpyAsync(azint_sum2.data(), gpu_sum2, sizeof(float) * azint_bins, cudaMemcpyDeviceToHost, *stream);
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cudaMemcpyAsync(azint_count.data(), gpu_count, sizeof(uint32_t) * azint_bins, cudaMemcpyDeviceToHost, *stream);
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cuda_err(cudaStreamSynchronize(*stream));
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profile.Clear(integration);
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profile.Add(azint_sum, azint_sum2, azint_count);
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}
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