Files
leonarski_fandClaude Opus 5 b8fa8e67d5 docs: the pages catch up with the last day on rc166
An audit of docs/ against the code at HEAD, concentrating on what landed after
the previous documentation audit: the balanced half-set split and CCanom, the
declared-range completeness denominator, the one rule for a quantity nobody
measured, and the PONI the calibration now refuses to write.

Five statements the code had made false:

- The rotation merge's CCref column shows a dash, not "nan".
- Two pages still promised unweighted 2Fo-Fc / Fo-Fc maps; they have been
  sigma_A-weighted since the rigid-body work, and one of the two sat six lines
  from a paragraph that said so.
- Inserting the CCanom prose into the SigAno paragraph left the sentence about
  the PDBx items and the SigAno column with CCanom as its subject, so it read as
  a claim about a quantity that is in neither. CCanom is also rotation-only and
  is not in the mmCIF, which nothing said.
- Two cross-references did not resolve - a heading that was renumbered, and a
  slug spelled without the hyphen MyST puts in "TCP/IP".

Added where the behaviour is new and a user meets it: the report's contract for
a quantity a run did not measure - no key, and a dash in the table, which is not
the same claim as a measured zero; the half-set rule behind CC1/2, which is why
a CUDA and a non-CUDA build now agree on it and on CCanom; and the second reason
a calibration writes no .poni, a detector whose stored image is mirrored or
quarter-turned, which the PONI format cannot state.

The rc.166 changelog stays a release note. One entry is widened from the shell
table to the rule it is a case of, and two are added for output that was wrong
rather than merely undocumented: FITTED_RESOLUTION was the P1 cross-check's, and
the unmerged MTZ carried the reference setting where the merged file carried the
adopted one.

Sphinx builds clean with -W on the pinned docs/requirements.txt, and every
intra-doc anchor resolves against the generated HTML.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01EFEJG6WBQv8th4UJFNe53N
2026-09-02 17:44:20 +02:00

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3.0 KiB
Markdown

# Tools
Besides the main services ([`jfjoch_broker`](JFJOCH_BROKER.md),
[`jfjoch_writer`](JFJOCH_WRITER.md), [`jfjoch_viewer`](JFJOCH_VIEWER.md)), the repository ships a
number of command-line tools. Each prints its own usage when run with `-h` or without arguments.
## Data analysis
### rugnux
Offline CLI tool that runs the full crystallographic analysis pipeline (spot finding, indexing,
integration, scaling/merging) on a stored HDF5 dataset, producing a `_process.h5` file and, when
merging, reflection files. Merging is on by default (`--no-merge` disables it). `--mode` picks what a
run does: `mx` (the above, the default), `azint` (only azimuthal integration, no spot
finding/indexing), `scale` (re-scale/merge the already-integrated reflections in a `_process.h5`
without re-integrating) or `calibration` (detector geometry from a calibrant's powder rings, written
as `<prefix>.poni` and `<prefix>.json`). See [rugnux](RUGNUX.md).
`rugnux` installs on its own, as the `rugnux` package or as a standalone archive — see
[Installing rugnux](RUGNUX_INSTALL.md).
### jfjoch_extract_hkl
Extracts reflections (HKL list) from a Jungfraujoch master file; can sum the same HKL across
neighbouring images and compare against an XDS `INTEGRATE.HKL` reference. A developer utility: it is
built from source but, like `jfjoch_recompress`, is not installed into any package.
## FPGA / PCIe card management
### jfjoch_pcie_status
Prints detailed status information about the card. Safe to run during data collection:
```
./jfjoch_pcie_status /dev/jfjoch0
```
### jfjoch_pcie_net_cfg
Reads and modifies the network configuration of the card's interfaces:
```
jfjoch_pcie_net_cfg <device name>
Read configuration for all network interfaces of a device
jfjoch_pcie_net_cfg <device name> <if number>|fgen
Read configuration for a particular network interface / internal frame generator
jfjoch_pcie_net_cfg <device name> <if number>|fgen ipv4 <IPv4 address>
Set IPv4 address for a particular network interface / internal frame generator
jfjoch_pcie_net_cfg <device name> <if number>|fgen direct 0|1
Set direct mode for a particular network interface / internal frame generator
jfjoch_pcie_net_cfg <device name> <if number>|fgen clear
Clear Ethernet counters for a particular network interface / internal frame generator
```
### jfjoch_pcie_clear_net_counters
Resets the card's Ethernet, UDP and ICMP packet counters (which otherwise run from power-on):
```
./jfjoch_pcie_clear_net_counters /dev/jfjoch0
```
## Testing, benchmarking and simulation
### jfjoch_udp_simulator
UDP packet simulator used to test the Jungfraujoch FPGA receiver.
### jfjoch_fpga_test
Exercises and benchmarks the FPGA data path and receiver. With `-H` it runs the high-level
synthesis C model on the CPU, so no FPGA device is required.
### jfjoch_lite_perf_test
Performance test of the lite (CPU/GPU) analysis path — indexing, integration and optional file
writing.
### jfjoch_hdf5_test
Tests single-threaded HDF5 writer performance.
### jfjoch_simplon_test
Minimal test client for a DECTRIS SIMPLON detector API.