leonarski_fandClaude Fable 5
70c4d871b6
- Capitalize Rugnux as a proper noun throughout the prose; the command stays lowercase `rugnux` in code font. RUGNUX_OVERVIEW.md is retitled "What Rugnux does". - ACKNOWLEDGEMENT.md cites the raw-data repositories only: dataset counts and DOI prefixes moved out (EXTERNAL_TEST_DATA.md owns them), the ESRF data portal gains its citation (Dimper et al. 2019), and MXRDR remains name + link - it has no canonical citation paper. - RUGNUX_FORMATS.md: the CCD formats (marCCD, SMV) are supported as-is with very limited scope, and per-panel XFEL data is not read. - Fix wrong facts a reader would act on: nonexistent `make jfjoch` targets, invalid udev rules, PUSH sockets documented as PULL, swapped writer width/height, underload semantics, the transposed pixel-mask numpy example (the server checks width and height separately), the Durin/Neggia mask-bit table, FPGA threshold register addresses and the mailbox bit field, the I2C core's document number (PG090), an inverted MODEL_FIT_SIGMA formula, a self-inconsistent worked report example, and 11 cross-page anchors whose slugs carry MyST section numbers. - Unify CC1/2 spelling in prose; math notation and report keys unchanged. - Sweep grammar, typos and editing residue across the FPGA, deployment, streaming and analysis pages, including historical CHANGELOG typos. - rugnux_cli.cpp: the -S usage/error examples pair 96 with P43212; 92 names a different group. - Root THIRD_PARTY_NOTICES.md: scope the GPL-compatibility claim (CUDA EULA) and the vendored-table intro (traccc); the docs copy regenerates via update_version.sh. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
83 lines
3.8 KiB
Markdown
83 lines
3.8 KiB
Markdown
# FPGA smartNIC
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See separate document for [installation instructions](DEPLOYMENT.md).
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## Hardware
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Currently supported FPGA is only **Xilinx Alveo U55C**.
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See AMD/Xilinx webpage for [card user guide (UG1469)](https://docs.xilinx.com/r/en-US/ug1469-alveo-u55c).
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According to the user guide:
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```
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Alveo data center accelerator cards are designed to be installed into a data center server, where controlled air flow provides direct cooling.
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```
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The card needs to be placed in a PCI Express (PCIe) Gen4 x8 slot, though mechanically slot has to accommodate x16 card.
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There is no need to connect additional power cable, as power of the card is not exceeding 75 W load available from PCIe edge connector.
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Current power estimation is about 30 W when idle and 45 W in operation. The card has built-in protection, which will cut power to the card if HBM temperature is above 120°C.
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Two variants of the card are available:
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* `100g` - this variant operates one port in 100 Gbit/s mode and should be used when connecting detector via a switch.
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* `8x10g` - this variant operates both QSFP ports at 4x10 Gbit/s. QSFP+ (40 Gbit/s) transceivers and MTO/MTP harness cables
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are necessary. It is designed for detector directly connected to the Jungfraujoch server, without switch.
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See [network documentation](FPGA_NETWORK.md) for details of network.
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## Building firmware
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The firmware build targets are generated by CMake only when `vivado` and `vitis_hls` are detected in
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the path, and the Vivado version has to match the one below precisely.
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### Xilinx Vivado
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The following procedures require having AMD (Xilinx) Vivado and Vitis HLS toolsets version **2022.2** installed on the machine.
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Due to the nature of TCL scripts used to generate board designs Vivado version has to exactly match one provided above -
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specifically newer versions of Vivado will not work.
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In addition to the Intellectual Property (IP) cores included in Vivado, two additional licenses are necessary:
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* Non-cost license for Ultrascale+ 100G core has to be requested from AMD/Xilinx website, see [Xilinx website](https://www.xilinx.com/products/intellectual-property/cmac_usplus.html), to build `100g` design.
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* A paid license for the 10G/25G Ethernet Subsystem for Ultrascale+ is necessary to build the `8x10g` design.
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PSI received non-cost licenses from Xilinx University Program for the latter cores. Therefore, usage of bitstreams
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generated by PSI continuous integration pipeline for `8x10g` is only allowed for non-commercial use.
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### HLS compilation
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Make HLS routines:
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```
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mkdir build
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cd build
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cmake ..
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make hls
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```
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### Synthesis
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Create PCIe `100g` bitstream with the following command:
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```
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mkdir build
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cd build
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cmake ..
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make pcie_100g
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```
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and `8x10g`:
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```
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mkdir build
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cd build
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cmake ..
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make pcie_8x10g
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```
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### When Vivado is not present
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During CMake execution, the following executables: `vivado` and `vitis_hls` must be present in the path.
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If not, build targets will not be generated, and such or similar error message will show up:
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```
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$ make pcie_100g
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make: *** No rule to make target 'pcie_100g'. Stop.
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```
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### Firmware releases
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The firmware is stable and is carried from version to version: the MCS files attached to a release
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are normally the ones from the release before it (see [Release contents](RELEASE_CONTENTS.md)). When
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it does need to change, it is rebuilt with the targets above on a machine with Vivado.
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## Frame generator
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The Jungfraujoch card is equipped with a frame generator. It allows simulating a JUNGFRAU detector without having access to such a system.
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It sits in parallel with the Ethernet MAC, so it is placed before the network stack and before any processing happening on the card.
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In the future a redirection will be possible to send the simulated stream through the 100G TX network link.
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Frame generator is written in HLS and controlled with AXI-Lite. |