21 lines
1019 B
Markdown
21 lines
1019 B
Markdown
# FPGA data flow
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The following steps are performed on FPGA (in the order of operation):
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1. UDP header decoding
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2. SLS detector header decoding
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3. State machine that controls data acquisition (start/stop/cancel)
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4. High-bandwidth memory cache to buffer network packets and reorder them to form full modules
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5. ADU histogram for JUNGFRAU
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6. Mask pixels from missing packets with special value
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7. Reorder lines for EIGER to form a proper module
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8. Mask pixels based on provided pixel mask
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9. JUNGFRAU conversion with gain and pedestal corrections
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10. Threshold to zero pixels below certain count value
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11. Integration according to predefined map (e.g., 1D azimuthal integration)
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12. Spot finding
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13. ROI calculation
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14. Image lossy compression using N*sqrt(pixel) values
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15. Send images, analysis results and metadata to host memory via PCI Express
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Each step has dedicated core, written in the high-level synthesis. Exact operation of cores for data analysis is explained in dedicated [document](FPGA_DATA_ANALYSIS.md). |