 leonarski_f
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9630c06b02
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Modifications necessary for the EIGER test
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2024-04-18 15:36:52 +02:00 |
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leonarski_f
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f5f86d9ab6
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Modifications in preparation to MAX IV experiment
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2024-01-27 21:23:56 +01:00 |
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leonarski_f
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427f0f7a45
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Fix tests + re-run FPGA synthesis
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2023-11-07 21:42:16 +01:00 |
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leonarski_f
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adc0a1bab6
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Fix tests + re-run FPGA synthesis
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2023-11-07 21:36:22 +01:00 |
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leonarski_f
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41985b6c29
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FPGA: Increase data width of conversion to 18-bit. This allows to use full unsigned precision + raw data are handled properly.
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2023-11-07 19:11:37 +01:00 |
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leonarski_f
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1b2b8f5863
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FPGA: Fix problems in summation and related cores
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2023-11-02 20:25:29 +01:00 |
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leonarski_f
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8cd0d497ad
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FPGA: Allow saving 32-bit unsigned.
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2023-11-02 13:32:29 +01:00 |
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leonarski_f
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961c17c4d0
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FPGA: data analysis is done based on 24-bit numbers - allowing frame summation
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2023-10-28 16:35:33 +02:00 |
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