2 Commits

Author	SHA1	Message	Date
Filip Leonarski	ec7278bd44	HLS: Changes to allow cosimulation with Vitis HLS	2023-10-18 14:44:30 +02:00
Filip Leonarski	98fe70315b	FPGA: add bitshuffle to HLS modules (don't integrate at the moment into the whole design)	2023-09-30 11:28:01 +02:00